Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912702900282.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Sudoku-PT-AN16, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912702900282
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 107M
-rw-r--r-- 1 mcc users 1.8M Feb 26 10:04 CTLCardinality.txt
-rw-r--r-- 1 mcc users 8.0M Feb 26 10:04 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7M Feb 26 09:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 22M Feb 26 09:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 1014K Feb 25 17:17 LTLCardinality.txt
-rw-r--r-- 1 mcc users 3.1M Feb 25 17:17 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.6M Feb 25 17:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 5.5M Feb 25 17:17 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.4M Feb 26 11:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15M Feb 26 11:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.9M Feb 26 10:17 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 32M Feb 26 10:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 142K Feb 25 17:17 UpperBounds.txt
-rw-r--r-- 1 mcc users 343K Feb 25 17:17 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 2.3M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-00
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-01
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-02
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-03
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-04
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-05
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-06
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-07
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-08
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-09
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-10
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-11
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-12
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-13
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-14
FORMULA_NAME Sudoku-PT-AN16-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679180913439

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Sudoku-PT-AN16
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-18 23:08:35] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-18 23:08:35] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-18 23:08:35] [INFO ] Load time of PNML (sax parser for PT used): 247 ms
[2023-03-18 23:08:35] [INFO ] Transformed 4864 places.
[2023-03-18 23:08:35] [INFO ] Transformed 4096 transitions.
[2023-03-18 23:08:35] [INFO ] Parsed PT model containing 4864 places and 4096 transitions and 16384 arcs in 445 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 360 ms.
Support contains 768 out of 4864 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 4864/4864 places, 4096/4096 transitions.
Reduce places removed 4096 places and 0 transitions.
Iterating post reduction 0 with 4096 rules applied. Total rules applied 4096 place count 768 transition count 4096
Applied a total of 4096 rules in 67 ms. Remains 768 /4864 variables (removed 4096) and now considering 4096/4096 (removed 0) transitions.
// Phase 1: matrix 4096 rows 768 cols
[2023-03-18 23:08:48] [INFO ] Computed 47 place invariants in 394 ms
[2023-03-18 23:08:48] [INFO ] Implicit Places using invariants in 717 ms returned []
[2023-03-18 23:08:48] [INFO ] Invariant cache hit.
[2023-03-18 23:08:49] [INFO ] Implicit Places using invariants and state equation in 1148 ms returned []
Implicit Place search using SMT with State Equation took 1893 ms to find 0 implicit places.
[2023-03-18 23:08:49] [INFO ] Invariant cache hit.
[2023-03-18 23:08:50] [INFO ] Dead Transitions using invariants and state equation in 1230 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 768/4864 places, 4096/4096 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3194 ms. Remains : 768/4864 places, 4096/4096 transitions.
Support contains 768 out of 768 places after structural reductions.
[2023-03-18 23:08:53] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-18 23:08:53] [INFO ] Flatten gal took : 1170 ms
FORMULA Sudoku-PT-AN16-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-18 23:09:08] [INFO ] Flatten gal took : 1502 ms
[2023-03-18 23:09:21] [INFO ] Input system was already deterministic with 4096 transitions.
Finished random walk after 223 steps, including 0 resets, run visited all 53 properties in 126 ms. (steps per millisecond=1 )
[2023-03-18 23:09:27] [INFO ] Flatten gal took : 905 ms
[2023-03-18 23:09:40] [INFO ] Flatten gal took : 1388 ms
[2023-03-18 23:09:54] [INFO ] Input system was already deterministic with 4096 transitions.
Computed a total of 768 stabilizing places and 4096 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 768 transition count 4096
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 3 formulas.
FORMULA Sudoku-PT-AN16-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 7 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:02] [INFO ] Flatten gal took : 213 ms
[2023-03-18 23:10:02] [INFO ] Flatten gal took : 290 ms
[2023-03-18 23:10:03] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 29 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:03] [INFO ] Flatten gal took : 194 ms
[2023-03-18 23:10:04] [INFO ] Flatten gal took : 261 ms
[2023-03-18 23:10:04] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:05] [INFO ] Flatten gal took : 207 ms
[2023-03-18 23:10:05] [INFO ] Flatten gal took : 289 ms
[2023-03-18 23:10:06] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 22 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:07] [INFO ] Flatten gal took : 232 ms
[2023-03-18 23:10:07] [INFO ] Flatten gal took : 312 ms
[2023-03-18 23:10:08] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 19 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:09] [INFO ] Flatten gal took : 211 ms
[2023-03-18 23:10:09] [INFO ] Flatten gal took : 275 ms
[2023-03-18 23:10:10] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 19 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:10] [INFO ] Flatten gal took : 127 ms
[2023-03-18 23:10:10] [INFO ] Flatten gal took : 143 ms
[2023-03-18 23:10:10] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:11] [INFO ] Flatten gal took : 261 ms
[2023-03-18 23:10:11] [INFO ] Flatten gal took : 359 ms
[2023-03-18 23:10:12] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 189 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 189 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:13] [INFO ] Flatten gal took : 106 ms
[2023-03-18 23:10:13] [INFO ] Flatten gal took : 105 ms
[2023-03-18 23:10:13] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 138 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 138 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:13] [INFO ] Flatten gal took : 99 ms
[2023-03-18 23:10:13] [INFO ] Flatten gal took : 109 ms
[2023-03-18 23:10:13] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 123 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 123 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:14] [INFO ] Flatten gal took : 100 ms
[2023-03-18 23:10:14] [INFO ] Flatten gal took : 111 ms
[2023-03-18 23:10:14] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 183 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 184 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:14] [INFO ] Flatten gal took : 98 ms
[2023-03-18 23:10:14] [INFO ] Flatten gal took : 110 ms
[2023-03-18 23:10:15] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 111 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 112 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:15] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-18 23:10:15] [INFO ] Flatten gal took : 98 ms
FORMULA Sudoku-PT-AN16-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-18 23:10:15] [INFO ] Flatten gal took : 111 ms
[2023-03-18 23:10:15] [INFO ] Input system was already deterministic with 4096 transitions.
Support contains 0 out of 768 places (down from 36) after GAL structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 128 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 128 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:15] [INFO ] Flatten gal took : 102 ms
[2023-03-18 23:10:15] [INFO ] Flatten gal took : 111 ms
[2023-03-18 23:10:16] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 112 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 113 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 23:10:16] [INFO ] Flatten gal took : 102 ms
[2023-03-18 23:10:16] [INFO ] Flatten gal took : 111 ms
[2023-03-18 23:10:16] [INFO ] Input system was already deterministic with 4096 transitions.
[2023-03-18 23:10:18] [INFO ] Flatten gal took : 1107 ms
[2023-03-18 23:10:27] [INFO ] Flatten gal took : 1159 ms
[2023-03-18 23:10:36] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 328 ms.
[2023-03-18 23:10:36] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 768 places, 4096 transitions and 12288 arcs took 13 ms.
Total runtime 121119 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Sudoku-PT-AN16
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

BK_STOP 1679181242559

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 480 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Sudoku-PT-AN16"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Sudoku-PT-AN16, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912702900282"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Sudoku-PT-AN16.tgz
mv Sudoku-PT-AN16 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;