Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912702600122.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Sudoku-COL-AN16, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912702600122
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 7.4K Feb 26 10:03 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 26 10:03 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Feb 26 09:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 61K Feb 26 09:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:17 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:17 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 17:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:17 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 11:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 125K Feb 26 11:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Feb 26 10:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 26 10:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:17 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:17 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 6.5K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-00
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-01
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-02
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-03
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-04
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-05
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-06
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-07
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-08
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-09
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-10
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-11
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-12
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-13
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-14
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679167873841

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Sudoku-COL-AN16
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-18 19:31:15] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-18 19:31:15] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-18 19:31:15] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-18 19:31:15] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-18 19:31:16] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 373 ms
[2023-03-18 19:31:16] [INFO ] Imported 4 HL places and 1 HL transitions for a total of 4864 PT places and 4096.0 transition bindings in 17 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 17 ms.
[2023-03-18 19:31:16] [INFO ] Built PT skeleton of HLPN with 4 places and 1 transitions 4 arcs in 3 ms.
[2023-03-18 19:31:16] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Computed a total of 4 stabilizing places and 1 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 4 transition count 1
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 13 formulas.
FORMULA Sudoku-COL-AN16-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Sudoku-COL-AN16-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 2 properties that can be checked using skeleton over-approximation.
Computed a total of 4 stabilizing places and 1 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 4 transition count 1
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Finished random walk after 0 steps, including 0 resets, run visited all 0 properties in 1 ms. (steps per millisecond=0 )
Finished probabilistic random walk after 0 steps, run visited all 0 properties in 0 ms. (steps per millisecond=0 )
[2023-03-18 19:31:16] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-18 19:31:16] [INFO ] Flatten gal took : 15 ms
FORMULA Sudoku-COL-AN16-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-18 19:31:16] [INFO ] Flatten gal took : 1 ms
Domain [N(16), N(16)] of place Rows breaks symmetries in sort N
[2023-03-18 19:31:16] [INFO ] Unfolded HLPN to a Petri net with 4864 places and 4096 transitions 16384 arcs in 66 ms.
[2023-03-18 19:31:16] [INFO ] Unfolded 13 HLPN properties in 35 ms.
Support contains 768 out of 4864 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 4864/4864 places, 4096/4096 transitions.
Reduce places removed 4096 places and 0 transitions.
Iterating post reduction 0 with 4096 rules applied. Total rules applied 4096 place count 768 transition count 4096
Applied a total of 4096 rules in 70 ms. Remains 768 /4864 variables (removed 4096) and now considering 4096/4096 (removed 0) transitions.
// Phase 1: matrix 4096 rows 768 cols
[2023-03-18 19:31:39] [INFO ] Computed 47 place invariants in 387 ms
[2023-03-18 19:31:39] [INFO ] Implicit Places using invariants in 654 ms returned []
[2023-03-18 19:31:39] [INFO ] Invariant cache hit.
[2023-03-18 19:31:40] [INFO ] Implicit Places using invariants and state equation in 879 ms returned []
Implicit Place search using SMT with State Equation took 1557 ms to find 0 implicit places.
[2023-03-18 19:31:40] [INFO ] Invariant cache hit.
[2023-03-18 19:31:41] [INFO ] Dead Transitions using invariants and state equation in 1304 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 768/4864 places, 4096/4096 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2935 ms. Remains : 768/4864 places, 4096/4096 transitions.
Support contains 768 out of 768 places after structural reductions.
[2023-03-18 19:31:47] [INFO ] Flatten gal took : 2394 ms
[2023-03-18 19:32:16] [INFO ] Flatten gal took : 3468 ms
[2023-03-18 19:32:45] [INFO ] Input system was already deterministic with 4096 transitions.
Incomplete random walk after 10000 steps, including 44 resets, run finished after 2624 ms. (steps per millisecond=3 ) properties (out of 13) seen :12
Interrupted Best-First random walk after 2001 steps, including 0 resets, run timeout after 5828 ms. (steps per millisecond=0 ) properties seen 0
Running SMT prover for 1 properties.
[2023-03-18 19:32:55] [INFO ] Invariant cache hit.
[2023-03-18 19:33:09] [INFO ] After 2295ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 13 simplifications.
[2023-03-18 19:33:27] [INFO ] Flatten gal took : 1969 ms
[2023-03-18 19:33:55] [INFO ] Flatten gal took : 3563 ms
[2023-03-18 19:34:23] [INFO ] Input system was already deterministic with 4096 transitions.
Computed a total of 768 stabilizing places and 4096 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 768 transition count 4096
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 1 formulas.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 8 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:38] [INFO ] Flatten gal took : 237 ms
[2023-03-18 19:34:39] [INFO ] Flatten gal took : 323 ms
[2023-03-18 19:34:39] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 29 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:40] [INFO ] Flatten gal took : 190 ms
[2023-03-18 19:34:40] [INFO ] Flatten gal took : 259 ms
[2023-03-18 19:34:41] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:41] [INFO ] Flatten gal took : 221 ms
[2023-03-18 19:34:42] [INFO ] Flatten gal took : 307 ms
[2023-03-18 19:34:42] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 22 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:44] [INFO ] Flatten gal took : 235 ms
[2023-03-18 19:34:44] [INFO ] Flatten gal took : 322 ms
[2023-03-18 19:34:45] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 18 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:45] [INFO ] Flatten gal took : 212 ms
[2023-03-18 19:34:46] [INFO ] Flatten gal took : 292 ms
[2023-03-18 19:34:46] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:47] [INFO ] Flatten gal took : 250 ms
[2023-03-18 19:34:47] [INFO ] Flatten gal took : 353 ms
[2023-03-18 19:34:48] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:49] [INFO ] Flatten gal took : 217 ms
[2023-03-18 19:34:49] [INFO ] Flatten gal took : 311 ms
[2023-03-18 19:34:50] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:50] [INFO ] Flatten gal took : 197 ms
[2023-03-18 19:34:51] [INFO ] Flatten gal took : 270 ms
[2023-03-18 19:34:51] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:52] [INFO ] Flatten gal took : 355 ms
[2023-03-18 19:34:53] [INFO ] Flatten gal took : 525 ms
[2023-03-18 19:34:54] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:57] [INFO ] Flatten gal took : 210 ms
[2023-03-18 19:34:57] [INFO ] Flatten gal took : 294 ms
[2023-03-18 19:34:58] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 9 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:34:59] [INFO ] Flatten gal took : 586 ms
[2023-03-18 19:35:00] [INFO ] Flatten gal took : 863 ms
[2023-03-18 19:35:02] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 7 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:35:03] [INFO ] Flatten gal took : 238 ms
[2023-03-18 19:35:04] [INFO ] Flatten gal took : 354 ms
[2023-03-18 19:35:04] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 768/768 places, 4096/4096 transitions.
[2023-03-18 19:35:05] [INFO ] Flatten gal took : 228 ms
[2023-03-18 19:35:05] [INFO ] Flatten gal took : 318 ms
[2023-03-18 19:35:06] [INFO ] Input system was already deterministic with 4096 transitions.
[2023-03-18 19:35:11] [INFO ] Flatten gal took : 3168 ms
[2023-03-18 19:35:37] [INFO ] Flatten gal took : 3131 ms
[2023-03-18 19:36:02] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 893 ms.
[2023-03-18 19:36:02] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 768 places, 4096 transitions and 12288 arcs took 14 ms.
Total runtime 286849 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Sudoku-COL-AN16
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

BK_STOP 1679168355072

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 489 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Sudoku-COL-AN16"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Sudoku-COL-AN16, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912702600122"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Sudoku-COL-AN16.tgz
mv Sudoku-COL-AN16 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;