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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r486-tall-167912702201196
Last Updated
May 14, 2023

About the Execution of LoLA for UtilityControlRoom-PT-Z4T4N04

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1699.680 130362.00 123561.00 432.80 F?FF?FF?FFFFFFFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r486-tall-167912702201196.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is UtilityControlRoom-PT-Z4T4N04, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912702201196
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 20K Feb 26 14:33 CTLCardinality.txt
-rw-r--r-- 1 mcc users 111K Feb 26 14:33 CTLCardinality.xml
-rw-r--r-- 1 mcc users 51K Feb 26 14:32 CTLFireability.txt
-rw-r--r-- 1 mcc users 184K Feb 26 14:32 CTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 53K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 14:37 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 26 14:37 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 94K Feb 26 14:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 357K Feb 26 14:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.4K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 128K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1679284990916

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z4T4N04
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT UtilityControlRoom-PT-Z4T4N04
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679285121278

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:184
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-PT-Z4T4N04-LTLFireability-00
lola: time limit : 94 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 1 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-00
lola: result : false
lola: markings : 20
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 7 (type EXCL) for 6 UtilityControlRoom-PT-Z4T4N04-LTLFireability-02
lola: time limit : 99 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 7 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-02
lola: result : false
lola: markings : 20
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 80 (type EXCL) for 19 UtilityControlRoom-PT-Z4T4N04-LTLFireability-05
lola: time limit : 105 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 81 (type SKEL/SRCH) for 53 UtilityControlRoom-PT-Z4T4N04-LTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 81 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-11
lola: result : false
lola: markings : 14
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 83 (type SKEL/SRCH) for 53 UtilityControlRoom-PT-Z4T4N04-LTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 83 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-11
lola: result : false
lola: markings : 39
lola: fired transitions : 39
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N04-LTLFireability-00: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N04-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-05: CONJ 0 3 1 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-11: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EG EXCL 5/163 2/32 UtilityControlRoom-PT-Z4T4N04-LTLFireability-05 380206 m, 76041 m/sec, 1748929 t fired, .

Time elapsed: 6 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N04-LTLFireability-00: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N04-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-05: CONJ 0 3 1 0 4 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-11: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EG EXCL 10/163 3/32 UtilityControlRoom-PT-Z4T4N04-LTLFireability-05 743908 m, 72740 m/sec, 3423003 t fired, .

Time elapsed: 11 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 80 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-05
lola: result : false
lola: markings : 856149
lola: fired transitions : 3940692
lola: time used : 11.000000
lola: memory pages used : 4
lola: LAUNCH task # 78 (type EXCL) for 77 UtilityControlRoom-PT-Z4T4N04-LTLFireability-15
lola: time limit : 170 sec
lola: memory limit: 32 pages
lola: FINISHED task # 78 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-15
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 75 (type EXCL) for 74 UtilityControlRoom-PT-Z4T4N04-LTLFireability-14
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: FINISHED task # 75 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-14
lola: result : false
lola: markings : 69
lola: fired transitions : 76
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 72 (type EXCL) for 71 UtilityControlRoom-PT-Z4T4N04-LTLFireability-13
lola: time limit : 188 sec
lola: memory limit: 32 pages
lola: FINISHED task # 72 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-13
lola: result : false
lola: markings : 46
lola: fired transitions : 46
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 69 (type EXCL) for 64 UtilityControlRoom-PT-Z4T4N04-LTLFireability-12
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 69 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-12
lola: result : false
lola: markings : 21
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 62 (type EXCL) for 53 UtilityControlRoom-PT-Z4T4N04-LTLFireability-11
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-11
lola: result : false
lola: markings : 20
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 50 UtilityControlRoom-PT-Z4T4N04-LTLFireability-10
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-10
lola: result : false
lola: markings : 20
lola: fired transitions : 20
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UtilityControlRoom-PT-Z4T4N04-LTLFireability-10: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-11: CONJ false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-12: CONJ false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-13: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-14: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-15: LTL true LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T4N04-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T4N04-LTLFireability-07: LTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N04-LTLFireability-00: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-01: LTL unknown AGGR
UtilityControlRoom-PT-Z4T4N04-LTLFireability-02: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-03: CONJ false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-04: LTL unknown AGGR
UtilityControlRoom-PT-Z4T4N04-LTLFireability-05: CONJ false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-06: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-07: LTL unknown AGGR
UtilityControlRoom-PT-Z4T4N04-LTLFireability-08: CONJ false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-09: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-10: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-11: CONJ false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-12: CONJ false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-13: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-14: LTL false LTL model checker
UtilityControlRoom-PT-Z4T4N04-LTLFireability-15: LTL true LTL model checker


Time elapsed: 131 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N04"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z4T4N04, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912702201196"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N04.tgz
mv UtilityControlRoom-PT-Z4T4N04 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;