fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r486-tall-167912702201146
Last Updated
May 14, 2023

About the Execution of LoLA for UtilityControlRoom-PT-Z2T4N08

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2535.220 160803.00 154120.00 170.00 ?TTFTTFFT?TTTFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r486-tall-167912702201146.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is UtilityControlRoom-PT-Z2T4N08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912702201146
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 28K Feb 26 14:36 CTLCardinality.txt
-rw-r--r-- 1 mcc users 150K Feb 26 14:36 CTLCardinality.xml
-rw-r--r-- 1 mcc users 37K Feb 26 14:34 CTLFireability.txt
-rw-r--r-- 1 mcc users 159K Feb 26 14:34 CTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 45K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 17K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 55K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 46K Feb 26 14:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 243K Feb 26 14:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 66K Feb 26 14:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 280K Feb 26 14:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.0K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.4K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 93K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679280423846

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z2T4N08
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT UtilityControlRoom-PT-Z2T4N08
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N08-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679280584649

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 68 (type SKEL/SRCH) for 6 UtilityControlRoom-PT-Z2T4N08-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 68 (type SKEL/SRCH) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-02
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: planning for (null) stopped (result already fixed).
lola: LAUNCH task # 16 (type EXCL) for 13 UtilityControlRoom-PT-Z2T4N08-CTLFireability-03
lola: time limit : 109 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 16 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-03
lola: result : false
lola: markings : 34
lola: fired transitions : 34
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 29 (type EXCL) for 28 UtilityControlRoom-PT-Z2T4N08-CTLFireability-04
lola: time limit : 112 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 70 (type FNDP) for 37 UtilityControlRoom-PT-Z2T4N08-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type EQUN) for 37 UtilityControlRoom-PT-Z2T4N08-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 73 (type SRCH) for 37 UtilityControlRoom-PT-Z2T4N08-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 70 (type FNDP) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-07
lola: result : true
lola: fired transitions : 7
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 71 (type EQUN) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-07 (obsolete)
lola: CANCELED task # 73 (type SRCH) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-07 (obsolete)
lola: FINISHED task # 71 (type EQUN) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-07
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: RELEASE
lola: FINISHED task # 73 (type SRCH) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-07
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: FINISHED task # 29 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-04
lola: result : true
lola: markings : 4823
lola: fired transitions : 8624
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 13 UtilityControlRoom-PT-Z2T4N08-CTLFireability-03
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 1 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/224 6/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-03 1114507 m, 222901 m/sec, 2076913 t fired, .

Time elapsed: 6 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 1 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/224 11/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-03 2174187 m, 211936 m/sec, 4230686 t fired, .

Time elapsed: 11 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 1 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/224 16/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-03 3183856 m, 201933 m/sec, 6332821 t fired, .

Time elapsed: 16 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 1 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 20/224 20/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-03 4169276 m, 197084 m/sec, 8395904 t fired, .

Time elapsed: 21 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 1 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/224 25/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-03 5140283 m, 194201 m/sec, 10461801 t fired, .

Time elapsed: 26 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 1 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 30/224 29/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-03 6080301 m, 188003 m/sec, 12590040 t fired, .

Time elapsed: 31 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 20 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 36 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 66 (type EXCL) for 65 UtilityControlRoom-PT-Z2T4N08-CTLFireability-15
lola: time limit : 237 sec
lola: memory limit: 32 pages
lola: FINISHED task # 66 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-15
lola: result : true
lola: markings : 165
lola: fired transitions : 331
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 56 UtilityControlRoom-PT-Z2T4N08-CTLFireability-12
lola: time limit : 254 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-12
lola: result : true
lola: markings : 877375
lola: fired transitions : 1563154
lola: time used : 3.000000
lola: memory pages used : 4
lola: LAUNCH task # 51 (type EXCL) for 50 UtilityControlRoom-PT-Z2T4N08-CTLFireability-10
lola: time limit : 273 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-10
lola: result : true
lola: markings : 1330
lola: fired transitions : 6120
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09
lola: time limit : 296 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 2/296 2/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 413329 m, 82665 m/sec, 1132629 t fired, .

Time elapsed: 41 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 7/296 4/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 876990 m, 92732 m/sec, 3688884 t fired, .

Time elapsed: 46 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 12/296 7/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 1331665 m, 90935 m/sec, 6176744 t fired, .

Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 17/296 9/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 1779027 m, 89472 m/sec, 8634152 t fired, .

Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 22/296 10/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 2219606 m, 88115 m/sec, 11069458 t fired, .

Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 27/296 12/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 2653463 m, 86771 m/sec, 13479249 t fired, .

Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 32/296 14/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 3082712 m, 85849 m/sec, 15865344 t fired, .

Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 37/296 16/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 3509426 m, 85342 m/sec, 18249314 t fired, .

Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 42/296 18/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 3930819 m, 84278 m/sec, 20611798 t fired, .

Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 47/296 20/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 4337801 m, 81396 m/sec, 22907496 t fired, .

Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 52/296 22/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 4742206 m, 80881 m/sec, 25204372 t fired, .

Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 57/296 24/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 5150066 m, 81572 m/sec, 27521443 t fired, .

Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 62/296 25/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 5553638 m, 80714 m/sec, 29838910 t fired, .

Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 67/296 27/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 5955609 m, 80394 m/sec, 32136803 t fired, .

Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 72/296 29/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 6356854 m, 80249 m/sec, 34437309 t fired, .

Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 77/296 31/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 6752905 m, 79210 m/sec, 36723117 t fired, .

Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 82/296 32/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 7148256 m, 79070 m/sec, 38999143 t fired, .

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 48 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ 0 2 0 0 5 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 35 (type EXCL) for 34 UtilityControlRoom-PT-Z2T4N08-CTLFireability-06
lola: time limit : 315 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-06
lola: result : false
lola: markings : 1699
lola: fired transitions : 3000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 6 UtilityControlRoom-PT-Z2T4N08-CTLFireability-02
lola: time limit : 347 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-02
lola: result : true
lola: markings : 71
lola: fired transitions : 71
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-PT-Z2T4N08-CTLFireability-01
lola: time limit : 386 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-01
lola: result : true
lola: markings : 391
lola: fired transitions : 537
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 63 (type EXCL) for 62 UtilityControlRoom-PT-Z2T4N08-CTLFireability-14
lola: time limit : 434 sec
lola: memory limit: 32 pages
lola: FINISHED task # 63 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-14
lola: result : true
lola: markings : 90353
lola: fired transitions : 206263
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 75 (type EXCL) for 59 UtilityControlRoom-PT-Z2T4N08-CTLFireability-13
lola: time limit : 496 sec
lola: memory limit: 32 pages
lola: FINISHED task # 75 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-13
lola: result : true
lola: markings : 31
lola: fired transitions : 31
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 UtilityControlRoom-PT-Z2T4N08-CTLFireability-08
lola: time limit : 579 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-08
lola: result : true
lola: markings : 34
lola: fired transitions : 34
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 13 UtilityControlRoom-PT-Z2T4N08-CTLFireability-03
lola: time limit : 694 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-03
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 13 UtilityControlRoom-PT-Z2T4N08-CTLFireability-03
lola: time limit : 868 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-03
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-PT-Z2T4N08-CTLFireability-00
lola: time limit : 1158 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG true state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F false state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/1158 6/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-00 1170040 m, 234008 m/sec, 4485799 t fired, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG true state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F false state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/1158 11/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-00 2487361 m, 263464 m/sec, 9119153 t fired, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG true state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F false state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/1158 16/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-00 3674891 m, 237506 m/sec, 13703638 t fired, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG true state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F false state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/1158 21/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-00 4801302 m, 225282 m/sec, 18317834 t fired, .

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG true state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F false state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/1158 26/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-00 6024319 m, 244603 m/sec, 22963776 t fired, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG true state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F false state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/1158 31/32 UtilityControlRoom-PT-Z2T4N08-CTLFireability-00 7153566 m, 225849 m/sec, 27609372 t fired, .

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG true state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F false state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 32 (type EXCL) for 31 UtilityControlRoom-PT-Z2T4N08-CTLFireability-05
lola: time limit : 1719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-05
lola: result : true
lola: markings : 199
lola: fired transitions : 307
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 UtilityControlRoom-PT-Z2T4N08-CTLFireability-11
lola: time limit : 3439 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-CTLFireability-11
lola: result : true
lola: markings : 137
lola: fired transitions : 266
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N08-CTLFireability-00: CTL unknown AGGR
UtilityControlRoom-PT-Z2T4N08-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-02: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-PT-Z2T4N08-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-07: CONJ false findpath
UtilityControlRoom-PT-Z2T4N08-CTLFireability-08: EG true state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-09: CTL unknown AGGR
UtilityControlRoom-PT-Z2T4N08-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-13: F false state space / EG
UtilityControlRoom-PT-Z2T4N08-CTLFireability-14: EGEF true CTL model checker
UtilityControlRoom-PT-Z2T4N08-CTLFireability-15: CTL true CTL model checker


Time elapsed: 161 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T4N08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z2T4N08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912702201146"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T4N08.tgz
mv UtilityControlRoom-PT-Z2T4N08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;