About the Execution of LoLA for UtilityControlRoom-COL-Z4T4N10
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
13595.724 | 664639.00 | 649581.00 | 1748.00 | T??T?T???????T?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r486-tall-167912702101082.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is UtilityControlRoom-COL-Z4T4N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912702101082
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 8.7K Feb 26 14:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 26 14:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Feb 26 14:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 78K Feb 26 14:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 17:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 17:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 10K Feb 26 15:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 26 15:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Feb 26 15:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 26 15:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:26 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:26 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z4T4N10-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679275798959
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-COL-Z4T4N10
Not applying reductions.
Model is COL
CTLFireability PT
[2023-03-20 01:30:00] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, CTLFireability, --reduce-single, STATESPACE]
[2023-03-20 01:30:00] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-20 01:30:00] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-20 01:30:00] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-20 01:30:00] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 404 ms
[2023-03-20 01:30:00] [INFO ] Imported 13 HL places and 12 HL transitions for a total of 376 PT places and 750.0 transition bindings in 12 ms.
Parsed 16 properties from file ./CTLFireability.xml in 15 ms.
[2023-03-20 01:30:00] [INFO ] Unfolded HLPN to a Petri net with 376 places and 750 transitions 2410 arcs in 127 ms.
[2023-03-20 01:30:00] [INFO ] Unfolded 16 HLPN properties in 6 ms.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 01:30:01] [INFO ] Reduced 30 identical enabling conditions.
Ensure Unique test removed 160 transitions
Reduce isomorphic transitions removed 160 transitions.
Drop transitions removed 40 transitions
Redundant transition composition rules discarded 40 transitions
[2023-03-20 01:30:01] [INFO ] Export to MCC of 16 properties in file ./CTLFireability.STATESPACE.xml took 57 ms.
[2023-03-20 01:30:01] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 376 places, 550 transitions and 1610 arcs took 8 ms.
Total runtime 905 ms.
starting LoLA
BK_INPUT UtilityControlRoom-COL-Z4T4N10
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfCTLFireability
FORMULA UtilityControlRoom-COL-Z4T4N10-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N10-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N10-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T4N10-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679276463598
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfCTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfCTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfCTLFireability/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01
lola: time limit : 178 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 5/223 3/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 493646 m, 98729 m/sec, 1763163 t fired, .
Time elapsed: 35 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 10/223 5/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 883592 m, 77989 m/sec, 3512586 t fired, .
Time elapsed: 40 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 15/223 7/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 1339909 m, 91263 m/sec, 5360500 t fired, .
Time elapsed: 45 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 20/223 9/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 1780902 m, 88198 m/sec, 7193480 t fired, .
Time elapsed: 50 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 25/223 11/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 2208622 m, 85544 m/sec, 9032801 t fired, .
Time elapsed: 55 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 30/223 13/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 2659704 m, 90216 m/sec, 10824268 t fired, .
Time elapsed: 60 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 35/223 15/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 3017530 m, 71565 m/sec, 12487518 t fired, .
Time elapsed: 65 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 40/223 17/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 3483649 m, 93223 m/sec, 14254003 t fired, .
Time elapsed: 70 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 45/223 18/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 3820286 m, 67327 m/sec, 15914534 t fired, .
Time elapsed: 75 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 50/223 21/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 4330673 m, 102077 m/sec, 17741672 t fired, .
Time elapsed: 80 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 55/223 22/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 4638688 m, 61603 m/sec, 19393469 t fired, .
Time elapsed: 85 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 60/223 24/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 5177799 m, 107822 m/sec, 21289122 t fired, .
Time elapsed: 90 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 65/223 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 5501782 m, 64796 m/sec, 23007129 t fired, .
Time elapsed: 95 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 70/223 28/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 6024744 m, 104592 m/sec, 24908555 t fired, .
Time elapsed: 100 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 75/223 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 6397598 m, 74570 m/sec, 26640112 t fired, .
Time elapsed: 105 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 EG EXCL 80/223 32/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 6825575 m, 85595 m/sec, 28354262 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15
lola: time limit : 232 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/232 9/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 1519628 m, 303925 m/sec, 1863462 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/232 11/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 1997287 m, 95531 m/sec, 3224214 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/232 14/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 2453545 m, 91251 m/sec, 4639633 t fired, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 20/232 16/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 2888774 m, 87045 m/sec, 6082362 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/232 18/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 3356599 m, 93565 m/sec, 7538734 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 30/232 20/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 3798701 m, 88420 m/sec, 9029233 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 35/232 22/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 4222683 m, 84796 m/sec, 10512085 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 40/232 25/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 4659040 m, 87271 m/sec, 12017997 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 45/232 27/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 5120137 m, 92219 m/sec, 13508679 t fired, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 50/232 29/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 5564933 m, 88959 m/sec, 15025023 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 55/232 31/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 5972601 m, 81533 m/sec, 16544449 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 46 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 43 (type EXCL) for 42 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14
lola: time limit : 244 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/244 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 1726911 m, 345382 m/sec, 1999248 t fired, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/244 14/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 2399855 m, 134588 m/sec, 3226959 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/244 16/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 2897449 m, 99518 m/sec, 4389589 t fired, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/244 19/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 3402449 m, 101000 m/sec, 5601742 t fired, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/244 21/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 3888824 m, 97275 m/sec, 6830791 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/244 23/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 4378662 m, 97967 m/sec, 8072857 t fired, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 35/244 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 4877178 m, 99703 m/sec, 9302756 t fired, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 40/244 28/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 5298552 m, 84274 m/sec, 10433850 t fired, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 45/244 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 5766636 m, 93616 m/sec, 11641514 t fired, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 40 (type EXCL) for 39 UtilityControlRoom-COL-Z4T4N10-CTLFireability-13
lola: time limit : 259 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-13
lola: result : true
lola: markings : 6437
lola: fired transitions : 10058
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12
lola: time limit : 281 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/281 6/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 840796 m, 168159 m/sec, 1541312 t fired, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/281 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 1582314 m, 148303 m/sec, 2936766 t fired, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/281 14/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 2288714 m, 141280 m/sec, 4273331 t fired, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/281 18/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 2966289 m, 135515 m/sec, 5563701 t fired, .
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/281 22/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 3633378 m, 133417 m/sec, 6832813 t fired, .
Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 30/281 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 4279876 m, 129299 m/sec, 8070531 t fired, .
Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 35/281 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 4915073 m, 127039 m/sec, 9286709 t fired, .
Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 37 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 34 (type EXCL) for 33 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11
lola: time limit : 303 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/303 5/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 633649 m, 126729 m/sec, 2007906 t fired, .
Time elapsed: 270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/303 8/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 1233593 m, 119988 m/sec, 3963888 t fired, .
Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/303 12/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 1818675 m, 117016 m/sec, 5874284 t fired, .
Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 20/303 16/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 2402230 m, 116711 m/sec, 7791195 t fired, .
Time elapsed: 285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 25/303 19/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 2961683 m, 111890 m/sec, 9670026 t fired, .
Time elapsed: 290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 30/303 23/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 3510517 m, 109766 m/sec, 11472099 t fired, .
Time elapsed: 295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 35/303 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 4083915 m, 114679 m/sec, 13334691 t fired, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 40/303 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 4658656 m, 114948 m/sec, 15211056 t fired, .
Time elapsed: 305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 34 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 30 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10
lola: time limit : 329 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/329 6/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 862372 m, 172474 m/sec, 1582051 t fired, .
Time elapsed: 315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/329 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 1611979 m, 149921 m/sec, 2993129 t fired, .
Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/329 15/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 2326523 m, 142908 m/sec, 4344465 t fired, .
Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/329 19/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 3010327 m, 136760 m/sec, 5648827 t fired, .
Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 25/329 22/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 3679616 m, 133857 m/sec, 6921004 t fired, .
Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 30/329 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 4329929 m, 130062 m/sec, 8166786 t fired, .
Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 35/329 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 4957605 m, 125535 m/sec, 9369299 t fired, .
Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 27 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09
lola: time limit : 361 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/361 3/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 462637 m, 92527 m/sec, 1353438 t fired, .
Time elapsed: 355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/361 5/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 908314 m, 89135 m/sec, 2659961 t fired, .
Time elapsed: 360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/361 7/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 1354954 m, 89328 m/sec, 3972559 t fired, .
Time elapsed: 365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/361 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 1783255 m, 85660 m/sec, 5225306 t fired, .
Time elapsed: 370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/361 12/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 2216857 m, 86720 m/sec, 6506057 t fired, .
Time elapsed: 375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 30/361 14/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 2634247 m, 83478 m/sec, 7741879 t fired, .
Time elapsed: 380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 35/361 16/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 3060704 m, 85291 m/sec, 9001871 t fired, .
Time elapsed: 385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 40/361 18/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 3473915 m, 82642 m/sec, 10226063 t fired, .
Time elapsed: 390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 45/361 20/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 3893494 m, 83915 m/sec, 11462760 t fired, .
Time elapsed: 395 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 50/361 22/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 4295018 m, 80304 m/sec, 12646778 t fired, .
Time elapsed: 400 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 55/361 24/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 4704428 m, 81882 m/sec, 13850904 t fired, .
Time elapsed: 405 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 60/361 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 5109125 m, 80939 m/sec, 15040366 t fired, .
Time elapsed: 410 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 65/361 28/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 5512152 m, 80605 m/sec, 16245163 t fired, .
Time elapsed: 415 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 70/361 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 5925024 m, 82574 m/sec, 17455613 t fired, .
Time elapsed: 420 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 75/361 32/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 6339594 m, 82914 m/sec, 18682320 t fired, .
Time elapsed: 425 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 430 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08
lola: time limit : 396 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/396 6/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 841962 m, 168392 m/sec, 1543609 t fired, .
Time elapsed: 435 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/396 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 1570965 m, 145800 m/sec, 2915086 t fired, .
Time elapsed: 440 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/396 14/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 2260895 m, 137986 m/sec, 4220960 t fired, .
Time elapsed: 445 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/396 18/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 2915221 m, 130865 m/sec, 5467056 t fired, .
Time elapsed: 450 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/396 22/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 3576649 m, 132285 m/sec, 6724826 t fired, .
Time elapsed: 455 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 30/396 25/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 4196934 m, 124057 m/sec, 7911493 t fired, .
Time elapsed: 460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 35/396 29/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 4803268 m, 121266 m/sec, 9073677 t fired, .
Time elapsed: 465 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 40/396 32/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 5415495 m, 122445 m/sec, 10245889 t fired, .
Time elapsed: 470 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 475 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06
lola: time limit : 446 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/446 4/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 650339 m, 130067 m/sec, 1581598 t fired, .
Time elapsed: 480 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/446 7/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 1223564 m, 114645 m/sec, 3183953 t fired, .
Time elapsed: 485 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/446 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 1809674 m, 117222 m/sec, 4823826 t fired, .
Time elapsed: 490 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/446 13/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 2437848 m, 125634 m/sec, 6396225 t fired, .
Time elapsed: 495 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/446 16/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 2979807 m, 108391 m/sec, 7896294 t fired, .
Time elapsed: 500 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/446 18/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 3528139 m, 109666 m/sec, 9452022 t fired, .
Time elapsed: 505 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/446 21/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 4154259 m, 125224 m/sec, 11033054 t fired, .
Time elapsed: 510 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 40/446 24/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 4744862 m, 118120 m/sec, 12645114 t fired, .
Time elapsed: 515 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 45/446 27/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 5317115 m, 114450 m/sec, 14239055 t fired, .
Time elapsed: 520 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 50/446 30/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 5926410 m, 121859 m/sec, 15823035 t fired, .
Time elapsed: 525 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 530 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 UtilityControlRoom-COL-Z4T4N10-CTLFireability-05
lola: time limit : 511 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-05
lola: result : true
lola: markings : 3128
lola: fired transitions : 4323
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04
lola: time limit : 613 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 4/613 6/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 898629 m, 179725 m/sec, 1368316 t fired, .
Time elapsed: 535 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 9/613 12/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 1788697 m, 178013 m/sec, 2726005 t fired, .
Time elapsed: 540 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 14/613 17/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 2660072 m, 174275 m/sec, 4060023 t fired, .
Time elapsed: 545 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 19/613 23/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 3503690 m, 168723 m/sec, 5346180 t fired, .
Time elapsed: 550 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/613 28/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 4349398 m, 169141 m/sec, 6639543 t fired, .
Time elapsed: 556 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 561 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02
lola: time limit : 759 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/759 6/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 1119029 m, 223805 m/sec, 2073380 t fired, .
Time elapsed: 566 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/759 11/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 2122970 m, 200788 m/sec, 4088455 t fired, .
Time elapsed: 571 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/759 16/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 3137981 m, 203002 m/sec, 6123098 t fired, .
Time elapsed: 576 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/759 21/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 4167390 m, 205881 m/sec, 8109863 t fired, .
Time elapsed: 581 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/759 26/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 5105985 m, 187719 m/sec, 10099025 t fired, .
Time elapsed: 586 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/759 31/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 6166050 m, 212013 m/sec, 12073061 t fired, .
Time elapsed: 591 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 596 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 UtilityControlRoom-COL-Z4T4N10-CTLFireability-03
lola: time limit : 1001 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-03
lola: result : true
lola: markings : 2315
lola: fired transitions : 4619
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-COL-Z4T4N10-CTLFireability-00
lola: time limit : 1502 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-00
lola: result : true
lola: markings : 41994
lola: fired transitions : 46092
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07
lola: time limit : 3004 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/3004 4/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 569641 m, 113928 m/sec, 2235074 t fired, .
Time elapsed: 601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/3004 7/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 1093221 m, 104716 m/sec, 4396798 t fired, .
Time elapsed: 606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/3004 10/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 1586477 m, 98651 m/sec, 6464256 t fired, .
Time elapsed: 611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/3004 12/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 2037419 m, 90188 m/sec, 8369667 t fired, .
Time elapsed: 616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 25/3004 15/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 2500580 m, 92632 m/sec, 10344691 t fired, .
Time elapsed: 621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 30/3004 17/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 2977519 m, 95387 m/sec, 12376035 t fired, .
Time elapsed: 626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 35/3004 20/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 3442675 m, 93031 m/sec, 14373256 t fired, .
Time elapsed: 631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 40/3004 22/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 3890041 m, 89473 m/sec, 16291947 t fired, .
Time elapsed: 636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 45/3004 25/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 4325544 m, 87100 m/sec, 18174741 t fired, .
Time elapsed: 641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 50/3004 27/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 4755507 m, 85992 m/sec, 20026577 t fired, .
Time elapsed: 646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 55/3004 29/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 5181665 m, 85231 m/sec, 21867849 t fired, .
Time elapsed: 651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 60/3004 32/32 UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 5603649 m, 84396 m/sec, 23706057 t fired, .
Time elapsed: 656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 22 (type EXCL) for UtilityControlRoom-COL-Z4T4N10-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T4N10-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-01: EG unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-02: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-04: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-06: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-07: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-08: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-09: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-10: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-11: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-12: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-COL-Z4T4N10-CTLFireability-14: CTL unknown AGGR
UtilityControlRoom-COL-Z4T4N10-CTLFireability-15: CTL unknown AGGR
Time elapsed: 661 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z4T4N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-COL-Z4T4N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912702101082"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z4T4N10.tgz
mv UtilityControlRoom-COL-Z4T4N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;