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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r486-tall-167912701900914
Last Updated
May 14, 2023

About the Execution of LoLA for TwoPhaseLocking-PT-nC05000vD

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2319.544 75224.00 62917.00 389.50 FFF?TF??TF?T?FF? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r486-tall-167912701900914.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is TwoPhaseLocking-PT-nC05000vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912701900914
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 464K
-rw-r--r-- 1 mcc users 7.0K Feb 25 17:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 17:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 25 17:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 17:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 125K Feb 25 17:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 25 17:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679257062851

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC05000vD
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC05000vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679257138075

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC05000vD-CTLFireability-02
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-02
lola: result : false
lola: markings : 10001
lola: fired transitions : 20006
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 46 (type EXCL) for 45 TwoPhaseLocking-PT-nC05000vD-CTLFireability-15
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/240 19/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-15 4303539 m, 860707 m/sec, 8501034 t fired, .

Time elapsed: 5 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 46 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: result : false
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lola: FINISHED task # 40 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-13
lola: result : false
lola: markings : 3136251
lola: fired transitions : 3141252
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lola: LAUNCH task # 37 (type EXCL) for 36 TwoPhaseLocking-PT-nC05000vD-CTLFireability-12
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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37 CTL EXCL 3/299 13/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-12 2954254 m, 590850 m/sec, 7381695 t fired, .

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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37 CTL EXCL 8/299 31/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-12 7152517 m, 839652 m/sec, 16975301 t fired, .

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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lola: FINISHED task # 28 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-09
lola: result : false
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lola: fired transitions : 25001
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lola: FINISHED task # 25 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-08
lola: result : true
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lola: fired transitions : 67503
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lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC05000vD-CTLFireability-04
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lola: FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-04
lola: result : true
lola: markings : 10002
lola: fired transitions : 22504
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lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC05000vD-CTLFireability-01
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lola: result : false
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lola: fired transitions : 5005
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lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC05000vD-CTLFireability-00
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lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-00
lola: result : false
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lola: fired transitions : 10004
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 EG EXCL 4/595 21/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-10 5861502 m, 1172300 m/sec, 9762227 t fired, .

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 EG EXCL 5/713 22/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-03 5968879 m, 1193775 m/sec, 9941242 t fired, .

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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22 AGEF EXCL 5/888 23/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-07 6239734 m, 1247946 m/sec, 10913513 t fired, .

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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lola: FINISHED task # 34 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-11
lola: result : true
lola: markings : 10009
lola: fired transitions : 75046
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/1772 9/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-06 2010938 m, 402187 m/sec, 6581823 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/1772 17/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-06 3926294 m, 383071 m/sec, 12883549 t fired, .

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/1772 25/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-06 5894130 m, 393567 m/sec, 19351563 t fired, .

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lola: CANCELED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC05000vD-CTLFireability-05
lola: time limit : 3525 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-05
lola: result : false
lola: markings : 19997
lola: fired transitions : 40004
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC05000vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC05000vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912701900914"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC05000vD.tgz
mv TwoPhaseLocking-PT-nC05000vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;