fond

jQuery Multi Level CSS Menu Css3Menu.com

Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r486-tall-167912701800858
Last Updated
May 14, 2023

About the Execution of LoLA for TwoPhaseLocking-PT-nC00200vN

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3434.287 160267.00 141982.00 395.10 F?T??FTFF?F?T??F normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r486-tall-167912701800858.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is TwoPhaseLocking-PT-nC00200vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912701800858
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 9.1K Feb 25 17:35 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K Feb 25 17:35 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.5K Feb 25 17:33 CTLFireability.txt
-rw-r--r-- 1 mcc users 34K Feb 25 17:33 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:23 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:23 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 25 17:35 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 159K Feb 25 17:35 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Feb 25 17:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 25 17:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:23 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679255110734

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC00200vN
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC00200vN
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA TwoPhaseLocking-PT-nC00200vN-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vN-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vN-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vN-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vN-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vN-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vN-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vN-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vN-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679255271001

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 37 (type EXCL) for 36 TwoPhaseLocking-PT-nC00200vN-CTLFireability-12
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 37 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-12
lola: result : true
lola: markings : 697201
lola: fired transitions : 2783451
lola: time used : 1.000000
lola: memory pages used : 3
lola: LAUNCH task # 46 (type EXCL) for 45 TwoPhaseLocking-PT-nC00200vN-CTLFireability-15
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-15
lola: result : false
lola: markings : 403
lola: fired transitions : 405
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 TwoPhaseLocking-PT-nC00200vN-CTLFireability-09
lola: time limit : 257 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 4/257 6/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-09 1453774 m, 290754 m/sec, 5476323 t fired, .

Time elapsed: 5 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 9/257 18/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-09 4264181 m, 562081 m/sec, 15240310 t fired, .

Time elapsed: 10 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 14/257 28/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-09 6784889 m, 504141 m/sec, 23783409 t fired, .

Time elapsed: 15 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC00200vN-CTLFireability-06
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-06
lola: result : true
lola: markings : 201
lola: fired transitions : 200
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC00200vN-CTLFireability-05
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-05
lola: result : false
lola: markings : 199
lola: fired transitions : 398
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC00200vN-CTLFireability-04
lola: time limit : 325 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/325 15/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-04 3631192 m, 726238 m/sec, 7002376 t fired, .

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/325 30/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-04 7175638 m, 708889 m/sec, 13094653 t fired, .

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC00200vN-CTLFireability-02
lola: time limit : 356 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-02
lola: result : true
lola: markings : 1622016
lola: fired transitions : 4055006
lola: time used : 2.000000
lola: memory pages used : 7
lola: LAUNCH task # 48 (type EXCL) for 30 TwoPhaseLocking-PT-nC00200vN-CTLFireability-10
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-10
lola: result : true
lola: markings : 1035450
lola: fired transitions : 2727097
lola: time used : 1.000000
lola: memory pages used : 4
lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC00200vN-CTLFireability-07
lola: time limit : 445 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-07
lola: result : false
lola: markings : 15451
lola: fired transitions : 25449
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 24 TwoPhaseLocking-PT-nC00200vN-CTLFireability-08
lola: time limit : 508 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-08
lola: result : true
lola: markings : 20401
lola: fired transitions : 40499
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC00200vN-CTLFireability-00
lola: time limit : 593 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-00
lola: result : false
lola: markings : 603
lola: fired transitions : 603
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 TwoPhaseLocking-PT-nC00200vN-CTLFireability-11
lola: time limit : 712 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 2/712 4/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-11 971353 m, 194270 m/sec, 3173447 t fired, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 7/712 11/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-11 2709894 m, 347708 m/sec, 9914783 t fired, .

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 12/712 18/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-11 4231288 m, 304278 m/sec, 16059975 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 17/712 23/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-11 5678063 m, 289355 m/sec, 21914995 t fired, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 22/712 29/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-11 7064079 m, 277203 m/sec, 27597341 t fired, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 34 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 43 (type EXCL) for 42 TwoPhaseLocking-PT-nC00200vN-CTLFireability-14
lola: time limit : 883 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/883 18/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-14 4450071 m, 890014 m/sec, 10711844 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 40 (type EXCL) for 39 TwoPhaseLocking-PT-nC00200vN-CTLFireability-13
lola: time limit : 1175 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/1175 8/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-13 1945061 m, 389012 m/sec, 7572579 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/1175 14/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-13 3480595 m, 307106 m/sec, 13991525 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/1175 20/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-13 4932590 m, 290399 m/sec, 20031951 t fired, .

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/1175 26/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-13 6314930 m, 276468 m/sec, 25857270 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 25/1175 31/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-13 7662487 m, 269511 m/sec, 31516577 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 40 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC00200vN-CTLFireability-03
lola: time limit : 1747 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/1747 11/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-03 2493776 m, 498755 m/sec, 12092810 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/1747 20/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-03 4903166 m, 481878 m/sec, 23571296 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/1747 30/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-03 7337922 m, 486951 m/sec, 34755520 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC00200vN-CTLFireability-01
lola: time limit : 3475 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/3475 7/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-01 1616936 m, 323387 m/sec, 8857384 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/3475 12/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-01 2894510 m, 255514 m/sec, 16509570 t fired, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/3475 17/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-01 4119212 m, 244940 m/sec, 23764225 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/3475 22/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-01 5304255 m, 237008 m/sec, 30793861 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/3475 26/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-01 6452308 m, 229610 m/sec, 37661839 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/3475 31/32 TwoPhaseLocking-PT-nC00200vN-CTLFireability-01 7573243 m, 224187 m/sec, 44381197 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-01: CTL unknown AGGR
TwoPhaseLocking-PT-nC00200vN-CTLFireability-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-03: CTL unknown AGGR
TwoPhaseLocking-PT-nC00200vN-CTLFireability-04: CTL unknown AGGR
TwoPhaseLocking-PT-nC00200vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-07: EG false state space / EG
TwoPhaseLocking-PT-nC00200vN-CTLFireability-08: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC00200vN-CTLFireability-10: EFAG false tscc_search
TwoPhaseLocking-PT-nC00200vN-CTLFireability-11: CTL unknown AGGR
TwoPhaseLocking-PT-nC00200vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vN-CTLFireability-13: CTL unknown AGGR
TwoPhaseLocking-PT-nC00200vN-CTLFireability-14: CTL unknown AGGR
TwoPhaseLocking-PT-nC00200vN-CTLFireability-15: CTL false CTL model checker


Time elapsed: 160 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00200vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC00200vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912701800858"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00200vN.tgz
mv TwoPhaseLocking-PT-nC00200vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;