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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r486-tall-167912701800850
Last Updated
May 14, 2023

About the Execution of LoLA for TwoPhaseLocking-PT-nC00200vD

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1413.915 43337.00 36343.00 197.50 TTFTT?FTT??FTTFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r486-tall-167912701800850.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is TwoPhaseLocking-PT-nC00200vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912701800850
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 476K
-rw-r--r-- 1 mcc users 9.2K Feb 25 17:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K Feb 25 17:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 25 17:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 17:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:23 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:23 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 17:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 139K Feb 25 17:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Feb 25 17:52 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 25 17:52 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:23 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC00200vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679253245880

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC00200vD
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC00200vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00200vD-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679253289217

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC00200vD-CTLFireability-01
lola: time limit : 109 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 84 (type FNDP) for 9 TwoPhaseLocking-PT-nC00200vD-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type EQUN) for 9 TwoPhaseLocking-PT-nC00200vD-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type SRCH) for 9 TwoPhaseLocking-PT-nC00200vD-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 87 (type SRCH) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-03
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-85.sara.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 84 (type FNDP) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-03
lola: result : true
lola: fired transitions : 99
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-01
lola: result : true
lola: markings : 5560
lola: fired transitions : 6869
lola: time used : 1.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: CANCELED task # 85 (type EQUN) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-03 (obsolete)
lola: LAUNCH task # 76 (type EXCL) for 75 TwoPhaseLocking-PT-nC00200vD-CTLFireability-13
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 88 (type FNDP) for 52 TwoPhaseLocking-PT-nC00200vD-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type EQUN) for 52 TwoPhaseLocking-PT-nC00200vD-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 91 (type SRCH) for 52 TwoPhaseLocking-PT-nC00200vD-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 85 (type EQUN) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-03
lola: result : unknown
lola: FINISHED task # 76 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-13
lola: result : true
lola: markings : 301
lola: fired transitions : 499
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 TwoPhaseLocking-PT-nC00200vD-CTLFireability-08
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: FINISHED task # 91 (type SRCH) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 37 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-08
lola: result : true
lola: markings : 404
lola: fired transitions : 1105
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lola: rewrite Frontend/Parser/formula_rewrite.k:659
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: FINISHED task # 88 (type FNDP) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-12
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:810
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:664
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 90 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-12
lola: result : true
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: FINISHED task # 89 (type EQUN) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-12
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 48 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-11
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-03: DISJ true findpath
TwoPhaseLocking-PT-nC00200vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-05: DISJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-12: DISJ 0 1 0 0 11 0 0 6
TwoPhaseLocking-PT-nC00200vD-CTLFireability-15: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 4/299 16/32 TwoPhaseLocking-PT-nC00200vD-CTLFireability-10 3892215 m, 778443 m/sec, 9363337 t fired, .

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-03: DISJ true findpath
TwoPhaseLocking-PT-nC00200vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-05: DISJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-12: DISJ 0 1 0 0 11 0 0 6
TwoPhaseLocking-PT-nC00200vD-CTLFireability-15: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 9/299 31/32 TwoPhaseLocking-PT-nC00200vD-CTLFireability-10 7488089 m, 719174 m/sec, 18122837 t fired, .

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-03: DISJ true findpath
TwoPhaseLocking-PT-nC00200vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-05: DISJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-12: DISJ 0 1 0 0 11 0 0 6
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TwoPhaseLocking-PT-nC00200vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-03: DISJ true findpath
TwoPhaseLocking-PT-nC00200vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-05: DISJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-12: DISJ 0 1 0 0 11 0 0 6
TwoPhaseLocking-PT-nC00200vD-CTLFireability-15: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/325 15/32 TwoPhaseLocking-PT-nC00200vD-CTLFireability-09 3593938 m, 718787 m/sec, 9227980 t fired, .

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-03: DISJ true findpath
TwoPhaseLocking-PT-nC00200vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-05: DISJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00200vD-CTLFireability-12: DISJ 0 1 0 0 11 0 0 6
TwoPhaseLocking-PT-nC00200vD-CTLFireability-15: EG 0 1 0 0 1 0 0 0

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40 CTL EXCL 10/325 25/32 TwoPhaseLocking-PT-nC00200vD-CTLFireability-09 6023208 m, 485854 m/sec, 16307562 t fired, .

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-03: DISJ true findpath
TwoPhaseLocking-PT-nC00200vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-05: DISJ 0 3 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00200vD-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-12: DISJ 0 1 0 0 11 0 0 6
TwoPhaseLocking-PT-nC00200vD-CTLFireability-15: EG 0 1 0 0 1 0 0 0

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lola: result : true
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TwoPhaseLocking-PT-nC00200vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-03: DISJ true findpath
TwoPhaseLocking-PT-nC00200vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-05: DISJ 0 2 1 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC00200vD-CTLFireability-12: DISJ 0 1 0 0 11 0 0 6
TwoPhaseLocking-PT-nC00200vD-CTLFireability-15: EG 0 1 0 0 1 0 0 0

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28 CTL EXCL 5/446 23/32 TwoPhaseLocking-PT-nC00200vD-CTLFireability-05 5442255 m, 1088451 m/sec, 8319080 t fired, .

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-03: DISJ true findpath
TwoPhaseLocking-PT-nC00200vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-14: CTL false CTL model checker

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TwoPhaseLocking-PT-nC00200vD-CTLFireability-12: DISJ 0 1 0 0 11 0 0 6
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# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 26 (type EXCL) for 19 TwoPhaseLocking-PT-nC00200vD-CTLFireability-05
lola: time limit : 508 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-05
lola: result : false
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC00200vD-CTLFireability-02
lola: time limit : 712 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-02
lola: result : false
lola: markings : 401
lola: fired transitions : 803
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 101 (type EXCL) for 45 TwoPhaseLocking-PT-nC00200vD-CTLFireability-11
lola: time limit : 890 sec
lola: memory limit: 32 pages
lola: FINISHED task # 101 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-11
lola: result : true
lola: markings : 15251
lola: fired transitions : 25150
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 82 (type EXCL) for 81 TwoPhaseLocking-PT-nC00200vD-CTLFireability-15
lola: time limit : 1186 sec
lola: memory limit: 32 pages
lola: FINISHED task # 82 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-15
lola: result : false
lola: markings : 201
lola: fired transitions : 200
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 92 (type EXCL) for 52 TwoPhaseLocking-PT-nC00200vD-CTLFireability-12
lola: time limit : 1780 sec
lola: memory limit: 32 pages
lola: FINISHED task # 92 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-12
lola: result : false
lola: markings : 307
lola: fired transitions : 308
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 TwoPhaseLocking-PT-nC00200vD-CTLFireability-04
lola: time limit : 3560 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for TwoPhaseLocking-PT-nC00200vD-CTLFireability-04
lola: result : true
lola: markings : 1025251
lola: fired transitions : 4055452
lola: time used : 4.000000
lola: memory pages used : 5
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00200vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-03: DISJ true findpath
TwoPhaseLocking-PT-nC00200vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-05: DISJ unknown DISJ
TwoPhaseLocking-PT-nC00200vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC00200vD-CTLFireability-10: CTL unknown AGGR
TwoPhaseLocking-PT-nC00200vD-CTLFireability-11: DISJ false DISJ
TwoPhaseLocking-PT-nC00200vD-CTLFireability-12: DISJ true tscc_search
TwoPhaseLocking-PT-nC00200vD-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-14: CTL false CTL model checker
TwoPhaseLocking-PT-nC00200vD-CTLFireability-15: EG false state space / EG


Time elapsed: 44 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00200vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC00200vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912701800850"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00200vD.tgz
mv TwoPhaseLocking-PT-nC00200vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;