About the Execution of LoLA for TwoPhaseLocking-PT-nC00100vD
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
6145.176 | 200415.00 | 186446.00 | 565.80 | ?TTFF??T?FFT??TF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r486-tall-167912701800834.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is TwoPhaseLocking-PT-nC00100vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912701800834
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 456K
-rw-r--r-- 1 mcc users 7.2K Feb 25 17:31 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 25 17:31 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 17:30 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 25 17:30 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:23 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:23 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 131K Feb 25 17:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 25 17:31 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 25 17:31 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:23 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:23 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679252703002
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC00100vD
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC00100vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679252903417
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC00100vD-CTLFireability-02
lola: time limit : 150 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-02
lola: result : true
lola: markings : 3876
lola: fired transitions : 6325
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 40 (type EXCL) for 27 TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 25 (type EXCL) for 24 TwoPhaseLocking-PT-nC00100vD-CTLFireability-08
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 68 (type FNDP) for 27 TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type EQUN) for 27 TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SRCH) for 27 TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 71 (type SRCH) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 73 (type FNDP) for 27 TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 68 (type FNDP) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 69 (type EQUN) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09 (obsolete)
lola: LAUNCH task # 74 (type EQUN) for 27 TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 76 (type SRCH) for 27 TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 69 (type EQUN) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: result : unknown
lola: FINISHED task # 73 (type FNDP) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: result : true
lola: fired transitions : 49
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 74 (type EQUN) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09 (obsolete)
lola: CANCELED task # 76 (type SRCH) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09 (obsolete)
lola: FINISHED task # 76 (type SRCH) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-74.sara.
lola: FINISHED task # 74 (type EQUN) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-09
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/225 8/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-08 1897627 m, 379525 m/sec, 7759271 t fired, .
Time elapsed: 5 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/225 14/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-08 3467750 m, 314024 m/sec, 14423851 t fired, .
Time elapsed: 10 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/225 20/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-08 4946456 m, 295741 m/sec, 20764191 t fired, .
Time elapsed: 15 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/225 26/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-08 6314525 m, 273613 m/sec, 26694194 t fired, .
Time elapsed: 20 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/225 31/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-08 7601324 m, 257359 m/sec, 32294011 t fired, .
Time elapsed: 25 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 60 (type EXCL) for 57 TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
lola: time limit : 238 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
lola: result : true
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 54 TwoPhaseLocking-PT-nC00100vD-CTLFireability-14
lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-14
lola: result : true
lola: markings : 1693202
lola: fired transitions : 4217607
lola: time used : 2.000000
lola: memory pages used : 7
lola: LAUNCH task # 52 (type EXCL) for 51 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13
lola: time limit : 274 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 3/274 3/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 665062 m, 133012 m/sec, 2891004 t fired, .
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# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 8/274 8/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 1764140 m, 219815 m/sec, 7744251 t fired, .
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# running tasks: 1 of 4 Visible: 16
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 13/274 11/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 2736490 m, 194470 m/sec, 12056363 t fired, .
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# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 18/274 15/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 3623038 m, 177309 m/sec, 15995174 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 23/274 19/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 4516858 m, 178764 m/sec, 19972342 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 28/274 22/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 5365476 m, 169723 m/sec, 23752598 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 33/274 25/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 6203314 m, 167567 m/sec, 27487192 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 38/274 29/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 7048917 m, 169120 m/sec, 31256382 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 43/274 32/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 7859243 m, 162065 m/sec, 34866432 t fired, .
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lola: CANCELED task # 52 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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lola: LAUNCH task # 49 (type EXCL) for 48 TwoPhaseLocking-PT-nC00100vD-CTLFireability-12
lola: time limit : 293 sec
lola: memory limit: 32 pages
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 5/293 13/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-12 3188551 m, 637710 m/sec, 6983506 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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49 CTL EXCL 10/293 21/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-12 4998500 m, 361989 m/sec, 13286398 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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49 CTL EXCL 15/293 26/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-12 6281798 m, 256659 m/sec, 19455086 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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49 CTL EXCL 20/293 29/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-12 7181908 m, 180022 m/sec, 25461324 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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49 CTL EXCL 25/293 32/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-12 7896329 m, 142884 m/sec, 31351363 t fired, .
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lola: CANCELED task # 49 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-12 (memory limit exceeded)
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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lola: LAUNCH task # 43 (type EXCL) for 42 TwoPhaseLocking-PT-nC00100vD-CTLFireability-10
lola: time limit : 317 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-10
lola: result : false
lola: markings : 2851
lola: fired transitions : 18248
lola: time used : 0.000000
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lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC00100vD-CTLFireability-07
lola: time limit : 349 sec
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lola: FINISHED task # 22 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-07
lola: result : true
lola: markings : 2702
lola: fired transitions : 4624
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lola: LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC00100vD-CTLFireability-06
lola: time limit : 387 sec
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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19 CTL EXCL 5/387 9/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-06 2171516 m, 434303 m/sec, 6777062 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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19 CTL EXCL 20/387 28/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-06 6776238 m, 287780 m/sec, 22550954 t fired, .
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lola: CANCELED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-06 (memory limit exceeded)
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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lola: LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05
lola: time limit : 433 sec
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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16 CTL EXCL 5/433 7/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 1499396 m, 299879 m/sec, 7204832 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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16 CTL EXCL 10/433 11/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 2734174 m, 246955 m/sec, 13461495 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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16 CTL EXCL 15/433 16/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 3875761 m, 228317 m/sec, 19352827 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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16 CTL EXCL 30/433 29/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-05 7072834 m, 202881 m/sec, 36125177 t fired, .
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ 0 2 0 0 4 0 0 0
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lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC00100vD-CTLFireability-03
lola: time limit : 490 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-03
lola: result : false
lola: markings : 98
lola: fired transitions : 98
lola: time used : 0.000000
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lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC00100vD-CTLFireability-01
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lola: FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-01
lola: result : true
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lola: fired transitions : 705
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lola: LAUNCH task # 64 (type EXCL) for 57 TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
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lola: FINISHED task # 64 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
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lola: FINISHED task # 66 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-15
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lola: FINISHED task # 46 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-11
lola: result : true
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lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC00100vD-CTLFireability-04
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lola: result : false
lola: markings : 100
lola: fired transitions : 102
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00
lola: time limit : 3430 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/3430 8/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 1845245 m, 369049 m/sec, 7585420 t fired, .
Time elapsed: 175 secs. Pages in use: 32
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/3430 14/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 3367050 m, 304361 m/sec, 14068917 t fired, .
Time elapsed: 180 secs. Pages in use: 32
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/3430 20/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 4772599 m, 281109 m/sec, 20171241 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/3430 25/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 6082312 m, 261942 m/sec, 25938826 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/3430 30/32 TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 7331292 m, 249796 m/sec, 31520541 t fired, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00100vD-CTLFireability-00: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-02: EG true state space / EG
TwoPhaseLocking-PT-nC00100vD-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-05: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-08: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-09: CONJ false findpath
TwoPhaseLocking-PT-nC00100vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-12: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-13: CTL unknown AGGR
TwoPhaseLocking-PT-nC00100vD-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC00100vD-CTLFireability-15: CONJ false CONJ
Time elapsed: 200 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00100vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC00100vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912701800834"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00100vD.tgz
mv TwoPhaseLocking-PT-nC00100vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;