About the Execution of 2022-gold for StigmergyCommit-PT-07a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16227.075 | 3592269.00 | 9677012.00 | 6702.70 | FFTFF?TFTTFTFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r478-smll-167912663800356.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool gold2022
Input is StigmergyCommit-PT-07a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r478-smll-167912663800356
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.9M
-rw-r--r-- 1 mcc users 5.4K Feb 26 11:00 CTLCardinality.txt
-rw-r--r-- 1 mcc users 53K Feb 26 11:00 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 26 10:59 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 26 10:59 CTLFireability.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.4M Mar 5 18:23 model.pnml
-rw-r--r-- 1 mcc users 15K Feb 26 11:01 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 164K Feb 26 11:01 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.0K Feb 26 11:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 26 11:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:12 UpperBounds.xml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-00
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-01
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-02
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-03
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-04
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-05
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-06
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-07
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-08
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-09
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-10
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-11
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-12
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-13
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-14
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679605837554
gold2022
Got BK_BIN_PATH=/home/mcc/BenchKit/bin/
---> gold2022 --- TAPAAL v5
Setting MODEL_PATH=.
Setting VERIFYPN=/home/mcc/BenchKit/bin/verifypn
Got BK_TIME_CONFINEMENT=3600
Setting TEMPDIR=/home/mcc/BenchKit/bin/tmp
Got BK_MEMORY_CONFINEMENT=16384
Limiting to 16265216 kB
Total timeout: 3590
Time left: 3590
*************************************
* TAPAAL verifying CTLFireability *
*************************************
TEMPDIR=/home/mcc/BenchKit/bin/tmp
QF=/home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR
MF=/home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S
Time left: 3590
---------------------------------------------------
Step -1: Stripping Colors
---------------------------------------------------
Verifying stripped models (16 in total)
/home/mcc/BenchKit/bin/verifypn -n -c -q 718 -l 29 -d 299 -z 4 -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
CPN OverApproximation is only usable on colored models
Time left: 3589
---------------------------------------------------
Step 0: Parallel Simplification
---------------------------------------------------
Doing parallel simplification (16 in total)
Total simplification timout is 718 -- reduction timeout is 299
timeout 3589 /home/mcc/BenchKit/bin/verifypn -n -q 718 -l 29 -d 299 -z 4 -s OverApprox --binary-query-io 2 --write-simplified /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --write-reduced /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
Time left: 3581
---------------------------------------------------
Step 1: Parallel processing
---------------------------------------------------
Doing parallel verification of individual queries (16 in total)
Each query is verified by 4 parallel strategies for 299 seconds
------------------- QUERY 1 ----------------------
Solution found by parallel processing (step 1)
Search strategy option was ignored as the TAR engine is called.
Query index 0 was solved
Query is NOT satisfied.
Solved using Trace Abstraction Refinement
Spent 0.012067 on verification
@@@0.21,10868@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 1 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING STRUCTURAL_REDUCTION QUERY_REDUCTION SAT_SMT TRACE_ABSTRACTION_REFINEMENT
Time left: 3580
------------------- QUERY 2 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is satisfied.
Spent 0.068224 on verification
@@@0.18,61112@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 2 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3580
------------------- QUERY 3 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 0.0574 on verification
@@@0.17,61296@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 3 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3579
------------------- QUERY 4 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 0.067405 on verification
@@@0.18,61296@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 4 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3579
------------------- QUERY 5 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 0.060571 on verification
@@@0.17,61156@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 5 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3579
------------------- QUERY 6 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is satisfied.
Spent 0.310081 on verification
@@@0.43,71444@@@
Query index 0 was solved
Query is satisfied.
Spent 0.316983 on verification
@@@0.44,71300@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 6 -n
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 6 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3578
------------------- QUERY 7 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is satisfied.
Spent 0.635362 on verification
@@@0.78,84492@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 7 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3577
------------------- QUERY 8 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 157.369 on verification
@@@157.77,2201464@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 8 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3419
------------------- QUERY 9 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is satisfied.
Spent 0.093941 on verification
@@@0.87,61284@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 9 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3418
------------------- QUERY 10 ----------------------
No solution found
Command terminated by signal 9
@@@186.85,7805952@@@
Command terminated by signal 9
@@@279.21,8341852@@@
Time left: 3115
------------------- QUERY 11 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 110.834 on verification
@@@111.26,1016360@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 11 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3004
------------------- QUERY 12 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is satisfied.
Spent 214.174 on verification
@@@214.56,1299604@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 12 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2789
------------------- QUERY 13 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 142.389 on verification
@@@142.78,2094904@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 13 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2646
------------------- QUERY 14 ----------------------
No solution found
Time left: 2344
------------------- QUERY 15 ----------------------
Solution found by parallel processing (step 1)
Command terminated by signal 9
@@@144.15,5669748@@@
Query index 0 was solved
Query is NOT satisfied.
Spent 176.701 on verification
@@@177.38,5833156@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 15 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2166
------------------- QUERY 16 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved
Query is NOT satisfied.
Spent 13.9745 on verification
@@@14.37,478848@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 16 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2151
---------------------------------------------------
Step 2: Sequential processing
---------------------------------------------------
Remaining 2 queries are verified sequentially.
Each query is verified for a dynamic timeout (at least 598 seconds)
Time left: 2151
------------------- QUERY 10 ----------------------
Running query 10 for 1075 seconds. Remaining: 2 queries and 2151 seconds
Solution found by sequential processing (step 2)
Command terminated by signal 9
@@@200.73,8169316@@@
FORMULA StigmergyCommit-PT-07a-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Query index 0 was solved
Query is NOT satisfied.
Spent 353.751 on verification
@@@354.70,12383596@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -q\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 10 -n
Command terminated by signal 9
@@@200.73,8169316@@@
Query index 0 was solved
Query is NOT satisfied.
Spent 353.751 on verification
@@@354.70,12383596@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -q\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.zR3wlmLt4S /home/mcc/BenchKit/bin/tmp/tmp.MeA5VAv0vR --binary-query-io 1 -x 10 -n
FORMULA StigmergyCommit-PT-07a-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 1796
------------------- QUERY 14 ----------------------
Running query 14 for 1796 seconds. Remaining: 1 queries and 1796 seconds
No solution found
Time left: -2
Out of time, terminating!
terminated-with-cleanup
BK_STOP 1679609429823
--------------------
content from stderr:
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyCommit-PT-07a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="gold2022"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool gold2022"
echo " Input is StigmergyCommit-PT-07a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r478-smll-167912663800356"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/StigmergyCommit-PT-07a.tgz
mv StigmergyCommit-PT-07a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;