About the Execution of LoLa+red for StigmergyElection-PT-11a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
8747.396 | 364869.00 | 454862.00 | 1826.40 | TTFFTT?TFFFTTTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647700698.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is StigmergyElection-PT-11a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647700698
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 154M
-rw-r--r-- 1 mcc users 7.6K Feb 26 17:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 85K Feb 26 17:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 26 16:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 16:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:15 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 17:15 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 18:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 144K Feb 26 18:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 26 17:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 26 17:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 17:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 153M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-00
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-01
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-02
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-03
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-04
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-05
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-06
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-07
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-08
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-09
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-10
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-11
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-12
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-13
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-14
FORMULA_NAME StigmergyElection-PT-11a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679352027606
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=StigmergyElection-PT-11a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-20 22:40:30] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-20 22:40:30] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-20 22:40:36] [INFO ] Load time of PNML (sax parser for PT used): 6421 ms
[2023-03-20 22:40:37] [INFO ] Transformed 156 places.
[2023-03-20 22:40:37] [INFO ] Transformed 136650 transitions.
[2023-03-20 22:40:37] [INFO ] Found NUPN structural information;
[2023-03-20 22:40:37] [INFO ] Parsed PT model containing 156 places and 136650 transitions and 3001363 arcs in 7374 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 48 ms.
Ensure Unique test removed 132345 transitions
Reduce redundant transitions removed 132345 transitions.
Support contains 11 out of 156 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 156/156 places, 4305/4305 transitions.
Discarding 21 places :
Symmetric choice reduction at 0 with 21 rule applications. Total rules 21 place count 135 transition count 4273
Iterating global reduction 0 with 21 rules applied. Total rules applied 42 place count 135 transition count 4273
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 53 place count 124 transition count 4251
Iterating global reduction 0 with 11 rules applied. Total rules applied 64 place count 124 transition count 4251
Applied a total of 64 rules in 168 ms. Remains 124 /156 variables (removed 32) and now considering 4251/4305 (removed 54) transitions.
[2023-03-20 22:40:39] [INFO ] Flow matrix only has 4239 transitions (discarded 12 similar events)
// Phase 1: matrix 4239 rows 124 cols
[2023-03-20 22:40:39] [INFO ] Computed 2 place invariants in 94 ms
[2023-03-20 22:40:39] [INFO ] Implicit Places using invariants in 374 ms returned []
[2023-03-20 22:40:39] [INFO ] Flow matrix only has 4239 transitions (discarded 12 similar events)
[2023-03-20 22:40:39] [INFO ] Invariant cache hit.
[2023-03-20 22:40:41] [INFO ] State equation strengthened by 4148 read => feed constraints.
[2023-03-20 22:40:41] [INFO ] Implicit Places using invariants and state equation in 2270 ms returned []
Implicit Place search using SMT with State Equation took 2702 ms to find 0 implicit places.
[2023-03-20 22:40:41] [INFO ] Flow matrix only has 4239 transitions (discarded 12 similar events)
[2023-03-20 22:40:41] [INFO ] Invariant cache hit.
[2023-03-20 22:40:44] [INFO ] Dead Transitions using invariants and state equation in 2364 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 124/156 places, 4251/4305 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5239 ms. Remains : 124/156 places, 4251/4305 transitions.
Support contains 11 out of 124 places after structural reductions.
[2023-03-20 22:40:45] [INFO ] Flatten gal took : 832 ms
[2023-03-20 22:40:45] [INFO ] Flatten gal took : 542 ms
[2023-03-20 22:40:47] [INFO ] Input system was already deterministic with 4251 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 3841 ms. (steps per millisecond=2 ) properties (out of 16) seen :12
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-20 22:40:51] [INFO ] Flow matrix only has 4239 transitions (discarded 12 similar events)
[2023-03-20 22:40:51] [INFO ] Invariant cache hit.
[2023-03-20 22:40:51] [INFO ] After 39ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :0
Fused 4 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 3 ms.
Successfully simplified 4 atomic propositions for a total of 16 simplifications.
[2023-03-20 22:40:52] [INFO ] Flatten gal took : 354 ms
[2023-03-20 22:40:52] [INFO ] Flatten gal took : 391 ms
[2023-03-20 22:40:53] [INFO ] Input system was already deterministic with 4251 transitions.
Computed a total of 24 stabilizing places and 23 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 25 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:40:53] [INFO ] Flatten gal took : 292 ms
[2023-03-20 22:40:54] [INFO ] Flatten gal took : 294 ms
[2023-03-20 22:40:54] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 23 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 24 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:40:55] [INFO ] Flatten gal took : 278 ms
[2023-03-20 22:40:55] [INFO ] Flatten gal took : 299 ms
[2023-03-20 22:40:55] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 20 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:40:56] [INFO ] Flatten gal took : 288 ms
[2023-03-20 22:40:56] [INFO ] Flatten gal took : 298 ms
[2023-03-20 22:40:57] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 23 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 24 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:40:57] [INFO ] Flatten gal took : 267 ms
[2023-03-20 22:40:57] [INFO ] Flatten gal took : 298 ms
[2023-03-20 22:40:58] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 19 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:40:58] [INFO ] Flatten gal took : 267 ms
[2023-03-20 22:40:59] [INFO ] Flatten gal took : 299 ms
[2023-03-20 22:40:59] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Reduce places removed 1 places and 1 transitions.
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition count delta: 22
Iterating post reduction 0 with 23 rules applied. Total rules applied 23 place count 122 transition count 4228
Reduce places removed 22 places and 0 transitions.
Iterating post reduction 1 with 22 rules applied. Total rules applied 45 place count 100 transition count 4228
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 11 Pre rules applied. Total rules applied 45 place count 100 transition count 4217
Deduced a syphon composed of 11 places in 0 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 2 with 22 rules applied. Total rules applied 67 place count 89 transition count 4217
Discarding 22 places :
Symmetric choice reduction at 2 with 22 rule applications. Total rules 89 place count 67 transition count 4195
Iterating global reduction 2 with 22 rules applied. Total rules applied 111 place count 67 transition count 4195
Ensure Unique test removed 2047 transitions
Reduce isomorphic transitions removed 2047 transitions.
Iterating post reduction 2 with 2047 rules applied. Total rules applied 2158 place count 67 transition count 2148
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 11 Pre rules applied. Total rules applied 2158 place count 67 transition count 2137
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 3 with 22 rules applied. Total rules applied 2180 place count 56 transition count 2137
Drop transitions removed 11 transitions
Redundant transition composition rules discarded 11 transitions
Iterating global reduction 3 with 11 rules applied. Total rules applied 2191 place count 56 transition count 2126
Performed 11 Post agglomeration using F-continuation condition.Transition count delta: 11
Deduced a syphon composed of 11 places in 2 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 3 with 22 rules applied. Total rules applied 2213 place count 45 transition count 2115
Applied a total of 2213 rules in 3136 ms. Remains 45 /124 variables (removed 79) and now considering 2115/4251 (removed 2136) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3137 ms. Remains : 45/124 places, 2115/4251 transitions.
[2023-03-20 22:41:03] [INFO ] Flatten gal took : 127 ms
[2023-03-20 22:41:03] [INFO ] Flatten gal took : 141 ms
[2023-03-20 22:41:03] [INFO ] Input system was already deterministic with 2115 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 18 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:41:03] [INFO ] Flatten gal took : 266 ms
[2023-03-20 22:41:04] [INFO ] Flatten gal took : 298 ms
[2023-03-20 22:41:04] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 19 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 19 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:41:05] [INFO ] Flatten gal took : 267 ms
[2023-03-20 22:41:05] [INFO ] Flatten gal took : 299 ms
[2023-03-20 22:41:05] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 16 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:41:06] [INFO ] Flatten gal took : 252 ms
[2023-03-20 22:41:06] [INFO ] Flatten gal took : 287 ms
[2023-03-20 22:41:07] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 18 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:41:07] [INFO ] Flatten gal took : 264 ms
[2023-03-20 22:41:07] [INFO ] Flatten gal took : 298 ms
[2023-03-20 22:41:08] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 17 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:41:08] [INFO ] Flatten gal took : 268 ms
[2023-03-20 22:41:09] [INFO ] Flatten gal took : 299 ms
[2023-03-20 22:41:09] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Reduce places removed 1 places and 1 transitions.
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition count delta: 22
Iterating post reduction 0 with 23 rules applied. Total rules applied 23 place count 122 transition count 4228
Reduce places removed 22 places and 0 transitions.
Iterating post reduction 1 with 22 rules applied. Total rules applied 45 place count 100 transition count 4228
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 11 Pre rules applied. Total rules applied 45 place count 100 transition count 4217
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 2 with 22 rules applied. Total rules applied 67 place count 89 transition count 4217
Discarding 22 places :
Symmetric choice reduction at 2 with 22 rule applications. Total rules 89 place count 67 transition count 4195
Iterating global reduction 2 with 22 rules applied. Total rules applied 111 place count 67 transition count 4195
Ensure Unique test removed 2047 transitions
Reduce isomorphic transitions removed 2047 transitions.
Iterating post reduction 2 with 2047 rules applied. Total rules applied 2158 place count 67 transition count 2148
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 11 Pre rules applied. Total rules applied 2158 place count 67 transition count 2137
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 3 with 22 rules applied. Total rules applied 2180 place count 56 transition count 2137
Drop transitions removed 11 transitions
Redundant transition composition rules discarded 11 transitions
Iterating global reduction 3 with 11 rules applied. Total rules applied 2191 place count 56 transition count 2126
Performed 11 Post agglomeration using F-continuation condition.Transition count delta: 11
Deduced a syphon composed of 11 places in 0 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 3 with 22 rules applied. Total rules applied 2213 place count 45 transition count 2115
Applied a total of 2213 rules in 2297 ms. Remains 45 /124 variables (removed 79) and now considering 2115/4251 (removed 2136) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2301 ms. Remains : 45/124 places, 2115/4251 transitions.
[2023-03-20 22:41:12] [INFO ] Flatten gal took : 131 ms
[2023-03-20 22:41:12] [INFO ] Flatten gal took : 149 ms
[2023-03-20 22:41:12] [INFO ] Input system was already deterministic with 2115 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 17 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:41:12] [INFO ] Flatten gal took : 270 ms
[2023-03-20 22:41:13] [INFO ] Flatten gal took : 304 ms
[2023-03-20 22:41:13] [INFO ] Input system was already deterministic with 4251 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Reduce places removed 1 places and 1 transitions.
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition count delta: 22
Iterating post reduction 0 with 23 rules applied. Total rules applied 23 place count 122 transition count 4228
Reduce places removed 22 places and 0 transitions.
Iterating post reduction 1 with 22 rules applied. Total rules applied 45 place count 100 transition count 4228
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 11 Pre rules applied. Total rules applied 45 place count 100 transition count 4217
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 2 with 22 rules applied. Total rules applied 67 place count 89 transition count 4217
Discarding 22 places :
Symmetric choice reduction at 2 with 22 rule applications. Total rules 89 place count 67 transition count 4195
Iterating global reduction 2 with 22 rules applied. Total rules applied 111 place count 67 transition count 4195
Ensure Unique test removed 2047 transitions
Reduce isomorphic transitions removed 2047 transitions.
Iterating post reduction 2 with 2047 rules applied. Total rules applied 2158 place count 67 transition count 2148
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 11 Pre rules applied. Total rules applied 2158 place count 67 transition count 2137
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 3 with 22 rules applied. Total rules applied 2180 place count 56 transition count 2137
Drop transitions removed 11 transitions
Redundant transition composition rules discarded 11 transitions
Iterating global reduction 3 with 11 rules applied. Total rules applied 2191 place count 56 transition count 2126
Performed 11 Post agglomeration using F-continuation condition.Transition count delta: 11
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 3 with 22 rules applied. Total rules applied 2213 place count 45 transition count 2115
Applied a total of 2213 rules in 2290 ms. Remains 45 /124 variables (removed 79) and now considering 2115/4251 (removed 2136) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2292 ms. Remains : 45/124 places, 2115/4251 transitions.
[2023-03-20 22:41:16] [INFO ] Flatten gal took : 131 ms
[2023-03-20 22:41:16] [INFO ] Flatten gal took : 150 ms
[2023-03-20 22:41:16] [INFO ] Input system was already deterministic with 2115 transitions.
Finished random walk after 11 steps, including 0 resets, run visited all 1 properties in 3 ms. (steps per millisecond=3 )
FORMULA StigmergyElection-PT-11a-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Reduce places removed 1 places and 1 transitions.
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition count delta: 22
Iterating post reduction 0 with 23 rules applied. Total rules applied 23 place count 122 transition count 4228
Reduce places removed 22 places and 0 transitions.
Iterating post reduction 1 with 22 rules applied. Total rules applied 45 place count 100 transition count 4228
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 11 Pre rules applied. Total rules applied 45 place count 100 transition count 4217
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 2 with 22 rules applied. Total rules applied 67 place count 89 transition count 4217
Discarding 22 places :
Symmetric choice reduction at 2 with 22 rule applications. Total rules 89 place count 67 transition count 4195
Iterating global reduction 2 with 22 rules applied. Total rules applied 111 place count 67 transition count 4195
Ensure Unique test removed 2047 transitions
Reduce isomorphic transitions removed 2047 transitions.
Iterating post reduction 2 with 2047 rules applied. Total rules applied 2158 place count 67 transition count 2148
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 11 Pre rules applied. Total rules applied 2158 place count 67 transition count 2137
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 3 with 22 rules applied. Total rules applied 2180 place count 56 transition count 2137
Drop transitions removed 11 transitions
Redundant transition composition rules discarded 11 transitions
Iterating global reduction 3 with 11 rules applied. Total rules applied 2191 place count 56 transition count 2126
Performed 11 Post agglomeration using F-continuation condition.Transition count delta: 11
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 3 with 22 rules applied. Total rules applied 2213 place count 45 transition count 2115
Applied a total of 2213 rules in 2180 ms. Remains 45 /124 variables (removed 79) and now considering 2115/4251 (removed 2136) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2181 ms. Remains : 45/124 places, 2115/4251 transitions.
[2023-03-20 22:41:18] [INFO ] Flatten gal took : 131 ms
[2023-03-20 22:41:19] [INFO ] Flatten gal took : 149 ms
[2023-03-20 22:41:19] [INFO ] Input system was already deterministic with 2115 transitions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 4251/4251 transitions.
Applied a total of 0 rules in 16 ms. Remains 124 /124 variables (removed 0) and now considering 4251/4251 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 124/124 places, 4251/4251 transitions.
[2023-03-20 22:41:19] [INFO ] Flatten gal took : 264 ms
[2023-03-20 22:41:20] [INFO ] Flatten gal took : 297 ms
[2023-03-20 22:41:20] [INFO ] Input system was already deterministic with 4251 transitions.
[2023-03-20 22:41:20] [INFO ] Flatten gal took : 300 ms
[2023-03-20 22:41:21] [INFO ] Flatten gal took : 299 ms
[2023-03-20 22:41:21] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 14 ms.
[2023-03-20 22:41:21] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 124 places, 4251 transitions and 90721 arcs took 81 ms.
Total runtime 50993 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT StigmergyElection-PT-11a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/366
CTLFireability
FORMULA StigmergyElection-PT-11a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679352392475
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/366/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/366/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/366/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyElection-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-15: CONJ 0 0 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 35 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 40 (type EXCL) for 39 StigmergyElection-PT-11a-CTLFireability-14
lola: time limit : 222 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: FINISHED task # 40 (type EXCL) for StigmergyElection-PT-11a-CTLFireability-14
lola: result : false
lola: markings : 2833
lola: fired transitions : 21586
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 StigmergyElection-PT-11a-CTLFireability-11
lola: time limit : 237 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for StigmergyElection-PT-11a-CTLFireability-11
lola: result : true
lola: markings : 2833
lola: fired transitions : 12754
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 StigmergyElection-PT-11a-CTLFireability-05
lola: time limit : 254 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for StigmergyElection-PT-11a-CTLFireability-05
lola: result : true
lola: markings : 2048
lola: fired transitions : 11300
lola: time used : 1.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyElection-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-15: CONJ 0 0 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 40 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 15
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 47 (type EXCL) for 42 StigmergyElection-PT-11a-CTLFireability-15
lola: time limit : 273 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 47 (type EXCL) for StigmergyElection-PT-11a-CTLFireability-15
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 37 (type EXCL) for 36 StigmergyElection-PT-11a-CTLFireability-12
lola: time limit : 296 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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StigmergyElection-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-15: CONJ 0 0 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 2/296 1/32 StigmergyElection-PT-11a-CTLFireability-12 21073 m, 4214 m/sec, 133664 t fired, .
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StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
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StigmergyElection-PT-11a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-15: CONJ 0 0 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 7/296 1/32 StigmergyElection-PT-11a-CTLFireability-12 79122 m, 11609 m/sec, 551103 t fired, .
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lola: FINISHED task # 37 (type EXCL) for StigmergyElection-PT-11a-CTLFireability-12
lola: result : true
lola: markings : 119220
lola: fired transitions : 852521
lola: time used : 11.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 StigmergyElection-PT-11a-CTLFireability-10
lola: time limit : 322 sec
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
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StigmergyElection-PT-11a-CTLFireability-15: CONJ 0 0 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 1/322 1/32 StigmergyElection-PT-11a-CTLFireability-10 10575 m, 2115 m/sec, 54223 t fired, .
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StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
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31 CTL EXCL 6/322 1/32 StigmergyElection-PT-11a-CTLFireability-10 62226 m, 10330 m/sec, 414077 t fired, .
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 50 (type FNDP) for 42 StigmergyElection-PT-11a-CTLFireability-15
lola: time limit : 32000000 sec
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lola: LAUNCH task # 51 (type EQUN) for 42 StigmergyElection-PT-11a-CTLFireability-15
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lola: LAUNCH task # 53 (type SRCH) for 42 StigmergyElection-PT-11a-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 50 (type FNDP) for StigmergyElection-PT-11a-CTLFireability-15
lola: result : true
lola: fired transitions : 10
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 51 (type EQUN) for StigmergyElection-PT-11a-CTLFireability-15 (obsolete)
lola: CANCELED task # 53 (type SRCH) for StigmergyElection-PT-11a-CTLFireability-15 (obsolete)
lola: FINISHED task # 53 (type SRCH) for StigmergyElection-PT-11a-CTLFireability-15
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/366/CTLFireability-51.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 51 (type EQUN) for StigmergyElection-PT-11a-CTLFireability-15
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-15: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 11/354 1/32 StigmergyElection-PT-11a-CTLFireability-10 113519 m, 10258 m/sec, 795356 t fired, .
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StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-15: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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StigmergyElection-PT-11a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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31 CTL EXCL 16/354 1/32 StigmergyElection-PT-11a-CTLFireability-10 170288 m, 11353 m/sec, 1227704 t fired, .
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lola: FINISHED task # 31 (type EXCL) for StigmergyElection-PT-11a-CTLFireability-10
lola: result : false
lola: markings : 179031
lola: fired transitions : 1300996
lola: time used : 17.000000
lola: memory pages used : 1
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lola: FINISHED task # 28 (type EXCL) for StigmergyElection-PT-11a-CTLFireability-09
lola: result : false
lola: markings : 2059
lola: fired transitions : 15393
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
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StigmergyElection-PT-11a-CTLFireability-10: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-15: CONJ false findpath
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25 CTL EXCL 4/441 1/32 StigmergyElection-PT-11a-CTLFireability-08 20744 m, 4148 m/sec, 308852 t fired, .
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StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
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25 CTL EXCL 9/441 1/32 StigmergyElection-PT-11a-CTLFireability-08 48957 m, 5642 m/sec, 786095 t fired, .
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StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
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StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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25 CTL EXCL 14/441 1/32 StigmergyElection-PT-11a-CTLFireability-08 75821 m, 5372 m/sec, 1275415 t fired, .
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StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
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25 CTL EXCL 19/441 1/32 StigmergyElection-PT-11a-CTLFireability-08 104980 m, 5831 m/sec, 1758147 t fired, .
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StigmergyElection-PT-11a-CTLFireability-10: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-15: CONJ false findpath
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lola: FINISHED task # 25 (type EXCL) for StigmergyElection-PT-11a-CTLFireability-08
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StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-15: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyElection-PT-11a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 9/3309 1/32 StigmergyElection-PT-11a-CTLFireability-00 78746 m, 10079 m/sec, 551044 t fired, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-CTLFireability-01: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-02: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-03: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-04: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-07: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-08: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-09: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-10: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-15: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyElection-PT-11a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
StigmergyElection-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 14/3309 1/32 StigmergyElection-PT-11a-CTLFireability-00 129071 m, 10065 m/sec, 922398 t fired, .
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lola: FINISHED task # 1 (type EXCL) for StigmergyElection-PT-11a-CTLFireability-00
lola: result : true
lola: markings : 177136
lola: fired transitions : 1298947
lola: time used : 19.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-CTLFireability-00: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-01: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-02: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-03: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-04: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-05: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-06: CTL unknown AGGR
StigmergyElection-PT-11a-CTLFireability-07: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-08: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-09: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-10: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-12: CTL true CTL model checker
StigmergyElection-PT-11a-CTLFireability-14: CTL false CTL model checker
StigmergyElection-PT-11a-CTLFireability-15: CONJ false findpath
Time elapsed: 310 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyElection-PT-11a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is StigmergyElection-PT-11a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647700698"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/StigmergyElection-PT-11a.tgz
mv StigmergyElection-PT-11a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;