Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647600586.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is StigmergyElection-PT-04a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647600586
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 7.2K Feb 26 16:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 26 16:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 26 16:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 26 16:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 17:14 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 17:14 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:14 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:14 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 16:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 149K Feb 26 16:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 16:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 26 16:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 17:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:14 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 71K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-00
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-01
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-02
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-03
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-04
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-05
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-06
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-07
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-08
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-09
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-10
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-11
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-12
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-13
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-14
FORMULA_NAME StigmergyElection-PT-04a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679312981150

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=StigmergyElection-PT-04a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-20 11:49:44] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-20 11:49:44] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-20 11:49:44] [INFO ] Load time of PNML (sax parser for PT used): 139 ms
[2023-03-20 11:49:44] [INFO ] Transformed 58 places.
[2023-03-20 11:49:44] [INFO ] Transformed 218 transitions.
[2023-03-20 11:49:44] [INFO ] Found NUPN structural information;
[2023-03-20 11:49:44] [INFO ] Parsed PT model containing 58 places and 218 transitions and 1238 arcs in 312 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 21 ms.
Initial state reduction rules removed 1 formulas.
Ensure Unique test removed 110 transitions
Reduce redundant transitions removed 110 transitions.
FORMULA StigmergyElection-PT-04a-CTLFireability-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 30 out of 58 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 58/58 places, 108/108 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 55 transition count 105
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 55 transition count 105
Applied a total of 6 rules in 33 ms. Remains 55 /58 variables (removed 3) and now considering 105/108 (removed 3) transitions.
[2023-03-20 11:49:45] [INFO ] Flow matrix only has 96 transitions (discarded 9 similar events)
// Phase 1: matrix 96 rows 55 cols
[2023-03-20 11:49:45] [INFO ] Computed 2 place invariants in 12 ms
[2023-03-20 11:49:45] [INFO ] Implicit Places using invariants in 312 ms returned []
[2023-03-20 11:49:45] [INFO ] Flow matrix only has 96 transitions (discarded 9 similar events)
[2023-03-20 11:49:45] [INFO ] Invariant cache hit.
[2023-03-20 11:49:45] [INFO ] State equation strengthened by 49 read => feed constraints.
[2023-03-20 11:49:45] [INFO ] Implicit Places using invariants and state equation in 202 ms returned []
Implicit Place search using SMT with State Equation took 576 ms to find 0 implicit places.
[2023-03-20 11:49:45] [INFO ] Flow matrix only has 96 transitions (discarded 9 similar events)
[2023-03-20 11:49:45] [INFO ] Invariant cache hit.
[2023-03-20 11:49:45] [INFO ] Dead Transitions using invariants and state equation in 120 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 55/58 places, 105/108 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 732 ms. Remains : 55/58 places, 105/108 transitions.
Support contains 30 out of 55 places after structural reductions.
[2023-03-20 11:49:45] [INFO ] Flatten gal took : 38 ms
[2023-03-20 11:49:45] [INFO ] Flatten gal took : 20 ms
[2023-03-20 11:49:46] [INFO ] Input system was already deterministic with 105 transitions.
Incomplete random walk after 10000 steps, including 80 resets, run finished after 727 ms. (steps per millisecond=13 ) properties (out of 40) seen :36
Incomplete Best-First random walk after 10001 steps, including 42 resets, run finished after 103 ms. (steps per millisecond=97 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 33 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10000 steps, including 34 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 36 resets, run finished after 73 ms. (steps per millisecond=137 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-20 11:49:47] [INFO ] Flow matrix only has 96 transitions (discarded 9 similar events)
[2023-03-20 11:49:47] [INFO ] Invariant cache hit.
[2023-03-20 11:49:47] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-20 11:49:47] [INFO ] After 74ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:1
[2023-03-20 11:49:47] [INFO ] [Nat]Absence check using 2 positive place invariants in 5 ms returned sat
[2023-03-20 11:49:47] [INFO ] After 59ms SMT Verify possible using all constraints in natural domain returned unsat :4 sat :0
Fused 4 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 4 atomic propositions for a total of 15 simplifications.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 13 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 12 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 105 transitions.
Support contains 27 out of 55 places (down from 28) after GAL structural reductions.
Computed a total of 10 stabilizing places and 9 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 51 transition count 97
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 51 transition count 97
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 12 place count 47 transition count 89
Iterating global reduction 0 with 4 rules applied. Total rules applied 16 place count 47 transition count 89
Applied a total of 16 rules in 8 ms. Remains 47 /55 variables (removed 8) and now considering 89/105 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 47/55 places, 89/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 6 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 8 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 89 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 51 transition count 97
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 51 transition count 97
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 12 place count 47 transition count 89
Iterating global reduction 0 with 4 rules applied. Total rules applied 16 place count 47 transition count 89
Applied a total of 16 rules in 8 ms. Remains 47 /55 variables (removed 8) and now considering 89/105 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 47/55 places, 89/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 6 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 7 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 89 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 2 place count 53 transition count 101
Iterating global reduction 0 with 2 rules applied. Total rules applied 4 place count 53 transition count 101
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 52 transition count 99
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 52 transition count 99
Applied a total of 6 rules in 6 ms. Remains 52 /55 variables (removed 3) and now considering 99/105 (removed 6) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 52/55 places, 99/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 7 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 6 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 99 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 2 place count 53 transition count 101
Iterating global reduction 0 with 2 rules applied. Total rules applied 4 place count 53 transition count 101
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 6 place count 51 transition count 97
Iterating global reduction 0 with 2 rules applied. Total rules applied 8 place count 51 transition count 97
Applied a total of 8 rules in 6 ms. Remains 51 /55 variables (removed 4) and now considering 97/105 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 51/55 places, 97/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 6 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 6 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 97 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 51 transition count 97
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 51 transition count 97
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 11 place count 48 transition count 91
Iterating global reduction 0 with 3 rules applied. Total rules applied 14 place count 48 transition count 91
Applied a total of 14 rules in 5 ms. Remains 48 /55 variables (removed 7) and now considering 91/105 (removed 14) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 48/55 places, 91/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 5 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 6 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 91 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 2 place count 53 transition count 101
Iterating global reduction 0 with 2 rules applied. Total rules applied 4 place count 53 transition count 101
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 6 place count 51 transition count 97
Iterating global reduction 0 with 2 rules applied. Total rules applied 8 place count 51 transition count 97
Applied a total of 8 rules in 6 ms. Remains 51 /55 variables (removed 4) and now considering 97/105 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 51/55 places, 97/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 6 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 6 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 97 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 52 transition count 99
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 52 transition count 99
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 8 place count 50 transition count 95
Iterating global reduction 0 with 2 rules applied. Total rules applied 10 place count 50 transition count 95
Applied a total of 10 rules in 10 ms. Remains 50 /55 variables (removed 5) and now considering 95/105 (removed 10) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 50/55 places, 95/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 8 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 10 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 95 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 52 transition count 99
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 52 transition count 99
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 8 place count 50 transition count 95
Iterating global reduction 0 with 2 rules applied. Total rules applied 10 place count 50 transition count 95
Applied a total of 10 rules in 9 ms. Remains 50 /55 variables (removed 5) and now considering 95/105 (removed 10) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 50/55 places, 95/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 9 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 9 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 95 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 51 transition count 97
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 51 transition count 97
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 12 place count 47 transition count 89
Iterating global reduction 0 with 4 rules applied. Total rules applied 16 place count 47 transition count 89
Applied a total of 16 rules in 8 ms. Remains 47 /55 variables (removed 8) and now considering 89/105 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 47/55 places, 89/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 8 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 9 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 89 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 51 transition count 97
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 51 transition count 97
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 12 place count 47 transition count 89
Iterating global reduction 0 with 4 rules applied. Total rules applied 16 place count 47 transition count 89
Applied a total of 16 rules in 10 ms. Remains 47 /55 variables (removed 8) and now considering 89/105 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 47/55 places, 89/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 8 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 9 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 89 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 51 transition count 97
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 51 transition count 97
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 12 place count 47 transition count 89
Iterating global reduction 0 with 4 rules applied. Total rules applied 16 place count 47 transition count 89
Applied a total of 16 rules in 9 ms. Remains 47 /55 variables (removed 8) and now considering 89/105 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 47/55 places, 89/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 8 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 9 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 89 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 51 transition count 97
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 51 transition count 97
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 12 place count 47 transition count 89
Iterating global reduction 0 with 4 rules applied. Total rules applied 16 place count 47 transition count 89
Applied a total of 16 rules in 10 ms. Remains 47 /55 variables (removed 8) and now considering 89/105 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 47/55 places, 89/105 transitions.
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 8 ms
[2023-03-20 11:49:47] [INFO ] Flatten gal took : 9 ms
[2023-03-20 11:49:47] [INFO ] Input system was already deterministic with 89 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 51 transition count 97
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 51 transition count 97
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 11 place count 48 transition count 91
Iterating global reduction 0 with 3 rules applied. Total rules applied 14 place count 48 transition count 91
Applied a total of 14 rules in 7 ms. Remains 48 /55 variables (removed 7) and now considering 91/105 (removed 14) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 48/55 places, 91/105 transitions.
[2023-03-20 11:49:48] [INFO ] Flatten gal took : 8 ms
[2023-03-20 11:49:48] [INFO ] Flatten gal took : 9 ms
[2023-03-20 11:49:48] [INFO ] Input system was already deterministic with 91 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 52 transition count 99
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 52 transition count 99
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 9 place count 49 transition count 93
Iterating global reduction 0 with 3 rules applied. Total rules applied 12 place count 49 transition count 93
Applied a total of 12 rules in 5 ms. Remains 49 /55 variables (removed 6) and now considering 93/105 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 49/55 places, 93/105 transitions.
[2023-03-20 11:49:48] [INFO ] Flatten gal took : 8 ms
[2023-03-20 11:49:48] [INFO ] Flatten gal took : 8 ms
[2023-03-20 11:49:48] [INFO ] Input system was already deterministic with 93 transitions.
Starting structural reductions in LTL mode, iteration 0 : 55/55 places, 105/105 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 52 transition count 99
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 52 transition count 99
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 8 place count 50 transition count 95
Iterating global reduction 0 with 2 rules applied. Total rules applied 10 place count 50 transition count 95
Applied a total of 10 rules in 5 ms. Remains 50 /55 variables (removed 5) and now considering 95/105 (removed 10) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 50/55 places, 95/105 transitions.
[2023-03-20 11:49:48] [INFO ] Flatten gal took : 7 ms
[2023-03-20 11:49:48] [INFO ] Flatten gal took : 9 ms
[2023-03-20 11:49:48] [INFO ] Input system was already deterministic with 95 transitions.
[2023-03-20 11:49:48] [INFO ] Flatten gal took : 9 ms
[2023-03-20 11:49:48] [INFO ] Flatten gal took : 18 ms
[2023-03-20 11:49:48] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 6 ms.
[2023-03-20 11:49:48] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 55 places, 105 transitions and 456 arcs took 1 ms.
Total runtime 3706 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT StigmergyElection-PT-04a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

FORMULA StigmergyElection-PT-04a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyElection-PT-04a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679312989778

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 36 (type EXCL) for 35 StigmergyElection-PT-04a-CTLFireability-10
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-10
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 25 (type EXCL) for 18 StigmergyElection-PT-04a-CTLFireability-07
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 25 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-07
lola: result : true
lola: markings : 977
lola: fired transitions : 4552
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 StigmergyElection-PT-04a-CTLFireability-12
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 42 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-12
lola: result : false
lola: markings : 83
lola: fired transitions : 432
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 StigmergyElection-PT-04a-CTLFireability-11
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-11
lola: result : true
lola: markings : 50
lola: fired transitions : 127
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 4 (type EXCL) for 3 StigmergyElection-PT-04a-CTLFireability-01
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-01
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 StigmergyElection-PT-04a-CTLFireability-00
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 1 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-00
lola: result : true
lola: markings : 84
lola: fired transitions : 240
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 13 (type EXCL) for 12 StigmergyElection-PT-04a-CTLFireability-05
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 13 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-05
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 StigmergyElection-PT-04a-CTLFireability-04
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-04
lola: result : true
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 53 (type EXCL) for 32 StigmergyElection-PT-04a-CTLFireability-09
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 53 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-09
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 StigmergyElection-PT-04a-CTLFireability-14
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 StigmergyElection-PT-04a-CTLFireability-13
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 45 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-13
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 51 (type EXCL) for 50 StigmergyElection-PT-04a-CTLFireability-15
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 51 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-15
lola: result : false
lola: markings : 20
lola: fired transitions : 73
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 StigmergyElection-PT-04a-CTLFireability-08
lola: time limit : 720 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-08
lola: result : false
lola: markings : 26
lola: fired transitions : 112
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 18 StigmergyElection-PT-04a-CTLFireability-07
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-07
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 18 StigmergyElection-PT-04a-CTLFireability-07
lola: time limit : 1200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-07
lola: result : true
lola: markings : 20
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 StigmergyElection-PT-04a-CTLFireability-06
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-06
lola: result : false
lola: markings : 82
lola: fired transitions : 227
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 StigmergyElection-PT-04a-CTLFireability-03
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for StigmergyElection-PT-04a-CTLFireability-03
lola: result : false
lola: markings : 802
lola: fired transitions : 2973
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-04a-CTLFireability-00: CTL true CTL model checker
StigmergyElection-PT-04a-CTLFireability-01: CTL false CTL model checker
StigmergyElection-PT-04a-CTLFireability-03: CTL false CTL model checker
StigmergyElection-PT-04a-CTLFireability-04: CTL true CTL model checker
StigmergyElection-PT-04a-CTLFireability-05: CTL true CTL model checker
StigmergyElection-PT-04a-CTLFireability-06: CTL false CTL model checker
StigmergyElection-PT-04a-CTLFireability-07: DISJ true CTL model checker
StigmergyElection-PT-04a-CTLFireability-08: CTL false CTL model checker
StigmergyElection-PT-04a-CTLFireability-09: AXAG false state space /EXEF
StigmergyElection-PT-04a-CTLFireability-10: CTL false CTL model checker
StigmergyElection-PT-04a-CTLFireability-11: CTL true CTL model checker
StigmergyElection-PT-04a-CTLFireability-12: CTL false CTL model checker
StigmergyElection-PT-04a-CTLFireability-13: CTL false CTL model checker
StigmergyElection-PT-04a-CTLFireability-14: CTL true CTL model checker
StigmergyElection-PT-04a-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyElection-PT-04a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is StigmergyElection-PT-04a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647600586"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/StigmergyElection-PT-04a.tgz
mv StigmergyElection-PT-04a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;