MCC'2023- Execution of r455-smll-167912647300418

About the Execution of LoLa+red for StigmergyCommit-PT-03b

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
1844.556	3600000.00	526410.00	11664.60	F?TT?FFFFFFT??TF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-sm
Waiting for the VM to be ready (probing
.........................................
...................
=========================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is StigmergyCommit-PT-03b,
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647
=========================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 780K
-rw-r--r-- 1 mcc users 6.2K Feb
-rw-r--r-- 1 mcc users 61K Feb
-rw-r--r-- 1 mcc users 5.1K Feb
-rw-r--r-- 1 mcc users 43K Feb
-rw-r--r-- 1 mcc users 3.7K Feb
-rw-r--r-- 1 mcc users 25K Feb
-rw-r--r-- 1 mcc users 2.4K Feb
-rw-r--r-- 1 mcc users 19K Feb
-rw-r--r-- 1 mcc users 13K Feb
-rw-r--r-- 1 mcc users 134K Feb
-rw-r--r-- 1 mcc users 7.4K Feb
-rw-r--r-- 1 mcc users 60K Feb
-rw-r--r-- 1 mcc users 1.7K Feb
-rw-r--r-- 1 mcc users 3.7K Feb
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 4 Mar
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 359K Mar

--------------------
content from stdout:

=== Data for post analysis generated

The expected result is a vector
BOOL_VECTOR

here is the order used to build
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi
FORMULA_NAME StigmergyCommit-PT-03b-CTLFi

=== Now, execution of the tool begins

BK_START 1679245008921

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=StigmergyCommit-PT-03b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 16:56:51] [INFO ]
[2023-03-19 16:56:51] [INFO ]
[2023-03-19 16:56:52] [INFO ]
[2023-03-19 16:56:52] [INFO ]
[2023-03-19 16:56:52] [INFO ]
[2023-03-19 16:56:52] [INFO ]
[2023-03-19 16:56:52] [INFO ]
Parsed 16 properties from file /home/mcc/
Support contains 113 out of 1231
Starting structural reductions in
Discarding 91 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 49 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 24 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 20 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 18 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 18 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 17 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 15 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 13 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 8 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 5 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 4 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Applied a total of 585 rules in
// Phase 1: matrix 1183 rows 939 cols
[2023-03-19 16:56:54] [INFO ]
[2023-03-19 16:56:54] [INFO ]
[2023-03-19 16:56:54] [INFO ]
[2023-03-19 16:56:55] [INFO ]
Implicit Place search using SMT
[2023-03-19 16:56:55] [INFO ]
[2023-03-19 16:56:56] [INFO ]
Starting structural reductions in
Finished structural reductions in
Support contains 113 out of 939
[2023-03-19 16:56:57] [INFO ]
[2023-03-19 16:56:57] [INFO ]
[2023-03-19 16:56:57] [INFO ]
Support contains 111 out of 939
Incomplete random walk after 10000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Running SMT prover for 44 properties.
[2023-03-19 16:56:58] [INFO ]
[2023-03-19 16:57:00] [INFO ]
[2023-03-19 16:57:01] [INFO ]
[2023-03-19 16:57:02] [INFO ]
[2023-03-19 16:57:05] [INFO ]
[2023-03-19 16:57:06] [INFO ]
[2023-03-19 16:57:07] [INFO ]
[2023-03-19 16:57:07] [INFO ]
[2023-03-19 16:57:07] [INFO ]
[2023-03-19 16:57:08] [INFO ]
[2023-03-19 16:57:08] [INFO ]
[2023-03-19 16:57:09] [INFO ]
[2023-03-19 16:57:10] [INFO ]
[2023-03-19 16:57:10] [INFO ]
[2023-03-19 16:57:10] [INFO ]
[2023-03-19 16:57:10] [INFO ]
[2023-03-19 16:57:11] [INFO ]
[2023-03-19 16:57:12] [INFO ]
[2023-03-19 16:57:13] [INFO ]
[2023-03-19 16:57:13] [INFO ]
[2023-03-19 16:57:14] [INFO ]
[2023-03-19 16:57:14] [INFO ]
[2023-03-19 16:57:14] [INFO ]
[2023-03-19 16:57:15] [INFO ]
[2023-03-19 16:57:15] [INFO ]
[2023-03-19 16:57:17] [INFO ]
[2023-03-19 16:57:18] [INFO ]
[2023-03-19 16:57:18] [INFO ]
Attempting to minimize the solution
Minimization took 2358 ms.
[2023-03-19 16:57:20] [INFO ]
Fused 44 Parikh solutions to 40
Parikh walk visited 25 properties
Support contains 18 out of 939 places.
Starting structural reductions in
Graph (trivial) has 902 edges and
Free SCC test removed 56 places
Drop transitions removed 74 transitions
Reduce isomorphic transitions removed
Graph (complete) has 1354 edges
Discarding 4 places :
Also discarding 0 output transitions
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed
Drop transitions removed 644 transitions
Trivial Post-agglo rules discarded
Performed 644 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 644 places
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded
Performed 5 trivial Post agglomeration.
Iterating post reduction 1 with
Reduce places removed 5 places and
Performed 6 Post agglomeration using
Iterating post reduction 2 with
Reduce places removed 6 places and
Iterating post reduction 3 with
Performed 49 Pre agglomeration using
Pre-agglomeration after 4 with 49
Deduced a syphon composed of 49
Reduce places removed 49 places
Iterating global reduction 4 with
Discarding 10 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Performed 3 Pre agglomeration using
Pre-agglomeration after 4 with 3
Deduced a syphon composed of 3 places
Reduce places removed 3 places and
Iterating global reduction 4 with
Discarding 6 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Performed 24 Post agglomeration
Deduced a syphon composed of 24
Reduce places removed 24 places
Iterating global reduction 5 with
Drop transitions removed 1 transitions
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Discarding 17 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Discarding 7 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Discarding 7 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed
Iterating post reduction 7 with
Performed 6 Post agglomeration using
Deduced a syphon composed of 6 places
Reduce places removed 6 places and
Iterating global reduction 8 with
Performed 3 Post agglomeration using
Deduced a syphon composed of 3 places
Reduce places removed 3 places and
Iterating global reduction 8 with
Drop transitions removed 1 transitions
Redundant transition composition
Iterating global reduction 8 with
Free-agglomeration rule applied
Iterating global reduction 8 with
Reduce places removed 32 places
Drop transitions removed 2 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 8 with
Drop transitions removed 18 transitions
Redundant transition composition
Iterating global reduction 9 with
Partial Free-agglomeration rule
Drop transitions removed 5 transitions
Iterating global reduction 9 with
Applied a total of 1702 rules in
Finished structural reductions in
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Running SMT prover for 1 properties.
// Phase 1: matrix 115 rows 58 cols
[2023-03-19 16:57:21] [INFO ]
[2023-03-19 16:57:21] [INFO ]
[2023-03-19 16:57:21] [INFO ]
[2023-03-19 16:57:21] [INFO ]
[2023-03-19 16:57:21] [INFO ]
[2023-03-19 16:57:21] [INFO ]
[2023-03-19 16:57:21] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
Attempting to minimize the solution
Minimization took 7 ms.
[2023-03-19 16:57:22] [INFO ]
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 58 places.
Starting structural reductions in
Graph (trivial) has 32 edges and
Free SCC test removed 1 places
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded
Performed 12 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 12 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Performed 2 Pre agglomeration using
Pre-agglomeration after 2 with 2
Deduced a syphon composed of 2 places
Reduce places removed 2 places and
Iterating global reduction 2 with
Discarding 3 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Performed 5 Post agglomeration using
Deduced a syphon composed of 5 places
Reduce places removed 5 places and
Iterating global reduction 3 with
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Discarding 5 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Drop transitions removed 2 transitions
Redundant transition composition
Iterating global reduction 5 with
Free-agglomeration rule applied 1 times.
Iterating global reduction 5 with
Reduce places removed 1 places and
Iterating post reduction 5 with
Discarding 4 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Partial Free-agglomeration rule
Drop transitions removed 4 transitions
Iterating global reduction 6 with
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Drop transitions removed 2 transitions
Redundant transition composition
Iterating global reduction 7 with
Applied a total of 96 rules in 36
Finished structural reductions in
Finished random walk after 313
Successfully simplified 4 atomic
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
FORMULA StigmergyCommit-PT-03b-CTLFireability-14
[2023-03-19 16:57:22] [INFO
[2023-03-19 16:57:22] [INFO ]
Support contains 95 out of 939 places
Computed a total of 179 stabilizing
Starting structural reductions in
Graph (trivial) has 928 edges and
Free SCC test removed 62 places
Ensure Unique test removed 70 transitions
Reduce isomorphic transitions removed
Reduce places removed 1 places and
Drop transitions removed 659 transitions
Trivial Post-agglo rules discarded
Performed 659 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 659 places
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded
Performed 4 trivial Post agglomeration.
Iterating post reduction 1 with
Reduce places removed 4 places and
Performed 6 Post agglomeration using
Iterating post reduction 2 with
Reduce places removed 6 places and
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Performed 1 Post agglomeration using
Iterating post reduction 3 with
Reduce places removed 1 places and
Iterating post reduction 4 with
Performed 45 Pre agglomeration using
Pre-agglomeration after 5 with 45
Deduced a syphon composed of 45
Reduce places removed 45 places
Iterating global reduction 5 with
Discarding 18 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Performed 3 Pre agglomeration using
Pre-agglomeration after 5 with 3
Deduced a syphon composed of 3 places
Reduce places removed 3 places and
Iterating global reduction 5 with
Discarding 9 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Discarding 3 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Discarding 1 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Performed 19 Post agglomeration
Deduced a syphon composed of 19
Reduce places removed 19 places
Iterating global reduction 7 with
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed
Iterating post reduction 7 with
Discarding 20 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed
Iterating post reduction 8 with
Discarding 11 places :
Symmetric choice reduction at 9
Iterating global reduction 9 with
Discarding 11 places :
Symmetric choice reduction at 9
Iterating global reduction 9 with
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed
Iterating post reduction 9 with
Performed 1 Post agglomeration using
Deduced a syphon composed of 1 places
Reduce places removed 1 places and
Iterating global reduction 10 with
Discarding 1 places :
Symmetric choice reduction at 10
Iterating global reduction 10 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 10 with
Drop transitions removed 4 transitions
Redundant transition composition
Iterating global reduction 11 with
Performed 4 Post agglomeration using
Deduced a syphon composed of 4 places
Reduce places removed 4 places and
Iterating global reduction 11 with
Reduce places removed 1 places and
Iterating global reduction 11 with
Applied a total of 1670 rules in
Finished structural reductions in
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
[2023-03-19 16:57:22] [INFO ]
Starting structural reductions in
Discarding 26 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 20 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 15 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 12 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Discarding 11 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 10 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 10 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 9 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 6 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Discarding 4 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Discarding 3 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 2 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Applied a total of 277 rules in
Finished structural reductions in
[2023-03-19 16:57:23] [INFO ]
[2023-03-19 16:57:23] [INFO ]
[2023-03-19 16:57:23] [INFO ]
Starting structural reductions in
Graph (trivial) has 932 edges and
Free SCC test removed 62 places
Ensure Unique test removed 70 transitions
Reduce isomorphic transitions removed
Reduce places removed 1 places and
Drop transitions removed 660 transitions
Trivial Post-agglo rules discarded
Performed 660 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 660 places
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded
Performed 5 trivial Post agglomeration.
Iterating post reduction 1 with
Reduce places removed 5 places and
Performed 1 Post agglomeration using
Iterating post reduction 2 with
Reduce places removed 1 places and
Iterating post reduction 3 with
Performed 45 Pre agglomeration using
Pre-agglomeration after 4 with 45
Deduced a syphon composed of 45
Reduce places removed 45 places
Iterating global reduction 4 with
Discarding 18 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Performed 3 Pre agglomeration using
Pre-agglomeration after 4 with 3
Deduced a syphon composed of 3 places
Reduce places removed 3 places and
Iterating global reduction 4 with
Discarding 9 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 3 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Performed 19 Post agglomeration
Deduced a syphon composed of 19
Reduce places removed 19 places
Iterating global reduction 6 with
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Discarding 20 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed
Iterating post reduction 7 with
Discarding 11 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Discarding 11 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed
Iterating post reduction 8 with
Performed 1 Post agglomeration using
Deduced a syphon composed of 1 places
Reduce places removed 1 places and
Iterating global reduction 9 with
Discarding 1 places :
Symmetric choice reduction at 9
Iterating global reduction 9 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 9 with
Drop transitions removed 4 transitions
Redundant transition composition
Iterating global reduction 10 with
Performed 4 Post agglomeration using
Deduced a syphon composed of 4 places
Reduce places removed 4 places and
Iterating global reduction 10 with
Reduce places removed 1 places and
Iterating global reduction 10 with
Applied a total of 1660 rules in
Finished structural reductions in
[2023-03-19 16:57:23] [INFO ]
[2023-03-19 16:57:23] [INFO ]
[2023-03-19 16:57:23] [INFO ]
Starting structural reductions in
Discarding 29 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 22 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 17 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 13 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Discarding 12 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 11 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 11 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 10 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 7 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Discarding 5 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Discarding 3 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 2 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Applied a total of 305 rules in
Finished structural reductions in
[2023-03-19 16:57:24] [INFO ]
[2023-03-19 16:57:24] [INFO ]
[2023-03-19 16:57:24] [INFO ]
Starting structural reductions in
Discarding 28 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 21 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 16 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 11 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Discarding 10 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 8 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 8 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 8 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 7 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Discarding 5 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Discarding 3 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 2 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Applied a total of 274 rules in
Finished structural reductions in
[2023-03-19 16:57:25] [INFO ]
[2023-03-19 16:57:25] [INFO ]
[2023-03-19 16:57:25] [INFO ]
Starting structural reductions in
Graph (trivial) has 930 edges and
Free SCC test removed 62 places
Ensure Unique test removed 70 transitions
Reduce isomorphic transitions removed
Reduce places removed 1 places and
Drop transitions removed 659 transitions
Trivial Post-agglo rules discarded
Performed 659 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 659 places
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded
Performed 5 trivial Post agglomeration.
Iterating post reduction 1 with
Reduce places removed 5 places and
Performed 3 Post agglomeration using
Iterating post reduction 2 with
Reduce places removed 3 places and
Iterating post reduction 3 with
Performed 44 Pre agglomeration using
Pre-agglomeration after 4 with 44
Deduced a syphon composed of 44
Reduce places removed 44 places
Iterating global reduction 4 with
Discarding 18 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Performed 3 Pre agglomeration using
Pre-agglomeration after 4 with 3
Deduced a syphon composed of 3 places
Reduce places removed 3 places and
Iterating global reduction 4 with
Discarding 9 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 2 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Performed 19 Post agglomeration
Deduced a syphon composed of 19
Reduce places removed 19 places
Iterating global reduction 5 with
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Discarding 20 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Discarding 11 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Discarding 11 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed
Iterating post reduction 7 with
Performed 1 Post agglomeration using
Deduced a syphon composed of 1 places
Reduce places removed 1 places and
Iterating global reduction 8 with
Discarding 1 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 8 with
Drop transitions removed 4 transitions
Redundant transition composition
Iterating global reduction 9 with
Performed 4 Post agglomeration using
Deduced a syphon composed of 4 places
Reduce places removed 4 places and
Iterating global reduction 9 with
Reduce places removed 1 places and
Iterating global reduction 9 with
Applied a total of 1659 rules in
Finished structural reductions in
[2023-03-19 16:57:25] [INFO ]
[2023-03-19 16:57:25] [INFO ]
[2023-03-19 16:57:25] [INFO ]
Starting structural reductions in
Graph (trivial) has 922 edges and
Free SCC test removed 62 places
Ensure Unique test removed 70 transitions
Reduce isomorphic transitions removed
Reduce places removed 1 places and
Drop transitions removed 650 transitions
Trivial Post-agglo rules discarded
Performed 650 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 650 places
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded
Performed 5 trivial Post agglomeration.
Iterating post reduction 1 with
Reduce places removed 5 places and
Performed 1 Post agglomeration using
Iterating post reduction 2 with
Reduce places removed 1 places and
Iterating post reduction 3 with
Performed 45 Pre agglomeration using
Pre-agglomeration after 4 with 45
Deduced a syphon composed of 45
Reduce places removed 45 places
Iterating global reduction 4 with
Discarding 17 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Performed 3 Pre agglomeration using
Pre-agglomeration after 4 with 3
Deduced a syphon composed of 3 places
Reduce places removed 3 places and
Iterating global reduction 4 with
Discarding 7 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 3 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Performed 20 Post agglomeration
Deduced a syphon composed of 20
Reduce places removed 20 places
Iterating global reduction 6 with
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Discarding 17 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed
Iterating post reduction 7 with
Discarding 10 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Discarding 10 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed
Iterating post reduction 8 with
Performed 1 Post agglomeration using
Deduced a syphon composed of 1 places
Reduce places removed 1 places and
Iterating global reduction 9 with
Discarding 1 places :
Symmetric choice reduction at 9
Iterating global reduction 9 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 9 with
Drop transitions removed 4 transitions
Redundant transition composition
Iterating global reduction 10 with
Performed 4 Post agglomeration using
Deduced a syphon composed of 4 places
Reduce places removed 4 places and
Iterating global reduction 10 with
Reduce places removed 1 places and
Iterating global reduction 10 with
Applied a total of 1620 rules in
Finished structural reductions in
[2023-03-19 16:57:25] [INFO ]
[2023-03-19 16:57:25] [INFO ]
[2023-03-19 16:57:25] [INFO ]
Starting structural reductions in
Graph (trivial) has 890 edges and
Free SCC test removed 56 places
Ensure Unique test removed 63 transitions
Reduce isomorphic transitions removed
Reduce places removed 1 places and
Drop transitions removed 625 transitions
Trivial Post-agglo rules discarded
Performed 625 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 625 places
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded
Performed 5 trivial Post agglomeration.
Iterating post reduction 1 with
Reduce places removed 5 places and
Performed 19 Post agglomeration
Iterating post reduction 2 with
Reduce places removed 19 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 46 Pre agglomeration using
Pre-agglomeration after 4 with 46
Deduced a syphon composed of 46
Reduce places removed 46 places
Iterating global reduction 4 with
Discarding 16 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Performed 1 Pre agglomeration using
Pre-agglomeration after 4 with 1
Deduced a syphon composed of 1 places
Reduce places removed 1 places and
Iterating global reduction 4 with
Discarding 8 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 2 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Performed 21 Post agglomeration
Deduced a syphon composed of 21
Reduce places removed 21 places
Iterating global reduction 5 with
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Discarding 13 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Discarding 10 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Discarding 9 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed
Iterating post reduction 7 with
Performed 1 Post agglomeration using
Deduced a syphon composed of 1 places
Reduce places removed 1 places and
Iterating global reduction 8 with
Discarding 1 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 8 with
Drop transitions removed 4 transitions
Redundant transition composition
Iterating global reduction 9 with
Performed 4 Post agglomeration using
Deduced a syphon composed of 4 places
Reduce places removed 4 places and
Iterating global reduction 9 with
Partial Post-agglomeration rule
Drop transitions removed 1 transitions
Iterating global reduction 9 with
Reduce places removed 1 places and
Iterating global reduction 9 with
Applied a total of 1594 rules in
Finished structural reductions in
[2023-03-19 16:57:25] [INFO ]
[2023-03-19 16:57:25] [INFO ]
[2023-03-19 16:57:25] [INFO ]
Starting structural reductions in
Discarding 26 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 20 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 16 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 13 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Discarding 12 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 11 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 11 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 10 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 7 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Discarding 5 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Discarding 3 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 2 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Applied a total of 293 rules in
Finished structural reductions in
[2023-03-19 16:57:26] [INFO ]
[2023-03-19 16:57:26] [INFO ]
[2023-03-19 16:57:26] [INFO ]
Starting structural reductions in
Graph (trivial) has 912 edges and
Free SCC test removed 62 places
Ensure Unique test removed 70 transitions
Reduce isomorphic transitions removed
Reduce places removed 1 places and
Drop transitions removed 637 transitions
Trivial Post-agglo rules discarded
Performed 637 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 637 places
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded
Performed 5 trivial Post agglomeration.
Iterating post reduction 1 with
Reduce places removed 5 places and
Performed 12 Post agglomeration
Iterating post reduction 2 with
Reduce places removed 12 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 45 Pre agglomeration using
Pre-agglomeration after 4 with 45
Deduced a syphon composed of 45
Reduce places removed 45 places
Iterating global reduction 4 with
Discarding 17 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Performed 3 Pre agglomeration using
Pre-agglomeration after 4 with 3
Deduced a syphon composed of 3 places
Reduce places removed 3 places and
Iterating global reduction 4 with
Discarding 7 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 3 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Performed 20 Post agglomeration
Deduced a syphon composed of 20
Reduce places removed 20 places
Iterating global reduction 6 with
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Discarding 19 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed
Iterating post reduction 7 with
Discarding 10 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Discarding 10 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed
Iterating post reduction 8 with
Performed 1 Post agglomeration using
Deduced a syphon composed of 1 places
Reduce places removed 1 places and
Iterating global reduction 9 with
Discarding 1 places :
Symmetric choice reduction at 9
Iterating global reduction 9 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 9 with
Drop transitions removed 4 transitions
Redundant transition composition
Iterating global reduction 10 with
Performed 4 Post agglomeration using
Deduced a syphon composed of 4 places
Reduce places removed 4 places and
Iterating global reduction 10 with
Reduce places removed 1 places and
Iterating global reduction 10 with
Applied a total of 1621 rules in
Finished structural reductions in
[2023-03-19 16:57:26] [INFO ]
[2023-03-19 16:57:26] [INFO ]
[2023-03-19 16:57:26] [INFO ]
Starting structural reductions in
Discarding 28 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 21 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 16 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 12 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Discarding 11 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 10 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 10 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 9 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 6 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Discarding 4 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Discarding 3 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Discarding 2 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Applied a total of 284 rules in
Finished structural reductions in
[2023-03-19 16:57:27] [INFO ]
[2023-03-19 16:57:27] [INFO ]
[2023-03-19 16:57:27] [INFO ]
Starting structural reductions in
Graph (trivial) has 917 edges and
Free SCC test removed 60 places
Ensure Unique test removed 67 transitions
Reduce isomorphic transitions removed
Reduce places removed 1 places and
Drop transitions removed 653 transitions
Trivial Post-agglo rules discarded
Performed 653 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 653 places
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded
Performed 5 trivial Post agglomeration.
Iterating post reduction 1 with
Reduce places removed 5 places and
Performed 6 Post agglomeration using
Iterating post reduction 2 with
Reduce places removed 6 places and
Iterating post reduction 3 with
Performed 46 Pre agglomeration using
Pre-agglomeration after 4 with 46
Deduced a syphon composed of 46
Reduce places removed 46 places
Iterating global reduction 4 with
Discarding 18 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Performed 3 Pre agglomeration using
Pre-agglomeration after 4 with 3
Deduced a syphon composed of 3 places
Reduce places removed 3 places and
Iterating global reduction 4 with
Discarding 8 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 2 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Performed 18 Post agglomeration
Deduced a syphon composed of 18
Reduce places removed 18 places
Iterating global reduction 6 with
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Discarding 18 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed
Iterating post reduction 7 with
Discarding 11 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Discarding 11 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed
Iterating post reduction 8 with
Performed 1 Post agglomeration using
Deduced a syphon composed of 1 places
Reduce places removed 1 places and
Iterating global reduction 9 with
Discarding 1 places :
Symmetric choice reduction at 9
Iterating global reduction 9 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 9 with
Drop transitions removed 5 transitions
Redundant transition composition
Iterating global reduction 10 with
Performed 5 Post agglomeration using
Deduced a syphon composed of 5 places
Reduce places removed 5 places and
Iterating global reduction 10 with
Reduce places removed 1 places and
Iterating global reduction 10 with
Applied a total of 1651 rules in
Finished structural reductions in
[2023-03-19 16:57:27] [INFO ]
[2023-03-19 16:57:27] [INFO ]
[2023-03-19 16:57:27] [INFO ]
Starting structural reductions in
Discarding 26 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 19 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 15 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 12 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Discarding 11 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 10 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 10 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 9 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 6 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Discarding 4 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Discarding 2 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Applied a total of 270 rules in
Finished structural reductions in
[2023-03-19 16:57:28] [INFO ]
[2023-03-19 16:57:28] [INFO ]
[2023-03-19 16:57:28] [INFO ]
Starting structural reductions in
Discarding 28 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 22 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 17 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Discarding 13 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Discarding 12 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 11 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 11 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 10 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 7 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Discarding 5 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Discarding 3 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Applied a total of 286 rules in
Finished structural reductions in
[2023-03-19 16:57:28] [INFO ]
[2023-03-19 16:57:28] [INFO ]
[2023-03-19 16:57:29] [INFO ]
Starting structural reductions in
Graph (trivial) has 903 edges and
Free SCC test removed 56 places
Ensure Unique test removed 62 transitions
Reduce isomorphic transitions removed
Reduce places removed 1 places and
Drop transitions removed 640 transitions
Trivial Post-agglo rules discarded
Performed 640 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 640 places
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded
Performed 5 trivial Post agglomeration.
Iterating post reduction 1 with
Reduce places removed 5 places and
Performed 17 Post agglomeration
Iterating post reduction 2 with
Reduce places removed 17 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 44 Pre agglomeration using
Pre-agglomeration after 4 with 44
Deduced a syphon composed of 44
Reduce places removed 44 places
Iterating global reduction 4 with
Discarding 17 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Performed 2 Pre agglomeration using
Pre-agglomeration after 4 with 2
Deduced a syphon composed of 2 places
Reduce places removed 2 places and
Iterating global reduction 4 with
Discarding 8 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Discarding 2 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Performed 19 Post agglomeration
Deduced a syphon composed of 19
Reduce places removed 19 places
Iterating global reduction 6 with
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Discarding 19 places :
Symmetric choice reduction at 7
Iterating global reduction 7 with
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed
Iterating post reduction 7 with
Discarding 10 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Discarding 10 places :
Symmetric choice reduction at 8
Iterating global reduction 8 with
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed
Iterating post reduction 8 with
Performed 1 Post agglomeration using
Deduced a syphon composed of 1 places
Reduce places removed 1 places and
Iterating global reduction 9 with
Discarding 1 places :
Symmetric choice reduction at 9
Iterating global reduction 9 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 9 with
Drop transitions removed 6 transitions
Redundant transition composition
Iterating global reduction 10 with
Performed 6 Post agglomeration using
Deduced a syphon composed of 6 places
Reduce places removed 6 places and
Iterating global reduction 10 with
Partial Post-agglomeration rule
Drop transitions removed 2 transitions
Iterating global reduction 10 with
Applied a total of 1642 rules in
Finished structural reductions in
[2023-03-19 16:57:29] [INFO ]
[2023-03-19 16:57:29] [INFO ]
[2023-03-19 16:57:29] [INFO ]
[2023-03-19 16:57:29] [INFO ]
[2023-03-19 16:57:29] [INFO ]
[2023-03-19 16:57:29] [INFO ]
[2023-03-19 16:57:29] [INFO ]
Total runtime 37549 ms.
There are residual formulas that
starting LoLA
BK_INPUT StigmergyCommit-PT-03b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//..
current directory: /home/mcc/execution/37
CTLFireability

FORMULA StigmergyCommit-PT-03b-CTLFireability-05

FORMULA StigmergyCommit-PT-03b-CTLFireability-11

FORMULA StigmergyCommit-PT-03b-CTLFireability-06

FORMULA StigmergyCommit-PT-03b-CTLFireability-03

FORMULA StigmergyCommit-PT-03b-CTLFireability-09

FORMULA StigmergyCommit-PT-03b-CTLFireability-02

FORMULA StigmergyCommit-PT-03b-CTLFireability-00

FORMULA StigmergyCommit-PT-03b-CTLFireability-15

FORMULA StigmergyCommit-PT-03b-CTLFireability-07

FORMULA StigmergyCommit-PT-03b-CTLFireability-08

FORMULA StigmergyCommit-PT-03b-CTLFireability-10
TIME LIMIT: Killed by timeout
MemTotal: 16393216 kB
MemFree: 14313540 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16103044 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/it
+ PYTHONPATH=/home/mcc/BenchKit/itstools/
+ export LD_LIBRARY_PATH=/home/mcc/BenchK
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itst
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin/
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execut
lola: reading pnml
lola: PNML file contains place/transition
lola: finished parsing
lola: closed net file /home/mcc/executi
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/ex
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: RELEASE
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: RELEASE
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: RELEASE
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Rule S: 0 transitions removed,0
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: LAUNCH task # 16 (type EXCL)
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: FINISHED task # 16 (type
lola: result : false
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 34 (type EXCL)
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type
lola: result : true
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: Created skeleton in 0.000000
lola: LAUNCH task # 19 (type EXCL)
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type
lola: result : false
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: LAUNCH INITIAL
lola: LAUNCH task # 10 (type CNST)
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: FINISHED task # 10 (type
lola: result : true
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: LAUNCH task # 28 (type EXCL)
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: FINISHED task # 28 (type
lola: result : false
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: Created skeleton in 0.000000
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: LAUNCH task # 51 (type EXCL)
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type
lola: result : false
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 49 (type EXCL)
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type
lola: result : true
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 47 (type EXCL)
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type
lola: result : false
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 22 (type EXCL)
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type
lola: result : false
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: Created skeleton in 0.000000
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: LAUNCH task # 25 (type EXCL)
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: FINISHED task # 25 (type
lola: result : false
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 4 (type EXCL)
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
lola: rewrite Frontend/Parser/formula_r
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 5/599

Time elapsed: 8 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 10/599

Time elapsed: 13 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 15/599

Time elapsed: 18 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 20/599

Time elapsed: 23 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 25/599

Time elapsed: 28 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 30/599

Time elapsed: 33 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 35/599

Time elapsed: 38 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 40/599

Time elapsed: 43 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 45/599

Time elapsed: 48 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 50/599

Time elapsed: 53 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 55/599

Time elapsed: 58 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 60/599

Time elapsed: 63 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 65/599

Time elapsed: 68 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 70/599

Time elapsed: 73 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 75/599

Time elapsed: 78 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 80/599

Time elapsed: 83 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 85/599

Time elapsed: 88 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 90/599

Time elapsed: 93 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 95/599

Time elapsed: 98 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 100/599

Time elapsed: 103 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 105/599

Time elapsed: 108 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 110/599

Time elapsed: 113 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 115/599

Time elapsed: 118 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 120/599

Time elapsed: 123 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 125/599

Time elapsed: 128 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
4 CTL EXCL 130/599

Time elapsed: 133 secs. Pages
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 4 (type
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 138 secs. Pages
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 44 (type EXCL)
lola: time limit : 692 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type
lola: result : false
lola: markings :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 42 (type EXCL)
lola: time limit : 865 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 5/865

Time elapsed: 143 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 10/865

Time elapsed: 148 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 15/865

Time elapsed: 153 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 20/865

Time elapsed: 158 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 25/865

Time elapsed: 163 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 30/865

Time elapsed: 168 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 35/865

Time elapsed: 173 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 40/865

Time elapsed: 178 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 45/865

Time elapsed: 183 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 50/865

Time elapsed: 188 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 55/865

Time elapsed: 193 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 60/865

Time elapsed: 198 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 65/865

Time elapsed: 203 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 70/865

Time elapsed: 208 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 75/865

Time elapsed: 213 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 80/865

Time elapsed: 218 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 85/865

Time elapsed: 223 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 90/865

Time elapsed: 228 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
42 CTL EXCL 95/865

Time elapsed: 233 secs. Pages
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 42 (type
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 238 secs. Pages
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 37 (type EXCL)
lola: time limit : 1120 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 5/1120

Time elapsed: 243 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 10/1120

Time elapsed: 248 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 15/1120

Time elapsed: 253 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 20/1120

Time elapsed: 258 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 25/1120

Time elapsed: 263 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 30/1120

Time elapsed: 268 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 35/1120

Time elapsed: 273 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 40/1120

Time elapsed: 278 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 45/1120

Time elapsed: 283 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 50/1120

Time elapsed: 288 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 55/1120

Time elapsed: 293 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 60/1120

Time elapsed: 298 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 65/1120

Time elapsed: 303 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 70/1120

Time elapsed: 308 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 75/1120

Time elapsed: 313 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 80/1120

Time elapsed: 318 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 85/1120

Time elapsed: 323 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 90/1120

Time elapsed: 328 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
37 CTL EXCL 95/1120

Time elapsed: 333 secs. Pages
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 37 (type
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 338 secs. Pages
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 31 (type EXCL)
lola: time limit : 1631 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type
lola: result : false
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 13 (type EXCL)
lola: time limit : 3262 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 5/3262

Time elapsed: 343 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 10/3262

Time elapsed: 348 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 15/3262

Time elapsed: 353 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 20/3262

Time elapsed: 358 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 25/3262

Time elapsed: 363 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 30/3262

Time elapsed: 368 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 35/3262

Time elapsed: 373 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 40/3262

Time elapsed: 378 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 45/3262

Time elapsed: 383 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 50/3262

Time elapsed: 388 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 55/3262

Time elapsed: 393 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 60/3262

Time elapsed: 398 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 65/3262

Time elapsed: 403 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 70/3262

Time elapsed: 408 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 75/3262

Time elapsed: 413 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 80/3262

Time elapsed: 418 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 85/3262

Time elapsed: 423 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 90/3262

Time elapsed: 428 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
13 CTL EXCL 95/3262

Time elapsed: 433 secs. Pages
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 13 (type
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 438 secs. Pages
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 443 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 448 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 453 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 458 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 463 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 468 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 473 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 478 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 483 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 488 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 493 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 498 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 503 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 508 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 513 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 518 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 523 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 528 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 533 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 538 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 543 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 548 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 553 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 558 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 563 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 568 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 573 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 578 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 583 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 588 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 593 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 598 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 603 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 608 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 613 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 618 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 623 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 628 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 633 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 638 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 643 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 648 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 653 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 658 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 663 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 668 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 673 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 678 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 683 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 688 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 693 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 698 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 703 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 708 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 713 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 718 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 723 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 728 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 733 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 738 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 743 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 748 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 753 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 758 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 763 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 768 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 773 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 778 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 783 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 788 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 793 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 798 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 803 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 808 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 813 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 818 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 823 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 828 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 833 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 838 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 843 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 848 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 853 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 858 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 863 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 868 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 873 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 878 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 883 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 888 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 893 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 898 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 903 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 908 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 913 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 918 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 923 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 928 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 933 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 938 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 943 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 948 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 953 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 958 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 963 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 968 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 973 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 978 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 983 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 988 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 993 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 998 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1003 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1008 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1013 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1018 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1023 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1028 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1033 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1038 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1043 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1048 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1053 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1058 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1063 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1068 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1073 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1078 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1083 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1088 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1093 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1098 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1103 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1108 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1113 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1118 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1123 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1128 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1133 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1138 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1143 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1148 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1153 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1158 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1163 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1168 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1173 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1178 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1183 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1188 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1193 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1198 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1203 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1208 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1213 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1218 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1223 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1228 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1233 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1238 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1243 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1248 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1253 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1258 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1263 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1268 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1273 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1278 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1283 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1288 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1293 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1298 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1303 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1308 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1313 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1318 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1323 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1328 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1333 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1338 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1343 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1348 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1353 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1358 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1363 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1368 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1373 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1378 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1383 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1388 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1393 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1398 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1403 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1408 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1413 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1418 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1423 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1428 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1433 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1438 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1443 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1448 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1453 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1458 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1463 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1468 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1473 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1478 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1483 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1488 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1493 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1498 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1503 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1508 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1513 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1518 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1523 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1528 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1533 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1538 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1543 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1548 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1553 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1558 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1563 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1568 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1573 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1578 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1583 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1588 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1593 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1598 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1603 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1608 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1613 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1618 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1623 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1628 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1633 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1638 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1643 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1648 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1653 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1658 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1663 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1668 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1673 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1678 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1683 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1688 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1693 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1698 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1703 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1708 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1713 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1718 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1723 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1728 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1733 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1738 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1743 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1748 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1753 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1758 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1763 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1768 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1773 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1778 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1783 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1788 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1793 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1798 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1803 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1808 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1813 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1818 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1823 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1828 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1833 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1838 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1843 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1848 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1853 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1858 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1863 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1868 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1873 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1878 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1883 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1888 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1893 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1898 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1903 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1908 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1913 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1918 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1923 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1928 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1933 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1938 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1943 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1948 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1953 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1958 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1963 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1968 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1973 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1978 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1983 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1988 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1993 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1998 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2003 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2008 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2013 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2018 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2023 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2028 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2033 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2038 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2043 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2048 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2053 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2058 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2063 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2068 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2073 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2078 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2083 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2088 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2093 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2098 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2103 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2108 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2113 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2118 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2123 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2128 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2133 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2138 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2143 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2148 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2153 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2158 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2163 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2168 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2173 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2178 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2183 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2188 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2193 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2198 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2203 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2208 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2213 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2218 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2223 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2228 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2233 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2238 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2243 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2248 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2253 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2258 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2263 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2268 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2273 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-01:
StigmergyCommit-PT-03b-CTLFireability-04:
StigmergyCommit-PT-03b-CTLFireability-12:
StigmergyCommit-PT-03b-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 2278 secs. Pages
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY
StigmergyCommit-PT-03b-CTLFireability-00:
StigmergyCommit-PT-03b-CTLFireability-02: SP ECTL
StigmergyCommit-PT-03b-CTLFireability-03: INITIAL
StigmergyCommit-PT-03b-CTLFireability-05:
StigmergyCommit-PT-03b-CTLFireability-06:
StigmergyCommit-PT-03b-CTLFireability-07:
StigmergyCommit-PT-03b-CTLFireability-08:
StigmergyCommit-PT-03b-CTLFireability-09:
StigmergyCommit-PT-03b-CTLFireability-10:
StigmergyCommit-PT-03b-CTLFireability-11:
StigmergyCommit-PT-03b-CTLFireability-15:

========== file over 1MB has been
retrieve it from the run archives
ll-167912647300418.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16 ssh) ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... ============================ examination is CTLFireability 300418 ============================ 26 10:51 CTLCardinality.txt 26 10:51 CTLCardinality.xml 26 10:51 CTLFireability.txt 26 10:51 CTLFireability.xml 25 17:11 LTLCardinality.txt 25 17:11 LTLCardinality.xml 25 17:11 LTLFireability.txt 25 17:11 LTLFireability.xml 26 10:52 ReachabilityCardinality.txt 26 10:52 ReachabilityCardinality.xml 26 10:52 ReachabilityFireability.txt 26 10:52 ReachabilityFireability.xml 25 17:11 UpperBounds.txt 25 17:11 UpperBounds.xml 5 18:23 equiv_col 5 18:23 instance 5 18:23 iscolored 5 18:23 model.pnml by BenchKit (invocation template) of booleans the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML] Parsing pnml file : /home/mcc/execution/model.pnml Load time of PNML (sax parser for PT used): 253 ms Transformed 1231 places. Transformed 1476 transitions. Found NUPN structural information; Parsed PT model containing 1231 places and 1476 transitions and 4168 arcs in 546 ms. execution/CTLFireability.xml in 23 ms. places. Attempting structural reductions. LTL mode, iteration 0 : 1231/1231 places, 1476/1476 transitions. with 91 rule applications. Total rules 91 place count 1140 transition count 1385 91 rules applied. Total rules applied 182 place count 1140 transition count 1385 with 49 rule applications. Total rules 231 place count 1091 transition count 1336 49 rules applied. Total rules applied 280 place count 1091 transition count 1336 with 24 rule applications. Total rules 304 place count 1067 transition count 1312 24 rules applied. Total rules applied 328 place count 1067 transition count 1312 with 20 rule applications. Total rules 348 place count 1047 transition count 1292 20 rules applied. Total rules applied 368 place count 1047 transition count 1292 with 18 rule applications. Total rules 386 place count 1029 transition count 1274 18 rules applied. Total rules applied 404 place count 1029 transition count 1274 with 18 rule applications. Total rules 422 place count 1011 transition count 1256 18 rules applied. Total rules applied 440 place count 1011 transition count 1256 with 17 rule applications. Total rules 457 place count 994 transition count 1239 17 rules applied. Total rules applied 474 place count 994 transition count 1239 with 15 rule applications. Total rules 489 place count 979 transition count 1224 15 rules applied. Total rules applied 504 place count 979 transition count 1224 with 13 rule applications. Total rules 517 place count 966 transition count 1211 13 rules applied. Total rules applied 530 place count 966 transition count 1211 with 8 rule applications. Total rules 538 place count 958 transition count 1203 8 rules applied. Total rules applied 546 place count 958 transition count 1203 with 5 rule applications. Total rules 551 place count 953 transition count 1198 5 rules applied. Total rules applied 556 place count 953 transition count 1198 with 4 rule applications. Total rules 560 place count 949 transition count 1194 4 rules applied. Total rules applied 564 place count 949 transition count 1194 with 1 rule applications. Total rules 565 place count 948 transition count 1193 1 rules applied. Total rules applied 566 place count 948 transition count 1193 with 1 rule applications. Total rules 567 place count 947 transition count 1192 1 rules applied. Total rules applied 568 place count 947 transition count 1192 with 1 rule applications. Total rules 569 place count 946 transition count 1191 1 rules applied. Total rules applied 570 place count 946 transition count 1191 with 1 rule applications. Total rules 571 place count 945 transition count 1190 1 rules applied. Total rules applied 572 place count 945 transition count 1190 with 1 rule applications. Total rules 573 place count 944 transition count 1189 1 rules applied. Total rules applied 574 place count 944 transition count 1189 with 1 rule applications. Total rules 575 place count 943 transition count 1188 1 rules applied. Total rules applied 576 place count 943 transition count 1188 with 1 rule applications. Total rules 577 place count 942 transition count 1187 1 rules applied. Total rules applied 578 place count 942 transition count 1187 with 1 rule applications. Total rules 579 place count 941 transition count 1186 1 rules applied. Total rules applied 580 place count 941 transition count 1186 with 1 rule applications. Total rules 581 place count 940 transition count 1185 1 rules applied. Total rules applied 582 place count 940 transition count 1185 with 1 rule applications. Total rules 583 place count 939 transition count 1184 1 rules applied. Total rules applied 584 place count 939 transition count 1184 1 transitions. 1 rules applied. Total rules applied 585 place count 939 transition count 1183 1567 ms. Remains 939 /1231 variables (removed 292) and now considering 1183/1476 (removed 293) transitions. Computed 5 place invariants in 35 ms Implicit Places using invariants in 619 ms returned [] Invariant cache hit. Implicit Places using invariants and state equation in 721 ms returned [] with State Equation took 1387 ms to find 0 implicit places. Invariant cache hit. Dead Transitions using invariants and state equation in 1204 ms found 0 transitions. LTL mode, iteration 1 : 939/1231 places, 1183/1476 transitions. LTL mode , in 1 iterations and 4162 ms. Remains : 939/1231 places, 1183/1476 transitions. places after structural reductions. Flatten gal took : 195 ms Flatten gal took : 104 ms Input system was already deterministic with 1183 transitions. places (down from 113) after GAL structural reductions. steps, including 130 resets, run finished after 848 ms. (steps per millisecond=11 ) properties (out of 66) seen :22 steps, including 3 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 44) seen :0 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 44) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 44) seen :0 Invariant cache hit. [Real]Absence check using 5 positive place invariants in 15 ms returned sat After 2261ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:43 [Nat]Absence check using 5 positive place invariants in 11 ms returned sat After 2744ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :41 Deduced a trap composed of 335 places in 580 ms of which 6 ms to minimize. Deduced a trap composed of 339 places in 713 ms of which 3 ms to minimize. Deduced a trap composed of 321 places in 630 ms of which 3 ms to minimize. Trap strengthening (SAT) tested/added 4/3 trap constraints in 2140 ms Deduced a trap composed of 323 places in 381 ms of which 3 ms to minimize. Trap strengthening (SAT) tested/added 2/1 trap constraints in 522 ms Deduced a trap composed of 344 places in 567 ms of which 2 ms to minimize. Deduced a trap composed of 347 places in 452 ms of which 1 ms to minimize. Trap strengthening (SAT) tested/added 3/2 trap constraints in 1232 ms Deduced a trap composed of 345 places in 373 ms of which 1 ms to minimize. Trap strengthening (SAT) tested/added 2/1 trap constraints in 528 ms Deduced a trap composed of 329 places in 379 ms of which 2 ms to minimize. Trap strengthening (SAT) tested/added 2/1 trap constraints in 533 ms Deduced a trap composed of 319 places in 423 ms of which 1 ms to minimize. Trap strengthening (SAT) tested/added 2/1 trap constraints in 557 ms Deduced a trap composed of 345 places in 436 ms of which 1 ms to minimize. Trap strengthening (SAT) tested/added 2/1 trap constraints in 571 ms Deduced a trap composed of 326 places in 612 ms of which 4 ms to minimize. Deduced a trap composed of 340 places in 488 ms of which 1 ms to minimize. Trap strengthening (SAT) tested/added 3/2 trap constraints in 1298 ms Deduced a trap composed of 347 places in 615 ms of which 2 ms to minimize. Trap strengthening (SAT) tested/added 2/1 trap constraints in 731 ms After 15328ms SMT Verify possible using trap constraints in natural domain returned unsat :4 sat :40 found. After 19446ms SMT Verify possible using all constraints in natural domain returned unsat :4 sat :40 different solutions. in 532 ms. Attempting structural reductions. REACHABILITY mode, iteration 0 : 939/939 places, 1183/1183 transitions. 939 vertex of which 67 / 939 are part of one of the 11 SCC in 7 ms 74 transitions. and 883 vertex of which 879 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.4 ms 4 transitions. 644 transitions Transition count delta: 644 648 rules applied. Total rules applied 650 place count 879 transition count 461 and 0 transitions. 6 transitions. 5 transitions Transition count delta: 5 655 rules applied. Total rules applied 1305 place count 235 transition count 450 0 transitions. F-continuation condition.Transition count delta: 6 11 rules applied. Total rules applied 1316 place count 230 transition count 444 0 transitions. 6 rules applied. Total rules applied 1322 place count 224 transition count 444 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1322 place count 224 transition count 395 places in 0 ms and 0 transitions. 98 rules applied. Total rules applied 1420 place count 175 transition count 395 with 10 rule applications. Total rules 1430 place count 165 transition count 384 10 rules applied. Total rules applied 1440 place count 165 transition count 384 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1440 place count 165 transition count 381 in 0 ms 0 transitions. 6 rules applied. Total rules applied 1446 place count 162 transition count 381 with 6 rule applications. Total rules 1452 place count 156 transition count 348 6 rules applied. Total rules applied 1458 place count 156 transition count 348 2 transitions. 2 rules applied. Total rules applied 1460 place count 156 transition count 346 with 1 rule applications. Total rules 1461 place count 155 transition count 345 1 rules applied. Total rules applied 1462 place count 155 transition count 345 with 1 rule applications. Total rules 1463 place count 154 transition count 344 1 rules applied. Total rules applied 1464 place count 154 transition count 344 using F-continuation condition with reduction of 1 identical transitions. places in 0 ms and 0 transitions. 48 rules applied. Total rules applied 1512 place count 130 transition count 319 7 transitions. 7 rules applied. Total rules applied 1519 place count 130 transition count 312 with 17 rule applications. Total rules 1536 place count 113 transition count 193 17 rules applied. Total rules applied 1553 place count 113 transition count 193 8 transitions. 8 rules applied. Total rules applied 1561 place count 113 transition count 185 with 7 rule applications. Total rules 1568 place count 106 transition count 178 7 rules applied. Total rules applied 1575 place count 106 transition count 178 with 7 rule applications. Total rules 1582 place count 99 transition count 171 7 rules applied. Total rules applied 1589 place count 99 transition count 171 4 transitions. 4 rules applied. Total rules applied 1593 place count 99 transition count 167 F-continuation condition.Transition count delta: 6 in 0 ms 0 transitions. 12 rules applied. Total rules applied 1605 place count 93 transition count 161 F-continuation condition.Transition count delta: -8 in 0 ms 0 transitions. 6 rules applied. Total rules applied 1611 place count 90 transition count 169 rules discarded 1 transitions 1 rules applied. Total rules applied 1612 place count 90 transition count 168 32 times. 32 rules applied. Total rules applied 1644 place count 90 transition count 136 and 0 transitions. 3 transitions. 35 rules applied. Total rules applied 1679 place count 58 transition count 133 rules discarded 18 transitions 18 rules applied. Total rules applied 1697 place count 58 transition count 115 applied 5 times. 5 rules applied. Total rules applied 1702 place count 58 transition count 115 182 ms. Remains 58 /939 variables (removed 881) and now considering 115/1183 (removed 1068) transitions. REACHABILITY mode , in 1 iterations and 182 ms. Remains : 58/939 places, 115/1183 transitions. steps, including 260 resets, run finished after 311 ms. (steps per millisecond=32 ) properties (out of 15) seen :12 steps, including 53 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 3) seen :2 steps, including 51 resets, run finished after 11 ms. (steps per millisecond=909 ) properties (out of 1) seen :0 Computed 5 place invariants in 2 ms [Real]Absence check using 5 positive place invariants in 3 ms returned sat After 56ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 State equation strengthened by 27 read => feed constraints. After 14ms SMT Verify possible using 27 Read/Feed constraints in real domain returned unsat :0 sat :1 Deduced a trap composed of 13 places in 57 ms of which 1 ms to minimize. Deduced a trap composed of 13 places in 59 ms of which 0 ms to minimize. Deduced a trap composed of 12 places in 32 ms of which 1 ms to minimize. Trap strengthening (SAT) tested/added 4/3 trap constraints in 176 ms After 198ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1 After 299ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1 [Nat]Absence check using 5 positive place invariants in 2 ms returned sat After 40ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1 After 11ms SMT Verify possible using 27 Read/Feed constraints in natural domain returned unsat :0 sat :1 Deduced a trap composed of 13 places in 38 ms of which 1 ms to minimize. Deduced a trap composed of 13 places in 34 ms of which 1 ms to minimize. Deduced a trap composed of 12 places in 28 ms of which 1 ms to minimize. Trap strengthening (SAT) tested/added 4/3 trap constraints in 125 ms After 146ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1 found. After 225ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1 Attempting structural reductions. REACHABILITY mode, iteration 0 : 58/58 places, 115/115 transitions. 58 vertex of which 2 / 58 are part of one of the 1 SCC in 0 ms 2 transitions. 12 transitions Transition count delta: 12 12 rules applied. Total rules applied 13 place count 57 transition count 101 and 0 transitions. 1 transitions. 13 rules applied. Total rules applied 26 place count 45 transition count 100 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 26 place count 45 transition count 98 in 0 ms 0 transitions. 4 rules applied. Total rules applied 30 place count 43 transition count 98 with 3 rule applications. Total rules 33 place count 40 transition count 95 3 rules applied. Total rules applied 36 place count 40 transition count 95 1 transitions. 1 rules applied. Total rules applied 37 place count 40 transition count 94 F-continuation condition.Transition count delta: 5 in 0 ms 0 transitions. 10 rules applied. Total rules applied 47 place count 35 transition count 89 3 transitions. 3 rules applied. Total rules applied 50 place count 35 transition count 86 with 5 rule applications. Total rules 55 place count 30 transition count 81 5 rules applied. Total rules applied 60 place count 30 transition count 81 14 transitions. 14 rules applied. Total rules applied 74 place count 30 transition count 67 with 1 rule applications. Total rules 75 place count 29 transition count 66 1 rules applied. Total rules applied 76 place count 29 transition count 66 rules discarded 2 transitions 2 rules applied. Total rules applied 78 place count 29 transition count 64 1 rules applied. Total rules applied 79 place count 29 transition count 63 0 transitions. 1 rules applied. Total rules applied 80 place count 28 transition count 63 with 4 rule applications. Total rules 84 place count 24 transition count 59 4 rules applied. Total rules applied 88 place count 24 transition count 59 applied 4 times. 4 rules applied. Total rules applied 92 place count 24 transition count 59 2 transitions. 2 rules applied. Total rules applied 94 place count 24 transition count 57 rules discarded 2 transitions 2 rules applied. Total rules applied 96 place count 24 transition count 55 ms. Remains 24 /58 variables (removed 34) and now considering 55/115 (removed 60) transitions. REACHABILITY mode , in 1 iterations and 37 ms. Remains : 24/58 places, 55/115 transitions. steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=156 ) propositions for a total of 16 simplifications. Initial state reduction rules for CTL removed 1 formulas. Flatten gal took : 67 ms TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE ] Flatten gal took : 70 ms Input system was already deterministic with 1183 transitions. (down from 98) after GAL structural reductions. places and 187 stable transitions SI_CTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. 939 vertex of which 74 / 939 are part of one of the 12 SCC in 3 ms 70 transitions. 1 transitions. 659 transitions Transition count delta: 659 659 rules applied. Total rules applied 660 place count 876 transition count 453 and 0 transitions. 6 transitions. 4 transitions Transition count delta: 4 669 rules applied. Total rules applied 1329 place count 217 transition count 443 0 transitions. F-continuation condition.Transition count delta: 6 10 rules applied. Total rules applied 1339 place count 213 transition count 437 0 transitions. 1 transitions. F-continuation condition.Transition count delta: 1 8 rules applied. Total rules applied 1347 place count 207 transition count 435 0 transitions. 1 rules applied. Total rules applied 1348 place count 206 transition count 435 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1348 place count 206 transition count 390 places in 0 ms and 0 transitions. 90 rules applied. Total rules applied 1438 place count 161 transition count 390 with 18 rule applications. Total rules 1456 place count 143 transition count 371 18 rules applied. Total rules applied 1474 place count 143 transition count 371 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1474 place count 143 transition count 368 in 0 ms 0 transitions. 6 rules applied. Total rules applied 1480 place count 140 transition count 368 with 9 rule applications. Total rules 1489 place count 131 transition count 332 9 rules applied. Total rules applied 1498 place count 131 transition count 332 3 transitions. 3 rules applied. Total rules applied 1501 place count 131 transition count 329 with 3 rule applications. Total rules 1504 place count 128 transition count 325 3 rules applied. Total rules applied 1507 place count 128 transition count 325 1 transitions. 1 rules applied. Total rules applied 1508 place count 128 transition count 324 with 1 rule applications. Total rules 1509 place count 127 transition count 323 1 rules applied. Total rules applied 1510 place count 127 transition count 323 using F-continuation condition.Transition count delta: 19 places in 0 ms and 0 transitions. 38 rules applied. Total rules applied 1548 place count 108 transition count 304 5 transitions. 5 rules applied. Total rules applied 1553 place count 108 transition count 299 with 20 rule applications. Total rules 1573 place count 88 transition count 180 20 rules applied. Total rules applied 1593 place count 88 transition count 180 10 transitions. 10 rules applied. Total rules applied 1603 place count 88 transition count 170 with 11 rule applications. Total rules 1614 place count 77 transition count 156 11 rules applied. Total rules applied 1625 place count 77 transition count 156 with 11 rule applications. Total rules 1636 place count 66 transition count 142 11 rules applied. Total rules applied 1647 place count 66 transition count 142 5 transitions. 5 rules applied. Total rules applied 1652 place count 66 transition count 137 F-continuation condition.Transition count delta: 1 in 0 ms 0 transitions. 2 rules applied. Total rules applied 1654 place count 65 transition count 136 with 1 rule applications. Total rules 1655 place count 64 transition count 132 1 rules applied. Total rules applied 1656 place count 64 transition count 132 1 transitions. 1 rules applied. Total rules applied 1657 place count 64 transition count 131 rules discarded 4 transitions 4 rules applied. Total rules applied 1661 place count 64 transition count 127 F-continuation condition.Transition count delta: 4 in 0 ms 0 transitions. 8 rules applied. Total rules applied 1669 place count 60 transition count 123 1 transitions. 1 rules applied. Total rules applied 1670 place count 59 transition count 122 121 ms. Remains 59 /939 variables (removed 880) and now considering 122/1183 (removed 1061) transitions. SI_CTL mode , in 1 iterations and 121 ms. Remains : 59/939 places, 122/1183 transitions. Flatten gal took : 8 ms Flatten gal took : 8 ms Input system was already deterministic with 122 transitions. LTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. with 26 rule applications. Total rules 26 place count 913 transition count 1157 26 rules applied. Total rules applied 52 place count 913 transition count 1157 with 20 rule applications. Total rules 72 place count 893 transition count 1137 20 rules applied. Total rules applied 92 place count 893 transition count 1137 with 15 rule applications. Total rules 107 place count 878 transition count 1122 15 rules applied. Total rules applied 122 place count 878 transition count 1122 with 12 rule applications. Total rules 134 place count 866 transition count 1110 12 rules applied. Total rules applied 146 place count 866 transition count 1110 1 transitions. 1 rules applied. Total rules applied 147 place count 866 transition count 1109 with 11 rule applications. Total rules 158 place count 855 transition count 1098 11 rules applied. Total rules applied 169 place count 855 transition count 1098 with 10 rule applications. Total rules 179 place count 845 transition count 1088 10 rules applied. Total rules applied 189 place count 845 transition count 1088 with 10 rule applications. Total rules 199 place count 835 transition count 1078 10 rules applied. Total rules applied 209 place count 835 transition count 1078 with 9 rule applications. Total rules 218 place count 826 transition count 1069 9 rules applied. Total rules applied 227 place count 826 transition count 1069 2 transitions. 2 rules applied. Total rules applied 229 place count 826 transition count 1067 with 6 rule applications. Total rules 235 place count 820 transition count 1061 6 rules applied. Total rules applied 241 place count 820 transition count 1061 1 transitions. 1 rules applied. Total rules applied 242 place count 820 transition count 1060 with 4 rule applications. Total rules 246 place count 816 transition count 1056 4 rules applied. Total rules applied 250 place count 816 transition count 1056 1 transitions. 1 rules applied. Total rules applied 251 place count 816 transition count 1055 with 3 rule applications. Total rules 254 place count 813 transition count 1052 3 rules applied. Total rules applied 257 place count 813 transition count 1052 1 transitions. 1 rules applied. Total rules applied 258 place count 813 transition count 1051 with 2 rule applications. Total rules 260 place count 811 transition count 1049 2 rules applied. Total rules applied 262 place count 811 transition count 1049 with 1 rule applications. Total rules 263 place count 810 transition count 1048 1 rules applied. Total rules applied 264 place count 810 transition count 1048 with 1 rule applications. Total rules 265 place count 809 transition count 1047 1 rules applied. Total rules applied 266 place count 809 transition count 1047 with 1 rule applications. Total rules 267 place count 808 transition count 1046 1 rules applied. Total rules applied 268 place count 808 transition count 1046 with 1 rule applications. Total rules 269 place count 807 transition count 1045 1 rules applied. Total rules applied 270 place count 807 transition count 1045 with 1 rule applications. Total rules 271 place count 806 transition count 1044 1 rules applied. Total rules applied 272 place count 806 transition count 1044 with 1 rule applications. Total rules 273 place count 805 transition count 1043 1 rules applied. Total rules applied 274 place count 805 transition count 1043 with 1 rule applications. Total rules 275 place count 804 transition count 1042 1 rules applied. Total rules applied 276 place count 804 transition count 1042 1 transitions. 1 rules applied. Total rules applied 277 place count 804 transition count 1041 870 ms. Remains 804 /939 variables (removed 135) and now considering 1041/1183 (removed 142) transitions. LTL mode , in 1 iterations and 878 ms. Remains : 804/939 places, 1041/1183 transitions. Flatten gal took : 36 ms Flatten gal took : 38 ms Input system was already deterministic with 1041 transitions. SI_CTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. 939 vertex of which 74 / 939 are part of one of the 12 SCC in 1 ms 70 transitions. 1 transitions. 660 transitions Transition count delta: 660 660 rules applied. Total rules applied 661 place count 876 transition count 452 and 0 transitions. 7 transitions. 5 transitions Transition count delta: 5 672 rules applied. Total rules applied 1333 place count 216 transition count 440 0 transitions. F-continuation condition.Transition count delta: 1 6 rules applied. Total rules applied 1339 place count 211 transition count 439 0 transitions. 1 rules applied. Total rules applied 1340 place count 210 transition count 439 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1340 place count 210 transition count 394 places in 1 ms and 0 transitions. 90 rules applied. Total rules applied 1430 place count 165 transition count 394 with 18 rule applications. Total rules 1448 place count 147 transition count 375 18 rules applied. Total rules applied 1466 place count 147 transition count 375 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1466 place count 147 transition count 372 in 0 ms 0 transitions. 6 rules applied. Total rules applied 1472 place count 144 transition count 372 with 9 rule applications. Total rules 1481 place count 135 transition count 336 9 rules applied. Total rules applied 1490 place count 135 transition count 336 3 transitions. 3 rules applied. Total rules applied 1493 place count 135 transition count 333 with 3 rule applications. Total rules 1496 place count 132 transition count 329 3 rules applied. Total rules applied 1499 place count 132 transition count 329 1 transitions. 1 rules applied. Total rules applied 1500 place count 132 transition count 328 with 1 rule applications. Total rules 1501 place count 131 transition count 327 1 rules applied. Total rules applied 1502 place count 131 transition count 327 using F-continuation condition.Transition count delta: 19 places in 0 ms and 0 transitions. 38 rules applied. Total rules applied 1540 place count 112 transition count 308 4 transitions. 4 rules applied. Total rules applied 1544 place count 112 transition count 304 with 20 rule applications. Total rules 1564 place count 92 transition count 185 20 rules applied. Total rules applied 1584 place count 92 transition count 185 9 transitions. 9 rules applied. Total rules applied 1593 place count 92 transition count 176 with 11 rule applications. Total rules 1604 place count 81 transition count 162 11 rules applied. Total rules applied 1615 place count 81 transition count 162 with 11 rule applications. Total rules 1626 place count 70 transition count 148 11 rules applied. Total rules applied 1637 place count 70 transition count 148 5 transitions. 5 rules applied. Total rules applied 1642 place count 70 transition count 143 F-continuation condition.Transition count delta: 1 in 0 ms 0 transitions. 2 rules applied. Total rules applied 1644 place count 69 transition count 142 with 1 rule applications. Total rules 1645 place count 68 transition count 138 1 rules applied. Total rules applied 1646 place count 68 transition count 138 1 transitions. 1 rules applied. Total rules applied 1647 place count 68 transition count 137 rules discarded 4 transitions 4 rules applied. Total rules applied 1651 place count 68 transition count 133 F-continuation condition.Transition count delta: 4 in 0 ms 0 transitions. 8 rules applied. Total rules applied 1659 place count 64 transition count 129 1 transitions. 1 rules applied. Total rules applied 1660 place count 63 transition count 128 99 ms. Remains 63 /939 variables (removed 876) and now considering 128/1183 (removed 1055) transitions. SI_CTL mode , in 1 iterations and 100 ms. Remains : 63/939 places, 128/1183 transitions. Flatten gal took : 5 ms Flatten gal took : 5 ms Input system was already deterministic with 128 transitions. LTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. with 29 rule applications. Total rules 29 place count 910 transition count 1154 29 rules applied. Total rules applied 58 place count 910 transition count 1154 with 22 rule applications. Total rules 80 place count 888 transition count 1132 22 rules applied. Total rules applied 102 place count 888 transition count 1132 with 17 rule applications. Total rules 119 place count 871 transition count 1115 17 rules applied. Total rules applied 136 place count 871 transition count 1115 with 13 rule applications. Total rules 149 place count 858 transition count 1102 13 rules applied. Total rules applied 162 place count 858 transition count 1102 1 transitions. 1 rules applied. Total rules applied 163 place count 858 transition count 1101 with 12 rule applications. Total rules 175 place count 846 transition count 1089 12 rules applied. Total rules applied 187 place count 846 transition count 1089 with 11 rule applications. Total rules 198 place count 835 transition count 1078 11 rules applied. Total rules applied 209 place count 835 transition count 1078 with 11 rule applications. Total rules 220 place count 824 transition count 1067 11 rules applied. Total rules applied 231 place count 824 transition count 1067 with 10 rule applications. Total rules 241 place count 814 transition count 1057 10 rules applied. Total rules applied 251 place count 814 transition count 1057 2 transitions. 2 rules applied. Total rules applied 253 place count 814 transition count 1055 with 7 rule applications. Total rules 260 place count 807 transition count 1048 7 rules applied. Total rules applied 267 place count 807 transition count 1048 1 transitions. 1 rules applied. Total rules applied 268 place count 807 transition count 1047 with 5 rule applications. Total rules 273 place count 802 transition count 1042 5 rules applied. Total rules applied 278 place count 802 transition count 1042 1 transitions. 1 rules applied. Total rules applied 279 place count 802 transition count 1041 with 3 rule applications. Total rules 282 place count 799 transition count 1038 3 rules applied. Total rules applied 285 place count 799 transition count 1038 1 transitions. 1 rules applied. Total rules applied 286 place count 799 transition count 1037 with 2 rule applications. Total rules 288 place count 797 transition count 1035 2 rules applied. Total rules applied 290 place count 797 transition count 1035 with 1 rule applications. Total rules 291 place count 796 transition count 1034 1 rules applied. Total rules applied 292 place count 796 transition count 1034 with 1 rule applications. Total rules 293 place count 795 transition count 1033 1 rules applied. Total rules applied 294 place count 795 transition count 1033 with 1 rule applications. Total rules 295 place count 794 transition count 1032 1 rules applied. Total rules applied 296 place count 794 transition count 1032 with 1 rule applications. Total rules 297 place count 793 transition count 1031 1 rules applied. Total rules applied 298 place count 793 transition count 1031 with 1 rule applications. Total rules 299 place count 792 transition count 1030 1 rules applied. Total rules applied 300 place count 792 transition count 1030 with 1 rule applications. Total rules 301 place count 791 transition count 1029 1 rules applied. Total rules applied 302 place count 791 transition count 1029 with 1 rule applications. Total rules 303 place count 790 transition count 1028 1 rules applied. Total rules applied 304 place count 790 transition count 1028 1 transitions. 1 rules applied. Total rules applied 305 place count 790 transition count 1027 586 ms. Remains 790 /939 variables (removed 149) and now considering 1027/1183 (removed 156) transitions. LTL mode , in 1 iterations and 587 ms. Remains : 790/939 places, 1027/1183 transitions. Flatten gal took : 32 ms Flatten gal took : 34 ms Input system was already deterministic with 1027 transitions. LTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. with 28 rule applications. Total rules 28 place count 911 transition count 1155 28 rules applied. Total rules applied 56 place count 911 transition count 1155 with 21 rule applications. Total rules 77 place count 890 transition count 1134 21 rules applied. Total rules applied 98 place count 890 transition count 1134 with 16 rule applications. Total rules 114 place count 874 transition count 1118 16 rules applied. Total rules applied 130 place count 874 transition count 1118 with 11 rule applications. Total rules 141 place count 863 transition count 1107 11 rules applied. Total rules applied 152 place count 863 transition count 1107 1 transitions. 1 rules applied. Total rules applied 153 place count 863 transition count 1106 with 10 rule applications. Total rules 163 place count 853 transition count 1096 10 rules applied. Total rules applied 173 place count 853 transition count 1096 with 8 rule applications. Total rules 181 place count 845 transition count 1088 8 rules applied. Total rules applied 189 place count 845 transition count 1088 with 8 rule applications. Total rules 197 place count 837 transition count 1080 8 rules applied. Total rules applied 205 place count 837 transition count 1080 with 8 rule applications. Total rules 213 place count 829 transition count 1072 8 rules applied. Total rules applied 221 place count 829 transition count 1072 1 transitions. 1 rules applied. Total rules applied 222 place count 829 transition count 1071 with 7 rule applications. Total rules 229 place count 822 transition count 1064 7 rules applied. Total rules applied 236 place count 822 transition count 1064 1 transitions. 1 rules applied. Total rules applied 237 place count 822 transition count 1063 with 5 rule applications. Total rules 242 place count 817 transition count 1058 5 rules applied. Total rules applied 247 place count 817 transition count 1058 1 transitions. 1 rules applied. Total rules applied 248 place count 817 transition count 1057 with 3 rule applications. Total rules 251 place count 814 transition count 1054 3 rules applied. Total rules applied 254 place count 814 transition count 1054 1 transitions. 1 rules applied. Total rules applied 255 place count 814 transition count 1053 with 2 rule applications. Total rules 257 place count 812 transition count 1051 2 rules applied. Total rules applied 259 place count 812 transition count 1051 with 1 rule applications. Total rules 260 place count 811 transition count 1050 1 rules applied. Total rules applied 261 place count 811 transition count 1050 with 1 rule applications. Total rules 262 place count 810 transition count 1049 1 rules applied. Total rules applied 263 place count 810 transition count 1049 with 1 rule applications. Total rules 264 place count 809 transition count 1048 1 rules applied. Total rules applied 265 place count 809 transition count 1048 with 1 rule applications. Total rules 266 place count 808 transition count 1047 1 rules applied. Total rules applied 267 place count 808 transition count 1047 with 1 rule applications. Total rules 268 place count 807 transition count 1046 1 rules applied. Total rules applied 269 place count 807 transition count 1046 with 1 rule applications. Total rules 270 place count 806 transition count 1045 1 rules applied. Total rules applied 271 place count 806 transition count 1045 with 1 rule applications. Total rules 272 place count 805 transition count 1044 1 rules applied. Total rules applied 273 place count 805 transition count 1044 1 transitions. 1 rules applied. Total rules applied 274 place count 805 transition count 1043 609 ms. Remains 805 /939 variables (removed 134) and now considering 1043/1183 (removed 140) transitions. LTL mode , in 1 iterations and 609 ms. Remains : 805/939 places, 1043/1183 transitions. Flatten gal took : 35 ms Flatten gal took : 32 ms Input system was already deterministic with 1043 transitions. SI_CTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. 939 vertex of which 74 / 939 are part of one of the 12 SCC in 1 ms 70 transitions. 1 transitions. 659 transitions Transition count delta: 659 659 rules applied. Total rules applied 660 place count 876 transition count 453 and 0 transitions. 7 transitions. 5 transitions Transition count delta: 5 671 rules applied. Total rules applied 1331 place count 217 transition count 441 0 transitions. F-continuation condition.Transition count delta: 3 8 rules applied. Total rules applied 1339 place count 212 transition count 438 0 transitions. 3 rules applied. Total rules applied 1342 place count 209 transition count 438 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1342 place count 209 transition count 394 places in 0 ms and 0 transitions. 88 rules applied. Total rules applied 1430 place count 165 transition count 394 with 18 rule applications. Total rules 1448 place count 147 transition count 375 18 rules applied. Total rules applied 1466 place count 147 transition count 375 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1466 place count 147 transition count 372 in 0 ms 0 transitions. 6 rules applied. Total rules applied 1472 place count 144 transition count 372 with 9 rule applications. Total rules 1481 place count 135 transition count 336 9 rules applied. Total rules applied 1490 place count 135 transition count 336 3 transitions. 3 rules applied. Total rules applied 1493 place count 135 transition count 333 with 2 rule applications. Total rules 1495 place count 133 transition count 330 2 rules applied. Total rules applied 1497 place count 133 transition count 330 with 1 rule applications. Total rules 1498 place count 132 transition count 329 1 rules applied. Total rules applied 1499 place count 132 transition count 329 using F-continuation condition.Transition count delta: 19 places in 0 ms and 0 transitions. 38 rules applied. Total rules applied 1537 place count 113 transition count 310 5 transitions. 5 rules applied. Total rules applied 1542 place count 113 transition count 305 with 20 rule applications. Total rules 1562 place count 93 transition count 186 20 rules applied. Total rules applied 1582 place count 93 transition count 186 10 transitions. 10 rules applied. Total rules applied 1592 place count 93 transition count 176 with 11 rule applications. Total rules 1603 place count 82 transition count 162 11 rules applied. Total rules applied 1614 place count 82 transition count 162 with 11 rule applications. Total rules 1625 place count 71 transition count 148 11 rules applied. Total rules applied 1636 place count 71 transition count 148 5 transitions. 5 rules applied. Total rules applied 1641 place count 71 transition count 143 F-continuation condition.Transition count delta: 1 in 0 ms 0 transitions. 2 rules applied. Total rules applied 1643 place count 70 transition count 142 with 1 rule applications. Total rules 1644 place count 69 transition count 138 1 rules applied. Total rules applied 1645 place count 69 transition count 138 1 transitions. 1 rules applied. Total rules applied 1646 place count 69 transition count 137 rules discarded 4 transitions 4 rules applied. Total rules applied 1650 place count 69 transition count 133 F-continuation condition.Transition count delta: 4 in 1 ms 0 transitions. 8 rules applied. Total rules applied 1658 place count 65 transition count 129 1 transitions. 1 rules applied. Total rules applied 1659 place count 64 transition count 128 67 ms. Remains 64 /939 variables (removed 875) and now considering 128/1183 (removed 1055) transitions. SI_CTL mode , in 1 iterations and 68 ms. Remains : 64/939 places, 128/1183 transitions. Flatten gal took : 5 ms Flatten gal took : 5 ms Input system was already deterministic with 128 transitions. SI_CTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. 939 vertex of which 74 / 939 are part of one of the 12 SCC in 2 ms 70 transitions. 1 transitions. 650 transitions Transition count delta: 650 650 rules applied. Total rules applied 651 place count 876 transition count 462 and 0 transitions. 7 transitions. 5 transitions Transition count delta: 5 662 rules applied. Total rules applied 1313 place count 226 transition count 450 0 transitions. F-continuation condition.Transition count delta: 1 6 rules applied. Total rules applied 1319 place count 221 transition count 449 0 transitions. 1 rules applied. Total rules applied 1320 place count 220 transition count 449 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1320 place count 220 transition count 404 places in 1 ms and 0 transitions. 90 rules applied. Total rules applied 1410 place count 175 transition count 404 with 17 rule applications. Total rules 1427 place count 158 transition count 386 17 rules applied. Total rules applied 1444 place count 158 transition count 386 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1444 place count 158 transition count 383 in 0 ms 0 transitions. 6 rules applied. Total rules applied 1450 place count 155 transition count 383 with 7 rule applications. Total rules 1457 place count 148 transition count 375 7 rules applied. Total rules applied 1464 place count 148 transition count 375 2 transitions. 2 rules applied. Total rules applied 1466 place count 148 transition count 373 with 3 rule applications. Total rules 1469 place count 145 transition count 369 3 rules applied. Total rules applied 1472 place count 145 transition count 369 1 transitions. 1 rules applied. Total rules applied 1473 place count 145 transition count 368 with 1 rule applications. Total rules 1474 place count 144 transition count 367 1 rules applied. Total rules applied 1475 place count 144 transition count 367 using F-continuation condition.Transition count delta: 20 places in 0 ms and 0 transitions. 40 rules applied. Total rules applied 1515 place count 124 transition count 347 4 transitions. 4 rules applied. Total rules applied 1519 place count 124 transition count 343 with 17 rule applications. Total rules 1536 place count 107 transition count 262 17 rules applied. Total rules applied 1553 place count 107 transition count 262 5 transitions. 5 rules applied. Total rules applied 1558 place count 107 transition count 257 with 10 rule applications. Total rules 1568 place count 97 transition count 244 10 rules applied. Total rules applied 1578 place count 97 transition count 244 with 10 rule applications. Total rules 1588 place count 87 transition count 231 10 rules applied. Total rules applied 1598 place count 87 transition count 231 4 transitions. 4 rules applied. Total rules applied 1602 place count 87 transition count 227 F-continuation condition.Transition count delta: 1 in 0 ms 0 transitions. 2 rules applied. Total rules applied 1604 place count 86 transition count 226 with 1 rule applications. Total rules 1605 place count 85 transition count 222 1 rules applied. Total rules applied 1606 place count 85 transition count 222 1 transitions. 1 rules applied. Total rules applied 1607 place count 85 transition count 221 rules discarded 4 transitions 4 rules applied. Total rules applied 1611 place count 85 transition count 217 F-continuation condition.Transition count delta: 4 in 0 ms 0 transitions. 8 rules applied. Total rules applied 1619 place count 81 transition count 213 1 transitions. 1 rules applied. Total rules applied 1620 place count 80 transition count 212 90 ms. Remains 80 /939 variables (removed 859) and now considering 212/1183 (removed 971) transitions. SI_CTL mode , in 1 iterations and 90 ms. Remains : 80/939 places, 212/1183 transitions. Flatten gal took : 16 ms Flatten gal took : 17 ms Input system was already deterministic with 212 transitions. SI_CTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. 939 vertex of which 67 / 939 are part of one of the 11 SCC in 1 ms 63 transitions. 1 transitions. 625 transitions Transition count delta: 625 625 rules applied. Total rules applied 626 place count 882 transition count 494 and 0 transitions. 6 transitions. 5 transitions Transition count delta: 5 636 rules applied. Total rules applied 1262 place count 257 transition count 483 0 transitions. using F-continuation condition.Transition count delta: 19 24 rules applied. Total rules applied 1286 place count 252 transition count 464 and 0 transitions. 1 transitions. 20 rules applied. Total rules applied 1306 place count 233 transition count 463 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1306 place count 233 transition count 417 places in 0 ms and 0 transitions. 92 rules applied. Total rules applied 1398 place count 187 transition count 417 with 16 rule applications. Total rules 1414 place count 171 transition count 400 16 rules applied. Total rules applied 1430 place count 171 transition count 400 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1430 place count 171 transition count 399 in 0 ms 0 transitions. 2 rules applied. Total rules applied 1432 place count 170 transition count 399 with 8 rule applications. Total rules 1440 place count 162 transition count 364 8 rules applied. Total rules applied 1448 place count 162 transition count 364 3 transitions. 3 rules applied. Total rules applied 1451 place count 162 transition count 361 with 2 rule applications. Total rules 1453 place count 160 transition count 358 2 rules applied. Total rules applied 1455 place count 160 transition count 358 with 1 rule applications. Total rules 1456 place count 159 transition count 357 1 rules applied. Total rules applied 1457 place count 159 transition count 357 using F-continuation condition.Transition count delta: 21 places in 0 ms and 0 transitions. 42 rules applied. Total rules applied 1499 place count 138 transition count 336 5 transitions. 5 rules applied. Total rules applied 1504 place count 138 transition count 331 with 13 rule applications. Total rules 1517 place count 125 transition count 299 13 rules applied. Total rules applied 1530 place count 125 transition count 299 3 transitions. 3 rules applied. Total rules applied 1533 place count 125 transition count 296 with 10 rule applications. Total rules 1543 place count 115 transition count 284 10 rules applied. Total rules applied 1553 place count 115 transition count 284 with 9 rule applications. Total rules 1562 place count 106 transition count 274 9 rules applied. Total rules applied 1571 place count 106 transition count 274 4 transitions. 4 rules applied. Total rules applied 1575 place count 106 transition count 270 F-continuation condition.Transition count delta: 1 in 1 ms 0 transitions. 2 rules applied. Total rules applied 1577 place count 105 transition count 269 with 1 rule applications. Total rules 1578 place count 104 transition count 263 1 rules applied. Total rules applied 1579 place count 104 transition count 263 1 transitions. 1 rules applied. Total rules applied 1580 place count 104 transition count 262 rules discarded 4 transitions 4 rules applied. Total rules applied 1584 place count 104 transition count 258 F-continuation condition.Transition count delta: 4 in 0 ms 0 transitions. 8 rules applied. Total rules applied 1592 place count 100 transition count 254 applied 1 times. 1 rules applied. Total rules applied 1593 place count 100 transition count 254 1 transitions. 1 rules applied. Total rules applied 1594 place count 99 transition count 253 110 ms. Remains 99 /939 variables (removed 840) and now considering 253/1183 (removed 930) transitions. SI_CTL mode , in 1 iterations and 110 ms. Remains : 99/939 places, 253/1183 transitions. Flatten gal took : 20 ms Flatten gal took : 21 ms Input system was already deterministic with 253 transitions. LTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. with 26 rule applications. Total rules 26 place count 913 transition count 1157 26 rules applied. Total rules applied 52 place count 913 transition count 1157 with 20 rule applications. Total rules 72 place count 893 transition count 1137 20 rules applied. Total rules applied 92 place count 893 transition count 1137 with 16 rule applications. Total rules 108 place count 877 transition count 1121 16 rules applied. Total rules applied 124 place count 877 transition count 1121 with 13 rule applications. Total rules 137 place count 864 transition count 1108 13 rules applied. Total rules applied 150 place count 864 transition count 1108 1 transitions. 1 rules applied. Total rules applied 151 place count 864 transition count 1107 with 12 rule applications. Total rules 163 place count 852 transition count 1095 12 rules applied. Total rules applied 175 place count 852 transition count 1095 with 11 rule applications. Total rules 186 place count 841 transition count 1084 11 rules applied. Total rules applied 197 place count 841 transition count 1084 with 11 rule applications. Total rules 208 place count 830 transition count 1073 11 rules applied. Total rules applied 219 place count 830 transition count 1073 with 10 rule applications. Total rules 229 place count 820 transition count 1063 10 rules applied. Total rules applied 239 place count 820 transition count 1063 2 transitions. 2 rules applied. Total rules applied 241 place count 820 transition count 1061 with 7 rule applications. Total rules 248 place count 813 transition count 1054 7 rules applied. Total rules applied 255 place count 813 transition count 1054 1 transitions. 1 rules applied. Total rules applied 256 place count 813 transition count 1053 with 5 rule applications. Total rules 261 place count 808 transition count 1048 5 rules applied. Total rules applied 266 place count 808 transition count 1048 1 transitions. 1 rules applied. Total rules applied 267 place count 808 transition count 1047 with 3 rule applications. Total rules 270 place count 805 transition count 1044 3 rules applied. Total rules applied 273 place count 805 transition count 1044 1 transitions. 1 rules applied. Total rules applied 274 place count 805 transition count 1043 with 2 rule applications. Total rules 276 place count 803 transition count 1041 2 rules applied. Total rules applied 278 place count 803 transition count 1041 with 1 rule applications. Total rules 279 place count 802 transition count 1040 1 rules applied. Total rules applied 280 place count 802 transition count 1040 with 1 rule applications. Total rules 281 place count 801 transition count 1039 1 rules applied. Total rules applied 282 place count 801 transition count 1039 with 1 rule applications. Total rules 283 place count 800 transition count 1038 1 rules applied. Total rules applied 284 place count 800 transition count 1038 with 1 rule applications. Total rules 285 place count 799 transition count 1037 1 rules applied. Total rules applied 286 place count 799 transition count 1037 with 1 rule applications. Total rules 287 place count 798 transition count 1036 1 rules applied. Total rules applied 288 place count 798 transition count 1036 with 1 rule applications. Total rules 289 place count 797 transition count 1035 1 rules applied. Total rules applied 290 place count 797 transition count 1035 with 1 rule applications. Total rules 291 place count 796 transition count 1034 1 rules applied. Total rules applied 292 place count 796 transition count 1034 1 transitions. 1 rules applied. Total rules applied 293 place count 796 transition count 1033 600 ms. Remains 796 /939 variables (removed 143) and now considering 1033/1183 (removed 150) transitions. LTL mode , in 1 iterations and 600 ms. Remains : 796/939 places, 1033/1183 transitions. Flatten gal took : 28 ms Flatten gal took : 32 ms Input system was already deterministic with 1033 transitions. SI_CTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. 939 vertex of which 74 / 939 are part of one of the 12 SCC in 1 ms 70 transitions. 1 transitions. 637 transitions Transition count delta: 637 637 rules applied. Total rules applied 638 place count 876 transition count 475 and 0 transitions. 6 transitions. 5 transitions Transition count delta: 5 648 rules applied. Total rules applied 1286 place count 239 transition count 464 0 transitions. using F-continuation condition.Transition count delta: 12 17 rules applied. Total rules applied 1303 place count 234 transition count 452 and 0 transitions. 1 transitions. 13 rules applied. Total rules applied 1316 place count 222 transition count 451 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1316 place count 222 transition count 406 places in 0 ms and 0 transitions. 90 rules applied. Total rules applied 1406 place count 177 transition count 406 with 17 rule applications. Total rules 1423 place count 160 transition count 388 17 rules applied. Total rules applied 1440 place count 160 transition count 388 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1440 place count 160 transition count 385 in 0 ms 0 transitions. 6 rules applied. Total rules applied 1446 place count 157 transition count 385 with 7 rule applications. Total rules 1453 place count 150 transition count 377 7 rules applied. Total rules applied 1460 place count 150 transition count 377 1 transitions. 1 rules applied. Total rules applied 1461 place count 150 transition count 376 with 3 rule applications. Total rules 1464 place count 147 transition count 372 3 rules applied. Total rules applied 1467 place count 147 transition count 372 1 transitions. 1 rules applied. Total rules applied 1468 place count 147 transition count 371 with 1 rule applications. Total rules 1469 place count 146 transition count 370 1 rules applied. Total rules applied 1470 place count 146 transition count 370 using F-continuation condition.Transition count delta: 20 places in 0 ms and 0 transitions. 40 rules applied. Total rules applied 1510 place count 126 transition count 350 3 transitions. 3 rules applied. Total rules applied 1513 place count 126 transition count 347 with 19 rule applications. Total rules 1532 place count 107 transition count 221 19 rules applied. Total rules applied 1551 place count 107 transition count 221 8 transitions. 8 rules applied. Total rules applied 1559 place count 107 transition count 213 with 10 rule applications. Total rules 1569 place count 97 transition count 200 10 rules applied. Total rules applied 1579 place count 97 transition count 200 with 10 rule applications. Total rules 1589 place count 87 transition count 187 10 rules applied. Total rules applied 1599 place count 87 transition count 187 4 transitions. 4 rules applied. Total rules applied 1603 place count 87 transition count 183 F-continuation condition.Transition count delta: 1 in 0 ms 0 transitions. 2 rules applied. Total rules applied 1605 place count 86 transition count 182 with 1 rule applications. Total rules 1606 place count 85 transition count 178 1 rules applied. Total rules applied 1607 place count 85 transition count 178 1 transitions. 1 rules applied. Total rules applied 1608 place count 85 transition count 177 rules discarded 4 transitions 4 rules applied. Total rules applied 1612 place count 85 transition count 173 F-continuation condition.Transition count delta: 4 in 0 ms 0 transitions. 8 rules applied. Total rules applied 1620 place count 81 transition count 169 1 transitions. 1 rules applied. Total rules applied 1621 place count 80 transition count 168 67 ms. Remains 80 /939 variables (removed 859) and now considering 168/1183 (removed 1015) transitions. SI_CTL mode , in 1 iterations and 68 ms. Remains : 80/939 places, 168/1183 transitions. Flatten gal took : 6 ms Flatten gal took : 11 ms Input system was already deterministic with 168 transitions. LTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. with 28 rule applications. Total rules 28 place count 911 transition count 1155 28 rules applied. Total rules applied 56 place count 911 transition count 1155 with 21 rule applications. Total rules 77 place count 890 transition count 1134 21 rules applied. Total rules applied 98 place count 890 transition count 1134 with 16 rule applications. Total rules 114 place count 874 transition count 1118 16 rules applied. Total rules applied 130 place count 874 transition count 1118 with 12 rule applications. Total rules 142 place count 862 transition count 1106 12 rules applied. Total rules applied 154 place count 862 transition count 1106 1 transitions. 1 rules applied. Total rules applied 155 place count 862 transition count 1105 with 11 rule applications. Total rules 166 place count 851 transition count 1094 11 rules applied. Total rules applied 177 place count 851 transition count 1094 with 10 rule applications. Total rules 187 place count 841 transition count 1084 10 rules applied. Total rules applied 197 place count 841 transition count 1084 with 10 rule applications. Total rules 207 place count 831 transition count 1074 10 rules applied. Total rules applied 217 place count 831 transition count 1074 with 9 rule applications. Total rules 226 place count 822 transition count 1065 9 rules applied. Total rules applied 235 place count 822 transition count 1065 2 transitions. 2 rules applied. Total rules applied 237 place count 822 transition count 1063 with 6 rule applications. Total rules 243 place count 816 transition count 1057 6 rules applied. Total rules applied 249 place count 816 transition count 1057 1 transitions. 1 rules applied. Total rules applied 250 place count 816 transition count 1056 with 4 rule applications. Total rules 254 place count 812 transition count 1052 4 rules applied. Total rules applied 258 place count 812 transition count 1052 with 3 rule applications. Total rules 261 place count 809 transition count 1049 3 rules applied. Total rules applied 264 place count 809 transition count 1049 1 transitions. 1 rules applied. Total rules applied 265 place count 809 transition count 1048 with 2 rule applications. Total rules 267 place count 807 transition count 1046 2 rules applied. Total rules applied 269 place count 807 transition count 1046 with 1 rule applications. Total rules 270 place count 806 transition count 1045 1 rules applied. Total rules applied 271 place count 806 transition count 1045 with 1 rule applications. Total rules 272 place count 805 transition count 1044 1 rules applied. Total rules applied 273 place count 805 transition count 1044 with 1 rule applications. Total rules 274 place count 804 transition count 1043 1 rules applied. Total rules applied 275 place count 804 transition count 1043 with 1 rule applications. Total rules 276 place count 803 transition count 1042 1 rules applied. Total rules applied 277 place count 803 transition count 1042 with 1 rule applications. Total rules 278 place count 802 transition count 1041 1 rules applied. Total rules applied 279 place count 802 transition count 1041 with 1 rule applications. Total rules 280 place count 801 transition count 1040 1 rules applied. Total rules applied 281 place count 801 transition count 1040 with 1 rule applications. Total rules 282 place count 800 transition count 1039 1 rules applied. Total rules applied 283 place count 800 transition count 1039 1 transitions. 1 rules applied. Total rules applied 284 place count 800 transition count 1038 616 ms. Remains 800 /939 variables (removed 139) and now considering 1038/1183 (removed 145) transitions. LTL mode , in 1 iterations and 617 ms. Remains : 800/939 places, 1038/1183 transitions. Flatten gal took : 29 ms Flatten gal took : 30 ms Input system was already deterministic with 1038 transitions. SI_CTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. 939 vertex of which 72 / 939 are part of one of the 12 SCC in 1 ms 67 transitions. 1 transitions. 653 transitions Transition count delta: 653 653 rules applied. Total rules applied 654 place count 878 transition count 462 and 0 transitions. 7 transitions. 5 transitions Transition count delta: 5 665 rules applied. Total rules applied 1319 place count 225 transition count 450 0 transitions. F-continuation condition.Transition count delta: 6 11 rules applied. Total rules applied 1330 place count 220 transition count 444 0 transitions. 6 rules applied. Total rules applied 1336 place count 214 transition count 444 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1336 place count 214 transition count 398 places in 1 ms and 0 transitions. 92 rules applied. Total rules applied 1428 place count 168 transition count 398 with 18 rule applications. Total rules 1446 place count 150 transition count 380 18 rules applied. Total rules applied 1464 place count 150 transition count 380 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1464 place count 150 transition count 377 in 1 ms 0 transitions. 6 rules applied. Total rules applied 1470 place count 147 transition count 377 with 8 rule applications. Total rules 1478 place count 139 transition count 343 8 rules applied. Total rules applied 1486 place count 139 transition count 343 3 transitions. 3 rules applied. Total rules applied 1489 place count 139 transition count 340 with 2 rule applications. Total rules 1491 place count 137 transition count 338 2 rules applied. Total rules applied 1493 place count 137 transition count 338 1 transitions. 1 rules applied. Total rules applied 1494 place count 137 transition count 337 with 1 rule applications. Total rules 1495 place count 136 transition count 336 1 rules applied. Total rules applied 1496 place count 136 transition count 336 using F-continuation condition.Transition count delta: 18 places in 0 ms and 0 transitions. 36 rules applied. Total rules applied 1532 place count 118 transition count 318 5 transitions. 5 rules applied. Total rules applied 1537 place count 118 transition count 313 with 18 rule applications. Total rules 1555 place count 100 transition count 214 18 rules applied. Total rules applied 1573 place count 100 transition count 214 8 transitions. 8 rules applied. Total rules applied 1581 place count 100 transition count 206 with 11 rule applications. Total rules 1592 place count 89 transition count 192 11 rules applied. Total rules applied 1603 place count 89 transition count 192 with 11 rule applications. Total rules 1614 place count 78 transition count 178 11 rules applied. Total rules applied 1625 place count 78 transition count 178 5 transitions. 5 rules applied. Total rules applied 1630 place count 78 transition count 173 F-continuation condition.Transition count delta: 1 in 0 ms 0 transitions. 2 rules applied. Total rules applied 1632 place count 77 transition count 172 with 1 rule applications. Total rules 1633 place count 76 transition count 167 1 rules applied. Total rules applied 1634 place count 76 transition count 167 1 transitions. 1 rules applied. Total rules applied 1635 place count 76 transition count 166 rules discarded 5 transitions 5 rules applied. Total rules applied 1640 place count 76 transition count 161 F-continuation condition.Transition count delta: 5 in 0 ms 0 transitions. 10 rules applied. Total rules applied 1650 place count 71 transition count 156 1 transitions. 1 rules applied. Total rules applied 1651 place count 70 transition count 155 74 ms. Remains 70 /939 variables (removed 869) and now considering 155/1183 (removed 1028) transitions. SI_CTL mode , in 1 iterations and 75 ms. Remains : 70/939 places, 155/1183 transitions. Flatten gal took : 9 ms Flatten gal took : 6 ms Input system was already deterministic with 155 transitions. LTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. with 26 rule applications. Total rules 26 place count 913 transition count 1157 26 rules applied. Total rules applied 52 place count 913 transition count 1157 with 19 rule applications. Total rules 71 place count 894 transition count 1138 19 rules applied. Total rules applied 90 place count 894 transition count 1138 with 15 rule applications. Total rules 105 place count 879 transition count 1123 15 rules applied. Total rules applied 120 place count 879 transition count 1123 with 12 rule applications. Total rules 132 place count 867 transition count 1111 12 rules applied. Total rules applied 144 place count 867 transition count 1111 1 transitions. 1 rules applied. Total rules applied 145 place count 867 transition count 1110 with 11 rule applications. Total rules 156 place count 856 transition count 1099 11 rules applied. Total rules applied 167 place count 856 transition count 1099 with 10 rule applications. Total rules 177 place count 846 transition count 1089 10 rules applied. Total rules applied 187 place count 846 transition count 1089 with 10 rule applications. Total rules 197 place count 836 transition count 1079 10 rules applied. Total rules applied 207 place count 836 transition count 1079 with 9 rule applications. Total rules 216 place count 827 transition count 1070 9 rules applied. Total rules applied 225 place count 827 transition count 1070 1 transitions. 1 rules applied. Total rules applied 226 place count 827 transition count 1069 with 6 rule applications. Total rules 232 place count 821 transition count 1063 6 rules applied. Total rules applied 238 place count 821 transition count 1063 1 transitions. 1 rules applied. Total rules applied 239 place count 821 transition count 1062 with 4 rule applications. Total rules 243 place count 817 transition count 1058 4 rules applied. Total rules applied 247 place count 817 transition count 1058 1 transitions. 1 rules applied. Total rules applied 248 place count 817 transition count 1057 with 2 rule applications. Total rules 250 place count 815 transition count 1055 2 rules applied. Total rules applied 252 place count 815 transition count 1055 1 transitions. 1 rules applied. Total rules applied 253 place count 815 transition count 1054 with 1 rule applications. Total rules 254 place count 814 transition count 1053 1 rules applied. Total rules applied 255 place count 814 transition count 1053 with 1 rule applications. Total rules 256 place count 813 transition count 1052 1 rules applied. Total rules applied 257 place count 813 transition count 1052 with 1 rule applications. Total rules 258 place count 812 transition count 1051 1 rules applied. Total rules applied 259 place count 812 transition count 1051 with 1 rule applications. Total rules 260 place count 811 transition count 1050 1 rules applied. Total rules applied 261 place count 811 transition count 1050 with 1 rule applications. Total rules 262 place count 810 transition count 1049 1 rules applied. Total rules applied 263 place count 810 transition count 1049 with 1 rule applications. Total rules 264 place count 809 transition count 1048 1 rules applied. Total rules applied 265 place count 809 transition count 1048 with 1 rule applications. Total rules 266 place count 808 transition count 1047 1 rules applied. Total rules applied 267 place count 808 transition count 1047 with 1 rule applications. Total rules 268 place count 807 transition count 1046 1 rules applied. Total rules applied 269 place count 807 transition count 1046 1 transitions. 1 rules applied. Total rules applied 270 place count 807 transition count 1045 676 ms. Remains 807 /939 variables (removed 132) and now considering 1045/1183 (removed 138) transitions. LTL mode , in 1 iterations and 676 ms. Remains : 807/939 places, 1045/1183 transitions. Flatten gal took : 28 ms Flatten gal took : 28 ms Input system was already deterministic with 1045 transitions. LTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. with 28 rule applications. Total rules 28 place count 911 transition count 1155 28 rules applied. Total rules applied 56 place count 911 transition count 1155 with 22 rule applications. Total rules 78 place count 889 transition count 1133 22 rules applied. Total rules applied 100 place count 889 transition count 1133 with 17 rule applications. Total rules 117 place count 872 transition count 1116 17 rules applied. Total rules applied 134 place count 872 transition count 1116 with 13 rule applications. Total rules 147 place count 859 transition count 1103 13 rules applied. Total rules applied 160 place count 859 transition count 1103 1 transitions. 1 rules applied. Total rules applied 161 place count 859 transition count 1102 with 12 rule applications. Total rules 173 place count 847 transition count 1090 12 rules applied. Total rules applied 185 place count 847 transition count 1090 with 11 rule applications. Total rules 196 place count 836 transition count 1079 11 rules applied. Total rules applied 207 place count 836 transition count 1079 with 11 rule applications. Total rules 218 place count 825 transition count 1068 11 rules applied. Total rules applied 229 place count 825 transition count 1068 with 10 rule applications. Total rules 239 place count 815 transition count 1058 10 rules applied. Total rules applied 249 place count 815 transition count 1058 2 transitions. 2 rules applied. Total rules applied 251 place count 815 transition count 1056 with 7 rule applications. Total rules 258 place count 808 transition count 1049 7 rules applied. Total rules applied 265 place count 808 transition count 1049 1 transitions. 1 rules applied. Total rules applied 266 place count 808 transition count 1048 with 5 rule applications. Total rules 271 place count 803 transition count 1043 5 rules applied. Total rules applied 276 place count 803 transition count 1043 1 transitions. 1 rules applied. Total rules applied 277 place count 803 transition count 1042 with 3 rule applications. Total rules 280 place count 800 transition count 1039 3 rules applied. Total rules applied 283 place count 800 transition count 1039 1 transitions. 1 rules applied. Total rules applied 284 place count 800 transition count 1038 with 1 rule applications. Total rules 285 place count 799 transition count 1037 1 rules applied. Total rules applied 286 place count 799 transition count 1037 423 ms. Remains 799 /939 variables (removed 140) and now considering 1037/1183 (removed 146) transitions. LTL mode , in 1 iterations and 423 ms. Remains : 799/939 places, 1037/1183 transitions. Flatten gal took : 28 ms Flatten gal took : 30 ms Input system was already deterministic with 1037 transitions. SI_CTL mode, iteration 0 : 939/939 places, 1183/1183 transitions. 939 vertex of which 68 / 939 are part of one of the 12 SCC in 1 ms 62 transitions. 1 transitions. 640 transitions Transition count delta: 640 640 rules applied. Total rules applied 641 place count 882 transition count 480 and 0 transitions. 6 transitions. 5 transitions Transition count delta: 5 651 rules applied. Total rules applied 1292 place count 242 transition count 469 0 transitions. using F-continuation condition.Transition count delta: 17 22 rules applied. Total rules applied 1314 place count 237 transition count 452 and 0 transitions. 1 transitions. 18 rules applied. Total rules applied 1332 place count 220 transition count 451 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1332 place count 220 transition count 407 places in 0 ms and 0 transitions. 88 rules applied. Total rules applied 1420 place count 176 transition count 407 with 17 rule applications. Total rules 1437 place count 159 transition count 390 17 rules applied. Total rules applied 1454 place count 159 transition count 390 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 1454 place count 159 transition count 388 in 0 ms 0 transitions. 4 rules applied. Total rules applied 1458 place count 157 transition count 388 with 8 rule applications. Total rules 1466 place count 149 transition count 354 8 rules applied. Total rules applied 1474 place count 149 transition count 354 3 transitions. 3 rules applied. Total rules applied 1477 place count 149 transition count 351 with 2 rule applications. Total rules 1479 place count 147 transition count 349 2 rules applied. Total rules applied 1481 place count 147 transition count 349 1 transitions. 1 rules applied. Total rules applied 1482 place count 147 transition count 348 with 1 rule applications. Total rules 1483 place count 146 transition count 347 1 rules applied. Total rules applied 1484 place count 146 transition count 347 using F-continuation condition.Transition count delta: 19 places in 0 ms and 0 transitions. 38 rules applied. Total rules applied 1522 place count 127 transition count 328 5 transitions. 5 rules applied. Total rules applied 1527 place count 127 transition count 323 with 19 rule applications. Total rules 1546 place count 108 transition count 206 19 rules applied. Total rules applied 1565 place count 108 transition count 206 9 transitions. 9 rules applied. Total rules applied 1574 place count 108 transition count 197 with 10 rule applications. Total rules 1584 place count 98 transition count 185 10 rules applied. Total rules applied 1594 place count 98 transition count 185 with 10 rule applications. Total rules 1604 place count 88 transition count 173 10 rules applied. Total rules applied 1614 place count 88 transition count 173 3 transitions. 3 rules applied. Total rules applied 1617 place count 88 transition count 170 F-continuation condition.Transition count delta: 1 in 0 ms 0 transitions. 2 rules applied. Total rules applied 1619 place count 87 transition count 169 with 1 rule applications. Total rules 1620 place count 86 transition count 163 1 rules applied. Total rules applied 1621 place count 86 transition count 163 1 transitions. 1 rules applied. Total rules applied 1622 place count 86 transition count 162 rules discarded 6 transitions 6 rules applied. Total rules applied 1628 place count 86 transition count 156 F-continuation condition.Transition count delta: 6 in 0 ms 0 transitions. 12 rules applied. Total rules applied 1640 place count 80 transition count 150 applied 2 times. 2 rules applied. Total rules applied 1642 place count 80 transition count 150 56 ms. Remains 80 /939 variables (removed 859) and now considering 150/1183 (removed 1033) transitions. SI_CTL mode , in 1 iterations and 56 ms. Remains : 80/939 places, 150/1183 transitions. Flatten gal took : 5 ms Flatten gal took : 5 ms Input system was already deterministic with 150 transitions. Flatten gal took : 30 ms Flatten gal took : 31 ms Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms. Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 939 places, 1183 transitions and 3568 arcs took 7 ms. ITS could not solve within timeout /reducer/bin//../../lola/bin/ 4 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT after 3600 seconds stools/pylibs pylibs it/itstools/pylibs: ools/pylibs: bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar /../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML ion/374/model.pnml net on/374/model.pnml ecution/374/CTLFireability.xml ewrite.k:98 ewrite.k:129 ewrite.k:322 ewrite.k:331 ewrite.k:296 ewrite.k:325 ewrite.k:328 ewrite.k:296 ewrite.k:98 ewrite.k:129 ewrite.k:394 ewrite.k:394 ewrite.k:322 ewrite.k:337 ewrite.k:314 ewrite.k:325 ewrite.k:334 ewrite.k:325 ewrite.k:334 ewrite.k:325 ewrite.k:331 ewrite.k:296 ewrite.k:296 ewrite.k:314 ewrite.k:296 ewrite.k:322 ewrite.k:331 ewrite.k:296 ewrite.k:325 ewrite.k:337 ewrite.k:296 ewrite.k:325 ewrite.k:328 ewrite.k:296 ewrite.k:325 ewrite.k:328 ewrite.k:296 ewrite.k:253 ewrite.k:325 ewrite.k:337 ewrite.k:325 ewrite.k:331 ewrite.k:296 ewrite.k:325 ewrite.k:337 ewrite.k:322 ewrite.k:331 ewrite.k:296 ewrite.k:317 ewrite.k:325 ewrite.k:337 ewrite.k:296 ewrite.k:296 ewrite.k:317 ewrite.k:296 ewrite.k:296 ewrite.k:325 ewrite.k:334 ewrite.k:325 ewrite.k:337 ewrite.k:296 ewrite.k:296 ewrite.k:253 ewrite.k:322 ewrite.k:337 ewrite.k:317 ewrite.k:325 ewrite.k:337 ewrite.k:296 ewrite.k:296 ewrite.k:317 ewrite.k:296 ewrite.k:296 ewrite.k:296 secs. secs. secs. secs. places removed secs. secs. secs. secs. secs. ewrite.k:811 ewrite.k:808 ewrite.k:811 ewrite.k:811 ewrite.k:808 ewrite.k:808 ewrite.k:811 ewrite.k:809 for 15 StigmergyCommit-PT-03b-CTLFireability-05 ewrite.k:814 ewrite.k:811 ewrite.k:815 ewrite.k:813 ewrite.k:809 EXCL) for StigmergyCommit-PT-03b-CTLFireability-05 111 228 0.000000 1 for 33 StigmergyCommit-PT-03b-CTLFireability-11 EXCL) for StigmergyCommit-PT-03b-CTLFireability-11 23 25 0.000000 1 secs. for 18 StigmergyCommit-PT-03b-CTLFireability-06 EXCL) for StigmergyCommit-PT-03b-CTLFireability-06 512 2241 0.000000 1 secs. secs. secs. for 9 StigmergyCommit-PT-03b-CTLFireability-03 ewrite.k:813 ewrite.k:808 ewrite.k:815 ewrite.k:815 ewrite.k:815 CNST) for StigmergyCommit-PT-03b-CTLFireability-03 ewrite.k:659 ewrite.k:661 ewrite.k:666 ewrite.k:668 ewrite.k:659 ewrite.k:662 ewrite.k:668 ewrite.k:679 ewrite.k:679 for 27 StigmergyCommit-PT-03b-CTLFireability-09 ewrite.k:809 ewrite.k:808 ewrite.k:811 ewrite.k:813 ewrite.k:813 ewrite.k:813 ewrite.k:814 ewrite.k:808 ewrite.k:806 ewrite.k:814 ewrite.k:814 EXCL) for StigmergyCommit-PT-03b-CTLFireability-09 1371 9197 0.000000 1 secs. ewrite.k:749 ewrite.k:787 ewrite.k:815 ewrite.k:810 ewrite.k:813 for 6 StigmergyCommit-PT-03b-CTLFireability-02 EXCL) for StigmergyCommit-PT-03b-CTLFireability-02 24 28 0.000000 1 for 0 StigmergyCommit-PT-03b-CTLFireability-00 EXCL) for StigmergyCommit-PT-03b-CTLFireability-00 18 17 0.000000 1 for 46 StigmergyCommit-PT-03b-CTLFireability-15 EXCL) for StigmergyCommit-PT-03b-CTLFireability-15 45 181 0.000000 1 for 21 StigmergyCommit-PT-03b-CTLFireability-07 EXCL) for StigmergyCommit-PT-03b-CTLFireability-07 57 183 0.000000 1 secs. ewrite.k:809 ewrite.k:811 ewrite.k:808 ewrite.k:811 ewrite.k:813 ewrite.k:812 ewrite.k:813 ewrite.k:809 ewrite.k:814 ewrite.k:811 ewrite.k:807 ewrite.k:811 ewrite.k:807 ewrite.k:809 for 24 StigmergyCommit-PT-03b-CTLFireability-08 ewrite.k:811 ewrite.k:809 ewrite.k:807 EXCL) for StigmergyCommit-PT-03b-CTLFireability-08 234 235 0.000000 1 for 3 StigmergyCommit-PT-03b-CTLFireability-01 ewrite.k:813 ewrite.k:811 ewrite.k:807 ewrite.k:813 ewrite.k:812 ewrite.k:812 ewrite.k:808 ewrite.k:810 ewrite.k:811 ewrite.k:812 ewrite.k:815 ewrite.k:812 ewrite.k:806 ewrite.k:809 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 StigmergyCommit-PT-03b-CTLFireability-01 298834 m, 59766 m/sec, 601507 t fired, . VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 StigmergyCommit-PT-03b-CTLFireability-01 516869 m, 43607 m/sec, 1316298 t fired, . in use: 4 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 StigmergyCommit-PT-03b-CTLFireability-01 750331 m, 46692 m/sec, 2018505 t fired, . in use: 5 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 StigmergyCommit-PT-03b-CTLFireability-01 994798 m, 48893 m/sec, 2704489 t fired, . in use: 7 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 StigmergyCommit-PT-03b-CTLFireability-01 1184640 m, 37968 m/sec, 3375618 t fired, . in use: 8 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 StigmergyCommit-PT-03b-CTLFireability-01 1354331 m, 33938 m/sec, 4046175 t fired, . in use: 10 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 StigmergyCommit-PT-03b-CTLFireability-01 1508387 m, 30811 m/sec, 4710456 t fired, . in use: 10 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 StigmergyCommit-PT-03b-CTLFireability-01 1675259 m, 33374 m/sec, 5369148 t fired, . in use: 12 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 StigmergyCommit-PT-03b-CTLFireability-01 1832041 m, 31356 m/sec, 6021318 t fired, . in use: 13 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 StigmergyCommit-PT-03b-CTLFireability-01 2028364 m, 39264 m/sec, 6721452 t fired, . in use: 14 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 StigmergyCommit-PT-03b-CTLFireability-01 2217620 m, 37851 m/sec, 7414797 t fired, . in use: 15 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 StigmergyCommit-PT-03b-CTLFireability-01 2405980 m, 37672 m/sec, 8103113 t fired, . in use: 16 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 StigmergyCommit-PT-03b-CTLFireability-01 2618416 m, 42487 m/sec, 8800723 t fired, . in use: 18 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 StigmergyCommit-PT-03b-CTLFireability-01 2857195 m, 47755 m/sec, 9464742 t fired, . in use: 19 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 StigmergyCommit-PT-03b-CTLFireability-01 3070783 m, 42717 m/sec, 10115177 t fired, . in use: 20 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 StigmergyCommit-PT-03b-CTLFireability-01 3252932 m, 36429 m/sec, 10779891 t fired, . in use: 21 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 StigmergyCommit-PT-03b-CTLFireability-01 3412560 m, 31925 m/sec, 11436960 t fired, . in use: 22 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 StigmergyCommit-PT-03b-CTLFireability-01 3578088 m, 33105 m/sec, 12091625 t fired, . in use: 23 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 StigmergyCommit-PT-03b-CTLFireability-01 3762628 m, 36908 m/sec, 12744491 t fired, . in use: 24 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 StigmergyCommit-PT-03b-CTLFireability-01 3994042 m, 46282 m/sec, 13435098 t fired, . in use: 25 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 StigmergyCommit-PT-03b-CTLFireability-01 4180117 m, 37215 m/sec, 14095151 t fired, . in use: 26 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 StigmergyCommit-PT-03b-CTLFireability-01 4349358 m, 33848 m/sec, 14763962 t fired, . in use: 27 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 StigmergyCommit-PT-03b-CTLFireability-01 4553685 m, 40865 m/sec, 15454642 t fired, . in use: 28 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 StigmergyCommit-PT-03b-CTLFireability-01 4780079 m, 45278 m/sec, 16143284 t fired, . in use: 29 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 StigmergyCommit-PT-03b-CTLFireability-01 5005750 m, 45134 m/sec, 16864065 t fired, . in use: 31 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 StigmergyCommit-PT-03b-CTLFireability-01 5215222 m, 41894 m/sec, 17575575 t fired, . in use: 32 EXCL) for StigmergyCommit-PT-03b-CTLFireability-01 (memory limit exceeded) VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 for 39 StigmergyCommit-PT-03b-CTLFireability-13 EXCL) for StigmergyCommit-PT-03b-CTLFireability-13 1 0.000000 1 for 39 StigmergyCommit-PT-03b-CTLFireability-13 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 StigmergyCommit-PT-03b-CTLFireability-13 323272 m, 64654 m/sec, 696001 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 StigmergyCommit-PT-03b-CTLFireability-13 639643 m, 63274 m/sec, 1392910 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 StigmergyCommit-PT-03b-CTLFireability-13 939203 m, 59912 m/sec, 2031824 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 StigmergyCommit-PT-03b-CTLFireability-13 1216710 m, 55501 m/sec, 2664625 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 StigmergyCommit-PT-03b-CTLFireability-13 1469777 m, 50613 m/sec, 3243058 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 StigmergyCommit-PT-03b-CTLFireability-13 1701859 m, 46416 m/sec, 3883376 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 StigmergyCommit-PT-03b-CTLFireability-13 1908603 m, 41348 m/sec, 4507447 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 StigmergyCommit-PT-03b-CTLFireability-13 2225895 m, 63458 m/sec, 5148370 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 StigmergyCommit-PT-03b-CTLFireability-13 2432714 m, 41363 m/sec, 5797983 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 StigmergyCommit-PT-03b-CTLFireability-13 2644463 m, 42349 m/sec, 6436946 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 StigmergyCommit-PT-03b-CTLFireability-13 2891998 m, 49507 m/sec, 7105421 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 StigmergyCommit-PT-03b-CTLFireability-13 3134477 m, 48495 m/sec, 7769315 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 StigmergyCommit-PT-03b-CTLFireability-13 3379462 m, 48997 m/sec, 8433985 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 StigmergyCommit-PT-03b-CTLFireability-13 3694682 m, 63044 m/sec, 9067723 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 StigmergyCommit-PT-03b-CTLFireability-13 3990131 m, 59089 m/sec, 9669532 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 StigmergyCommit-PT-03b-CTLFireability-13 4222933 m, 46560 m/sec, 10301120 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 StigmergyCommit-PT-03b-CTLFireability-13 4423996 m, 40212 m/sec, 10936119 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 StigmergyCommit-PT-03b-CTLFireability-13 4642166 m, 43634 m/sec, 11556873 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 StigmergyCommit-PT-03b-CTLFireability-13 4956253 m, 62817 m/sec, 12204593 t fired, . in use: 32 EXCL) for StigmergyCommit-PT-03b-CTLFireability-13 (memory limit exceeded) VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 for 36 StigmergyCommit-PT-03b-CTLFireability-12 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 StigmergyCommit-PT-03b-CTLFireability-12 320809 m, 64161 m/sec, 703190 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 StigmergyCommit-PT-03b-CTLFireability-12 672419 m, 70322 m/sec, 1374573 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 StigmergyCommit-PT-03b-CTLFireability-12 964113 m, 58338 m/sec, 2037598 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 StigmergyCommit-PT-03b-CTLFireability-12 1183290 m, 43835 m/sec, 2697846 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 StigmergyCommit-PT-03b-CTLFireability-12 1394539 m, 42249 m/sec, 3356052 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 StigmergyCommit-PT-03b-CTLFireability-12 1597333 m, 40558 m/sec, 4003942 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 StigmergyCommit-PT-03b-CTLFireability-12 1859840 m, 52501 m/sec, 4688438 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 StigmergyCommit-PT-03b-CTLFireability-12 2114314 m, 50894 m/sec, 5364248 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 StigmergyCommit-PT-03b-CTLFireability-12 2402100 m, 57557 m/sec, 6043407 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 StigmergyCommit-PT-03b-CTLFireability-12 2759168 m, 71413 m/sec, 6673645 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 StigmergyCommit-PT-03b-CTLFireability-12 3011628 m, 50492 m/sec, 7319760 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 StigmergyCommit-PT-03b-CTLFireability-12 3221778 m, 42030 m/sec, 7965710 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 StigmergyCommit-PT-03b-CTLFireability-12 3436426 m, 42929 m/sec, 8609580 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 StigmergyCommit-PT-03b-CTLFireability-12 3756482 m, 64011 m/sec, 9260058 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 StigmergyCommit-PT-03b-CTLFireability-12 4003911 m, 49485 m/sec, 9909420 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 StigmergyCommit-PT-03b-CTLFireability-12 4258762 m, 50970 m/sec, 10576758 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 StigmergyCommit-PT-03b-CTLFireability-12 4575990 m, 63445 m/sec, 11248072 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 StigmergyCommit-PT-03b-CTLFireability-12 4886030 m, 62008 m/sec, 11954528 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 StigmergyCommit-PT-03b-CTLFireability-12 5121195 m, 47033 m/sec, 12635057 t fired, . in use: 32 EXCL) for StigmergyCommit-PT-03b-CTLFireability-12 (memory limit exceeded) VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 for 30 StigmergyCommit-PT-03b-CTLFireability-10 EXCL) for StigmergyCommit-PT-03b-CTLFireability-10 232 233 0.000000 1 for 12 StigmergyCommit-PT-03b-CTLFireability-04 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 StigmergyCommit-PT-03b-CTLFireability-04 318214 m, 63642 m/sec, 697918 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 StigmergyCommit-PT-03b-CTLFireability-04 666376 m, 69632 m/sec, 1363551 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 StigmergyCommit-PT-03b-CTLFireability-04 958657 m, 58456 m/sec, 2020332 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 StigmergyCommit-PT-03b-CTLFireability-04 1177611 m, 43790 m/sec, 2676755 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 StigmergyCommit-PT-03b-CTLFireability-04 1386725 m, 41822 m/sec, 3330226 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 StigmergyCommit-PT-03b-CTLFireability-04 1582513 m, 39157 m/sec, 3971950 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 StigmergyCommit-PT-03b-CTLFireability-04 1846517 m, 52800 m/sec, 4648279 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 StigmergyCommit-PT-03b-CTLFireability-04 2097989 m, 50294 m/sec, 5317282 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 StigmergyCommit-PT-03b-CTLFireability-04 2378836 m, 56169 m/sec, 5989310 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 StigmergyCommit-PT-03b-CTLFireability-04 2726533 m, 69539 m/sec, 6617457 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 StigmergyCommit-PT-03b-CTLFireability-04 2987303 m, 52154 m/sec, 7248426 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 StigmergyCommit-PT-03b-CTLFireability-04 3197368 m, 42013 m/sec, 7887628 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 StigmergyCommit-PT-03b-CTLFireability-04 3410208 m, 42568 m/sec, 8526432 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 StigmergyCommit-PT-03b-CTLFireability-04 3707306 m, 59419 m/sec, 9168656 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 StigmergyCommit-PT-03b-CTLFireability-04 3973561 m, 53251 m/sec, 9808192 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 StigmergyCommit-PT-03b-CTLFireability-04 4212350 m, 47757 m/sec, 10468091 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 StigmergyCommit-PT-03b-CTLFireability-04 4515948 m, 60719 m/sec, 11138277 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 StigmergyCommit-PT-03b-CTLFireability-04 4835854 m, 63981 m/sec, 11832327 t fired, . in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 StigmergyCommit-PT-03b-CTLFireability-04 5089798 m, 50788 m/sec, 12518401 t fired, . in use: 32 EXCL) for StigmergyCommit-PT-03b-CTLFireability-04 (memory limit exceeded) VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY F false state space / EG true LTL model checker true preprocessing CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker truncated ====== if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyCommit-PT-03b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is StigmergyCommit-PT-03b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647300418"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/StigmergyCommit-PT-03b.tgz
mv StigmergyCommit-PT-03b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;