Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647200282.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmartHome-PT-17, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647200282
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 560K
-rw-r--r-- 1 mcc users 6.3K Feb 26 05:38 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K Feb 26 05:38 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 26 05:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 26 05:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:10 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:10 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:10 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:10 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.5K Feb 26 05:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 88K Feb 26 05:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Feb 26 05:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 85K Feb 26 05:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 139K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmartHome-PT-17-CTLFireability-00
FORMULA_NAME SmartHome-PT-17-CTLFireability-01
FORMULA_NAME SmartHome-PT-17-CTLFireability-02
FORMULA_NAME SmartHome-PT-17-CTLFireability-03
FORMULA_NAME SmartHome-PT-17-CTLFireability-04
FORMULA_NAME SmartHome-PT-17-CTLFireability-05
FORMULA_NAME SmartHome-PT-17-CTLFireability-06
FORMULA_NAME SmartHome-PT-17-CTLFireability-07
FORMULA_NAME SmartHome-PT-17-CTLFireability-08
FORMULA_NAME SmartHome-PT-17-CTLFireability-09
FORMULA_NAME SmartHome-PT-17-CTLFireability-10
FORMULA_NAME SmartHome-PT-17-CTLFireability-11
FORMULA_NAME SmartHome-PT-17-CTLFireability-12
FORMULA_NAME SmartHome-PT-17-CTLFireability-13
FORMULA_NAME SmartHome-PT-17-CTLFireability-14
FORMULA_NAME SmartHome-PT-17-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679215753031

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmartHome-PT-17
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 08:49:16] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 08:49:16] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 08:49:17] [INFO ] Load time of PNML (sax parser for PT used): 181 ms
[2023-03-19 08:49:17] [INFO ] Transformed 571 places.
[2023-03-19 08:49:17] [INFO ] Transformed 617 transitions.
[2023-03-19 08:49:17] [INFO ] Found NUPN structural information;
[2023-03-19 08:49:17] [INFO ] Parsed PT model containing 571 places and 617 transitions and 1410 arcs in 401 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 19 ms.
Deduced a syphon composed of 176 places in 13 ms
Reduce places removed 176 places and 150 transitions.
FORMULA SmartHome-PT-17-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 53 out of 395 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 395/395 places, 467/467 transitions.
Reduce places removed 15 places and 0 transitions.
Iterating post reduction 0 with 15 rules applied. Total rules applied 15 place count 380 transition count 467
Discarding 94 places :
Symmetric choice reduction at 1 with 94 rule applications. Total rules 109 place count 286 transition count 373
Iterating global reduction 1 with 94 rules applied. Total rules applied 203 place count 286 transition count 373
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 1 with 8 rules applied. Total rules applied 211 place count 286 transition count 365
Discarding 15 places :
Symmetric choice reduction at 2 with 15 rule applications. Total rules 226 place count 271 transition count 350
Iterating global reduction 2 with 15 rules applied. Total rules applied 241 place count 271 transition count 350
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 252 place count 260 transition count 339
Iterating global reduction 2 with 11 rules applied. Total rules applied 263 place count 260 transition count 339
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 268 place count 255 transition count 334
Iterating global reduction 2 with 5 rules applied. Total rules applied 273 place count 255 transition count 334
Applied a total of 273 rules in 184 ms. Remains 255 /395 variables (removed 140) and now considering 334/467 (removed 133) transitions.
// Phase 1: matrix 334 rows 255 cols
[2023-03-19 08:49:17] [INFO ] Computed 3 place invariants in 39 ms
[2023-03-19 08:49:18] [INFO ] Implicit Places using invariants in 434 ms returned []
[2023-03-19 08:49:18] [INFO ] Invariant cache hit.
[2023-03-19 08:49:18] [INFO ] Implicit Places using invariants and state equation in 433 ms returned []
Implicit Place search using SMT with State Equation took 957 ms to find 0 implicit places.
[2023-03-19 08:49:18] [INFO ] Invariant cache hit.
[2023-03-19 08:49:18] [INFO ] Dead Transitions using invariants and state equation in 400 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 255/395 places, 334/467 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1546 ms. Remains : 255/395 places, 334/467 transitions.
Support contains 53 out of 255 places after structural reductions.
[2023-03-19 08:49:19] [INFO ] Flatten gal took : 107 ms
[2023-03-19 08:49:19] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA SmartHome-PT-17-CTLFireability-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 08:49:19] [INFO ] Flatten gal took : 44 ms
[2023-03-19 08:49:19] [INFO ] Input system was already deterministic with 334 transitions.
Support contains 52 out of 255 places (down from 53) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 36 resets, run finished after 769 ms. (steps per millisecond=13 ) properties (out of 44) seen :39
Incomplete Best-First random walk after 10001 steps, including 4 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 3 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 3 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
[2023-03-19 08:49:20] [INFO ] Invariant cache hit.
[2023-03-19 08:49:20] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 08:49:20] [INFO ] [Real]Absence check using 2 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 08:49:21] [INFO ] After 464ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-19 08:49:21] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 08:49:21] [INFO ] [Nat]Absence check using 2 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 08:49:21] [INFO ] After 288ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :5
[2023-03-19 08:49:21] [INFO ] After 474ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :5
Attempting to minimize the solution found.
Minimization took 118 ms.
[2023-03-19 08:49:21] [INFO ] After 816ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :5
Fused 5 Parikh solutions to 4 different solutions.
Parikh walk visited 1 properties in 38 ms.
Support contains 6 out of 255 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 255/255 places, 334/334 transitions.
Graph (trivial) has 262 edges and 255 vertex of which 131 / 255 are part of one of the 11 SCC in 6 ms
Free SCC test removed 120 places
Drop transitions removed 177 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 179 transitions.
Graph (complete) has 205 edges and 135 vertex of which 127 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.2 ms
Discarding 8 places :
Also discarding 5 output transitions
Drop transitions removed 5 transitions
Drop transitions removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Drop transitions removed 46 transitions
Trivial Post-agglo rules discarded 46 transitions
Performed 46 trivial Post agglomeration. Transition count delta: 46
Iterating post reduction 0 with 56 rules applied. Total rules applied 58 place count 127 transition count 94
Reduce places removed 46 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 57 rules applied. Total rules applied 115 place count 81 transition count 83
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 2 with 5 rules applied. Total rules applied 120 place count 76 transition count 83
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 9 Pre rules applied. Total rules applied 120 place count 76 transition count 74
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 3 with 18 rules applied. Total rules applied 138 place count 67 transition count 74
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 142 place count 63 transition count 70
Iterating global reduction 3 with 4 rules applied. Total rules applied 146 place count 63 transition count 70
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 148 place count 63 transition count 68
Performed 31 Post agglomeration using F-continuation condition with reduction of 4 identical transitions.
Deduced a syphon composed of 31 places in 0 ms
Reduce places removed 31 places and 0 transitions.
Iterating global reduction 4 with 62 rules applied. Total rules applied 210 place count 32 transition count 33
Drop transitions removed 8 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 9 transitions.
Graph (complete) has 51 edges and 32 vertex of which 25 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.0 ms
Discarding 7 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 10 rules applied. Total rules applied 220 place count 25 transition count 24
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 223 place count 25 transition count 21
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 6 with 1 rules applied. Total rules applied 224 place count 24 transition count 20
Reduce places removed 5 places and 0 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 6 with 7 rules applied. Total rules applied 231 place count 19 transition count 18
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 7 with 2 rules applied. Total rules applied 233 place count 17 transition count 18
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 8 with 1 Pre rules applied. Total rules applied 233 place count 17 transition count 17
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 235 place count 16 transition count 17
Free-agglomeration rule applied 1 times.
Iterating global reduction 8 with 1 rules applied. Total rules applied 236 place count 16 transition count 16
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 237 place count 15 transition count 16
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 9 with 1 rules applied. Total rules applied 238 place count 14 transition count 15
Applied a total of 238 rules in 63 ms. Remains 14 /255 variables (removed 241) and now considering 15/334 (removed 319) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 63 ms. Remains : 14/255 places, 15/334 transitions.
Finished random walk after 3353 steps, including 1 resets, run visited all 4 properties in 12 ms. (steps per millisecond=279 )
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 33 ms
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 37 ms
[2023-03-19 08:49:22] [INFO ] Input system was already deterministic with 334 transitions.
Computed a total of 51 stabilizing places and 50 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 232 transition count 311
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 232 transition count 311
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 47 place count 232 transition count 310
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 57 place count 222 transition count 300
Iterating global reduction 1 with 10 rules applied. Total rules applied 67 place count 222 transition count 300
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 68 place count 222 transition count 299
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 75 place count 215 transition count 292
Iterating global reduction 2 with 7 rules applied. Total rules applied 82 place count 215 transition count 292
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 83 place count 215 transition count 291
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 86 place count 212 transition count 288
Iterating global reduction 3 with 3 rules applied. Total rules applied 89 place count 212 transition count 288
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 90 place count 211 transition count 287
Iterating global reduction 3 with 1 rules applied. Total rules applied 91 place count 211 transition count 287
Applied a total of 91 rules in 57 ms. Remains 211 /255 variables (removed 44) and now considering 287/334 (removed 47) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 57 ms. Remains : 211/255 places, 287/334 transitions.
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 26 ms
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 27 ms
[2023-03-19 08:49:22] [INFO ] Input system was already deterministic with 287 transitions.
Starting structural reductions in LTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 231 transition count 310
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 231 transition count 310
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 50 place count 231 transition count 308
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 59 place count 222 transition count 299
Iterating global reduction 1 with 9 rules applied. Total rules applied 68 place count 222 transition count 299
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 69 place count 222 transition count 298
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 75 place count 216 transition count 292
Iterating global reduction 2 with 6 rules applied. Total rules applied 81 place count 216 transition count 292
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 82 place count 216 transition count 291
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 84 place count 214 transition count 289
Iterating global reduction 3 with 2 rules applied. Total rules applied 86 place count 214 transition count 289
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 87 place count 213 transition count 288
Iterating global reduction 3 with 1 rules applied. Total rules applied 88 place count 213 transition count 288
Applied a total of 88 rules in 62 ms. Remains 213 /255 variables (removed 42) and now considering 288/334 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 62 ms. Remains : 213/255 places, 288/334 transitions.
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 26 ms
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 24 ms
[2023-03-19 08:49:22] [INFO ] Input system was already deterministic with 288 transitions.
Starting structural reductions in LTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 232 transition count 311
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 232 transition count 311
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 48 place count 232 transition count 309
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 58 place count 222 transition count 299
Iterating global reduction 1 with 10 rules applied. Total rules applied 68 place count 222 transition count 299
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 69 place count 222 transition count 298
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 76 place count 215 transition count 291
Iterating global reduction 2 with 7 rules applied. Total rules applied 83 place count 215 transition count 291
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 84 place count 215 transition count 290
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 87 place count 212 transition count 287
Iterating global reduction 3 with 3 rules applied. Total rules applied 90 place count 212 transition count 287
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 91 place count 211 transition count 286
Iterating global reduction 3 with 1 rules applied. Total rules applied 92 place count 211 transition count 286
Applied a total of 92 rules in 50 ms. Remains 211 /255 variables (removed 44) and now considering 286/334 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 51 ms. Remains : 211/255 places, 286/334 transitions.
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 20 ms
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 21 ms
[2023-03-19 08:49:22] [INFO ] Input system was already deterministic with 286 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Graph (trivial) has 269 edges and 255 vertex of which 140 / 255 are part of one of the 11 SCC in 1 ms
Free SCC test removed 129 places
Ensure Unique test removed 168 transitions
Reduce isomorphic transitions removed 168 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 43 transitions
Trivial Post-agglo rules discarded 43 transitions
Performed 43 trivial Post agglomeration. Transition count delta: 43
Iterating post reduction 0 with 43 rules applied. Total rules applied 44 place count 125 transition count 122
Reduce places removed 43 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 1 with 51 rules applied. Total rules applied 95 place count 82 transition count 114
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 98 place count 79 transition count 114
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 6 Pre rules applied. Total rules applied 98 place count 79 transition count 108
Deduced a syphon composed of 6 places in 1 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 3 with 12 rules applied. Total rules applied 110 place count 73 transition count 108
Discarding 7 places :
Symmetric choice reduction at 3 with 7 rule applications. Total rules 117 place count 66 transition count 99
Iterating global reduction 3 with 7 rules applied. Total rules applied 124 place count 66 transition count 99
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 126 place count 66 transition count 97
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 127 place count 65 transition count 96
Iterating global reduction 4 with 1 rules applied. Total rules applied 128 place count 65 transition count 96
Performed 32 Post agglomeration using F-continuation condition with reduction of 1 identical transitions.
Deduced a syphon composed of 32 places in 0 ms
Reduce places removed 32 places and 0 transitions.
Iterating global reduction 4 with 64 rules applied. Total rules applied 192 place count 33 transition count 63
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 4 with 5 rules applied. Total rules applied 197 place count 33 transition count 58
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 199 place count 32 transition count 57
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 200 place count 31 transition count 56
Iterating global reduction 6 with 1 rules applied. Total rules applied 201 place count 31 transition count 56
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 6 with 6 rules applied. Total rules applied 207 place count 28 transition count 53
Discarding 2 places :
Symmetric choice reduction at 6 with 2 rule applications. Total rules 209 place count 26 transition count 45
Iterating global reduction 6 with 2 rules applied. Total rules applied 211 place count 26 transition count 45
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 6 with 13 rules applied. Total rules applied 224 place count 26 transition count 32
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 6 with 2 rules applied. Total rules applied 226 place count 24 transition count 32
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 7 with 1 Pre rules applied. Total rules applied 226 place count 24 transition count 31
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 7 with 2 rules applied. Total rules applied 228 place count 23 transition count 31
Discarding 1 places :
Symmetric choice reduction at 7 with 1 rule applications. Total rules 229 place count 22 transition count 29
Iterating global reduction 7 with 1 rules applied. Total rules applied 230 place count 22 transition count 29
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 7 with 1 rules applied. Total rules applied 231 place count 21 transition count 28
Applied a total of 231 rules in 60 ms. Remains 21 /255 variables (removed 234) and now considering 28/334 (removed 306) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 61 ms. Remains : 21/255 places, 28/334 transitions.
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 3 ms
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 3 ms
[2023-03-19 08:49:22] [INFO ] Input system was already deterministic with 28 transitions.
Finished random walk after 6 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=3 )
FORMULA SmartHome-PT-17-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 232 transition count 311
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 232 transition count 311
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 48 place count 232 transition count 309
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 56 place count 224 transition count 301
Iterating global reduction 1 with 8 rules applied. Total rules applied 64 place count 224 transition count 301
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 69 place count 219 transition count 296
Iterating global reduction 1 with 5 rules applied. Total rules applied 74 place count 219 transition count 296
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 75 place count 219 transition count 295
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 78 place count 216 transition count 292
Iterating global reduction 2 with 3 rules applied. Total rules applied 81 place count 216 transition count 292
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 82 place count 215 transition count 291
Iterating global reduction 2 with 1 rules applied. Total rules applied 83 place count 215 transition count 291
Applied a total of 83 rules in 56 ms. Remains 215 /255 variables (removed 40) and now considering 291/334 (removed 43) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 56 ms. Remains : 215/255 places, 291/334 transitions.
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 26 ms
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 23 ms
[2023-03-19 08:49:22] [INFO ] Input system was already deterministic with 291 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Graph (trivial) has 270 edges and 255 vertex of which 149 / 255 are part of one of the 12 SCC in 1 ms
Free SCC test removed 137 places
Ensure Unique test removed 178 transitions
Reduce isomorphic transitions removed 178 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 39 transitions
Trivial Post-agglo rules discarded 39 transitions
Performed 39 trivial Post agglomeration. Transition count delta: 39
Iterating post reduction 0 with 39 rules applied. Total rules applied 40 place count 117 transition count 116
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 1 with 47 rules applied. Total rules applied 87 place count 78 transition count 108
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 90 place count 75 transition count 108
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 6 Pre rules applied. Total rules applied 90 place count 75 transition count 102
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 3 with 12 rules applied. Total rules applied 102 place count 69 transition count 102
Discarding 7 places :
Symmetric choice reduction at 3 with 7 rule applications. Total rules 109 place count 62 transition count 93
Iterating global reduction 3 with 7 rules applied. Total rules applied 116 place count 62 transition count 93
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 118 place count 62 transition count 91
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 119 place count 61 transition count 90
Iterating global reduction 4 with 1 rules applied. Total rules applied 120 place count 61 transition count 90
Performed 29 Post agglomeration using F-continuation condition.Transition count delta: 29
Deduced a syphon composed of 29 places in 0 ms
Reduce places removed 29 places and 0 transitions.
Iterating global reduction 4 with 58 rules applied. Total rules applied 178 place count 32 transition count 61
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 181 place count 32 transition count 58
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 182 place count 31 transition count 57
Iterating global reduction 5 with 1 rules applied. Total rules applied 183 place count 31 transition count 57
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 5 with 6 rules applied. Total rules applied 189 place count 28 transition count 54
Discarding 2 places :
Symmetric choice reduction at 5 with 2 rule applications. Total rules 191 place count 26 transition count 46
Iterating global reduction 5 with 2 rules applied. Total rules applied 193 place count 26 transition count 46
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 5 with 13 rules applied. Total rules applied 206 place count 26 transition count 33
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 208 place count 24 transition count 33
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 1 Pre rules applied. Total rules applied 208 place count 24 transition count 32
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 210 place count 23 transition count 32
Discarding 2 places :
Symmetric choice reduction at 6 with 2 rule applications. Total rules 212 place count 21 transition count 28
Iterating global reduction 6 with 2 rules applied. Total rules applied 214 place count 21 transition count 28
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 6 with 1 rules applied. Total rules applied 215 place count 20 transition count 27
Applied a total of 215 rules in 28 ms. Remains 20 /255 variables (removed 235) and now considering 27/334 (removed 307) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 20/255 places, 27/334 transitions.
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 1 ms
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 1 ms
[2023-03-19 08:49:22] [INFO ] Input system was already deterministic with 27 transitions.
Finished random walk after 19 steps, including 1 resets, run visited all 1 properties in 1 ms. (steps per millisecond=19 )
FORMULA SmartHome-PT-17-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Discarding 21 places :
Symmetric choice reduction at 0 with 21 rule applications. Total rules 21 place count 234 transition count 313
Iterating global reduction 0 with 21 rules applied. Total rules applied 42 place count 234 transition count 313
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 44 place count 234 transition count 311
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 52 place count 226 transition count 303
Iterating global reduction 1 with 8 rules applied. Total rules applied 60 place count 226 transition count 303
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 61 place count 226 transition count 302
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 67 place count 220 transition count 296
Iterating global reduction 2 with 6 rules applied. Total rules applied 73 place count 220 transition count 296
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 74 place count 220 transition count 295
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 76 place count 218 transition count 293
Iterating global reduction 3 with 2 rules applied. Total rules applied 78 place count 218 transition count 293
Applied a total of 78 rules in 24 ms. Remains 218 /255 variables (removed 37) and now considering 293/334 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 24 ms. Remains : 218/255 places, 293/334 transitions.
[2023-03-19 08:49:22] [INFO ] Flatten gal took : 13 ms
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 14 ms
[2023-03-19 08:49:23] [INFO ] Input system was already deterministic with 293 transitions.
Starting structural reductions in LTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 238 transition count 317
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 238 transition count 317
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 36 place count 238 transition count 315
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 43 place count 231 transition count 308
Iterating global reduction 1 with 7 rules applied. Total rules applied 50 place count 231 transition count 308
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 51 place count 231 transition count 307
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 56 place count 226 transition count 302
Iterating global reduction 2 with 5 rules applied. Total rules applied 61 place count 226 transition count 302
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 62 place count 226 transition count 301
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 63 place count 225 transition count 300
Iterating global reduction 3 with 1 rules applied. Total rules applied 64 place count 225 transition count 300
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 65 place count 224 transition count 299
Iterating global reduction 3 with 1 rules applied. Total rules applied 66 place count 224 transition count 299
Applied a total of 66 rules in 26 ms. Remains 224 /255 variables (removed 31) and now considering 299/334 (removed 35) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 224/255 places, 299/334 transitions.
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 12 ms
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 12 ms
[2023-03-19 08:49:23] [INFO ] Input system was already deterministic with 299 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Graph (trivial) has 264 edges and 255 vertex of which 148 / 255 are part of one of the 12 SCC in 1 ms
Free SCC test removed 136 places
Ensure Unique test removed 177 transitions
Reduce isomorphic transitions removed 177 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 35 transitions
Trivial Post-agglo rules discarded 35 transitions
Performed 35 trivial Post agglomeration. Transition count delta: 35
Iterating post reduction 0 with 35 rules applied. Total rules applied 36 place count 118 transition count 121
Reduce places removed 35 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 41 rules applied. Total rules applied 77 place count 83 transition count 115
Reduce places removed 2 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 4 rules applied. Total rules applied 81 place count 81 transition count 113
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 84 place count 79 transition count 112
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 7 Pre rules applied. Total rules applied 84 place count 79 transition count 105
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 4 with 14 rules applied. Total rules applied 98 place count 72 transition count 105
Discarding 7 places :
Symmetric choice reduction at 4 with 7 rule applications. Total rules 105 place count 65 transition count 96
Iterating global reduction 4 with 7 rules applied. Total rules applied 112 place count 65 transition count 96
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 114 place count 65 transition count 94
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 115 place count 64 transition count 93
Iterating global reduction 5 with 1 rules applied. Total rules applied 116 place count 64 transition count 93
Performed 28 Post agglomeration using F-continuation condition.Transition count delta: 28
Deduced a syphon composed of 28 places in 0 ms
Reduce places removed 28 places and 0 transitions.
Iterating global reduction 5 with 56 rules applied. Total rules applied 172 place count 36 transition count 65
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 175 place count 36 transition count 62
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 176 place count 35 transition count 61
Iterating global reduction 6 with 1 rules applied. Total rules applied 177 place count 35 transition count 61
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 6 with 4 rules applied. Total rules applied 181 place count 33 transition count 59
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 182 place count 32 transition count 55
Iterating global reduction 6 with 1 rules applied. Total rules applied 183 place count 32 transition count 55
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 6 with 13 rules applied. Total rules applied 196 place count 32 transition count 42
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 197 place count 31 transition count 42
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 7 with 1 Pre rules applied. Total rules applied 197 place count 31 transition count 41
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 7 with 2 rules applied. Total rules applied 199 place count 30 transition count 41
Discarding 2 places :
Symmetric choice reduction at 7 with 2 rule applications. Total rules 201 place count 28 transition count 37
Iterating global reduction 7 with 2 rules applied. Total rules applied 203 place count 28 transition count 37
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 7 with 1 rules applied. Total rules applied 204 place count 27 transition count 36
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 205 place count 26 transition count 36
Applied a total of 205 rules in 27 ms. Remains 26 /255 variables (removed 229) and now considering 36/334 (removed 298) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 26/255 places, 36/334 transitions.
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 1 ms
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 2 ms
[2023-03-19 08:49:23] [INFO ] Input system was already deterministic with 36 transitions.
Starting structural reductions in LTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 231 transition count 310
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 231 transition count 310
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 50 place count 231 transition count 308
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 60 place count 221 transition count 298
Iterating global reduction 1 with 10 rules applied. Total rules applied 70 place count 221 transition count 298
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 71 place count 221 transition count 297
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 78 place count 214 transition count 290
Iterating global reduction 2 with 7 rules applied. Total rules applied 85 place count 214 transition count 290
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 86 place count 214 transition count 289
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 89 place count 211 transition count 286
Iterating global reduction 3 with 3 rules applied. Total rules applied 92 place count 211 transition count 286
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 93 place count 210 transition count 285
Iterating global reduction 3 with 1 rules applied. Total rules applied 94 place count 210 transition count 285
Applied a total of 94 rules in 27 ms. Remains 210 /255 variables (removed 45) and now considering 285/334 (removed 49) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 210/255 places, 285/334 transitions.
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 10 ms
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 10 ms
[2023-03-19 08:49:23] [INFO ] Input system was already deterministic with 285 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Graph (trivial) has 271 edges and 255 vertex of which 150 / 255 are part of one of the 12 SCC in 1 ms
Free SCC test removed 138 places
Ensure Unique test removed 180 transitions
Reduce isomorphic transitions removed 180 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 39 transitions
Trivial Post-agglo rules discarded 39 transitions
Performed 39 trivial Post agglomeration. Transition count delta: 39
Iterating post reduction 0 with 39 rules applied. Total rules applied 40 place count 116 transition count 114
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 1 with 47 rules applied. Total rules applied 87 place count 77 transition count 106
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 90 place count 74 transition count 106
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 5 Pre rules applied. Total rules applied 90 place count 74 transition count 101
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 10 rules applied. Total rules applied 100 place count 69 transition count 101
Discarding 7 places :
Symmetric choice reduction at 3 with 7 rule applications. Total rules 107 place count 62 transition count 92
Iterating global reduction 3 with 7 rules applied. Total rules applied 114 place count 62 transition count 92
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 116 place count 62 transition count 90
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 117 place count 61 transition count 89
Iterating global reduction 4 with 1 rules applied. Total rules applied 118 place count 61 transition count 89
Performed 29 Post agglomeration using F-continuation condition.Transition count delta: 29
Deduced a syphon composed of 29 places in 0 ms
Reduce places removed 29 places and 0 transitions.
Iterating global reduction 4 with 58 rules applied. Total rules applied 176 place count 32 transition count 60
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 179 place count 32 transition count 57
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 180 place count 31 transition count 56
Iterating global reduction 5 with 1 rules applied. Total rules applied 181 place count 31 transition count 56
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 5 with 6 rules applied. Total rules applied 187 place count 28 transition count 53
Discarding 2 places :
Symmetric choice reduction at 5 with 2 rule applications. Total rules 189 place count 26 transition count 45
Iterating global reduction 5 with 2 rules applied. Total rules applied 191 place count 26 transition count 45
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 5 with 13 rules applied. Total rules applied 204 place count 26 transition count 32
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 206 place count 24 transition count 32
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 1 Pre rules applied. Total rules applied 206 place count 24 transition count 31
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 208 place count 23 transition count 31
Discarding 2 places :
Symmetric choice reduction at 6 with 2 rule applications. Total rules 210 place count 21 transition count 27
Iterating global reduction 6 with 2 rules applied. Total rules applied 212 place count 21 transition count 27
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 6 with 1 rules applied. Total rules applied 213 place count 20 transition count 26
Applied a total of 213 rules in 19 ms. Remains 20 /255 variables (removed 235) and now considering 26/334 (removed 308) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 20/255 places, 26/334 transitions.
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 1 ms
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 1 ms
[2023-03-19 08:49:23] [INFO ] Input system was already deterministic with 26 transitions.
Finished random walk after 744 steps, including 50 resets, run visited all 1 properties in 4 ms. (steps per millisecond=186 )
FORMULA SmartHome-PT-17-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 232 transition count 311
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 232 transition count 311
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 48 place count 232 transition count 309
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 57 place count 223 transition count 300
Iterating global reduction 1 with 9 rules applied. Total rules applied 66 place count 223 transition count 300
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 67 place count 223 transition count 299
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 74 place count 216 transition count 292
Iterating global reduction 2 with 7 rules applied. Total rules applied 81 place count 216 transition count 292
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 82 place count 216 transition count 291
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 85 place count 213 transition count 288
Iterating global reduction 3 with 3 rules applied. Total rules applied 88 place count 213 transition count 288
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 89 place count 212 transition count 287
Iterating global reduction 3 with 1 rules applied. Total rules applied 90 place count 212 transition count 287
Applied a total of 90 rules in 26 ms. Remains 212 /255 variables (removed 43) and now considering 287/334 (removed 47) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 212/255 places, 287/334 transitions.
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 10 ms
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 10 ms
[2023-03-19 08:49:23] [INFO ] Input system was already deterministic with 287 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Graph (trivial) has 262 edges and 255 vertex of which 138 / 255 are part of one of the 11 SCC in 1 ms
Free SCC test removed 127 places
Ensure Unique test removed 164 transitions
Reduce isomorphic transitions removed 164 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 40 transitions
Trivial Post-agglo rules discarded 40 transitions
Performed 40 trivial Post agglomeration. Transition count delta: 40
Iterating post reduction 0 with 40 rules applied. Total rules applied 41 place count 127 transition count 129
Reduce places removed 40 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 1 with 47 rules applied. Total rules applied 88 place count 87 transition count 122
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 91 place count 84 transition count 122
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 7 Pre rules applied. Total rules applied 91 place count 84 transition count 115
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 3 with 14 rules applied. Total rules applied 105 place count 77 transition count 115
Discarding 7 places :
Symmetric choice reduction at 3 with 7 rule applications. Total rules 112 place count 70 transition count 106
Iterating global reduction 3 with 7 rules applied. Total rules applied 119 place count 70 transition count 106
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 120 place count 70 transition count 105
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 121 place count 69 transition count 104
Iterating global reduction 4 with 1 rules applied. Total rules applied 122 place count 69 transition count 104
Performed 30 Post agglomeration using F-continuation condition with reduction of 1 identical transitions.
Deduced a syphon composed of 30 places in 0 ms
Reduce places removed 30 places and 0 transitions.
Iterating global reduction 4 with 60 rules applied. Total rules applied 182 place count 39 transition count 73
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 4 with 6 rules applied. Total rules applied 188 place count 39 transition count 67
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 190 place count 38 transition count 66
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 191 place count 37 transition count 65
Iterating global reduction 6 with 1 rules applied. Total rules applied 192 place count 37 transition count 65
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 6 with 6 rules applied. Total rules applied 198 place count 34 transition count 62
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 199 place count 33 transition count 58
Iterating global reduction 6 with 1 rules applied. Total rules applied 200 place count 33 transition count 58
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 6 with 6 rules applied. Total rules applied 206 place count 33 transition count 52
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 207 place count 32 transition count 49
Iterating global reduction 6 with 1 rules applied. Total rules applied 208 place count 32 transition count 49
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 6 with 1 rules applied. Total rules applied 209 place count 31 transition count 48
Applied a total of 209 rules in 18 ms. Remains 31 /255 variables (removed 224) and now considering 48/334 (removed 286) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 31/255 places, 48/334 transitions.
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 1 ms
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 2 ms
[2023-03-19 08:49:23] [INFO ] Input system was already deterministic with 48 transitions.
Starting structural reductions in LTL mode, iteration 0 : 255/255 places, 334/334 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 231 transition count 310
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 231 transition count 310
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 50 place count 231 transition count 308
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 59 place count 222 transition count 299
Iterating global reduction 1 with 9 rules applied. Total rules applied 68 place count 222 transition count 299
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 69 place count 222 transition count 298
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 75 place count 216 transition count 292
Iterating global reduction 2 with 6 rules applied. Total rules applied 81 place count 216 transition count 292
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 82 place count 216 transition count 291
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 85 place count 213 transition count 288
Iterating global reduction 3 with 3 rules applied. Total rules applied 88 place count 213 transition count 288
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 89 place count 212 transition count 287
Iterating global reduction 3 with 1 rules applied. Total rules applied 90 place count 212 transition count 287
Applied a total of 90 rules in 16 ms. Remains 212 /255 variables (removed 43) and now considering 287/334 (removed 47) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 212/255 places, 287/334 transitions.
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 10 ms
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 10 ms
[2023-03-19 08:49:23] [INFO ] Input system was already deterministic with 287 transitions.
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 12 ms
[2023-03-19 08:49:23] [INFO ] Flatten gal took : 11 ms
[2023-03-19 08:49:23] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 08:49:23] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 255 places, 334 transitions and 735 arcs took 2 ms.
Total runtime 6659 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmartHome-PT-17
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/370
CTLFireability

FORMULA SmartHome-PT-17-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-17-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-17-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-17-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-17-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-17-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-17-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-17-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679216057357

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/370/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/370/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/370/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 14 (type EXCL) for 9 SmartHome-PT-17-CTLFireability-06
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 49 (type FNDP) for 16 SmartHome-PT-17-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type EQUN) for 16 SmartHome-PT-17-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SRCH) for 16 SmartHome-PT-17-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 49 (type FNDP) for SmartHome-PT-17-CTLFireability-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 50 (type EQUN) for SmartHome-PT-17-CTLFireability-08 (obsolete)
lola: CANCELED task # 52 (type SRCH) for SmartHome-PT-17-CTLFireability-08 (obsolete)
lola: FINISHED task # 52 (type SRCH) for SmartHome-PT-17-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
sara: try reading problem file /home/mcc/execution/370/CTLFireability-50.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 50 (type EQUN) for SmartHome-PT-17-CTLFireability-08
lola: result : true
lola: LAUNCH task # 55 (type FNDP) for 38 SmartHome-PT-17-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 55 (type FNDP) for SmartHome-PT-17-CTLFireability-15
lola: result : true
lola: fired transitions : 29
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-17-CTLFireability-08: DISJ true findpath

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14 CTL EXCL 5/327 2/32 SmartHome-PT-17-CTLFireability-06 494829 m, 98965 m/sec, 7320040 t fired, .

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14 CTL EXCL 10/327 5/32 SmartHome-PT-17-CTLFireability-06 1013356 m, 103705 m/sec, 15060295 t fired, .

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lola: FINISHED task # 14 (type EXCL) for SmartHome-PT-17-CTLFireability-06
lola: result : true
lola: markings : 1247232
lola: fired transitions : 18633704
lola: time used : 12.000000
lola: memory pages used : 5
lola: LAUNCH task # 33 (type EXCL) for 32 SmartHome-PT-17-CTLFireability-13
lola: time limit : 358 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for SmartHome-PT-17-CTLFireability-13
lola: result : true
lola: markings : 934
lola: fired transitions : 2182
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 SmartHome-PT-17-CTLFireability-11
lola: time limit : 398 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for SmartHome-PT-17-CTLFireability-11
lola: result : false
lola: markings : 672
lola: fired transitions : 1491
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 23 SmartHome-PT-17-CTLFireability-09
lola: time limit : 448 sec
lola: memory limit: 32 pages
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24 CTL EXCL 8/448 4/32 SmartHome-PT-17-CTLFireability-09 590941 m, 65666 m/sec, 3122004 t fired, .

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24 CTL EXCL 18/448 8/32 SmartHome-PT-17-CTLFireability-09 1217446 m, 67892 m/sec, 6972648 t fired, .

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24 CTL EXCL 23/448 11/32 SmartHome-PT-17-CTLFireability-09 1588048 m, 74120 m/sec, 8930337 t fired, .

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24 CTL EXCL 28/448 13/32 SmartHome-PT-17-CTLFireability-09 1931296 m, 68649 m/sec, 10807118 t fired, .

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24 CTL EXCL 33/448 15/32 SmartHome-PT-17-CTLFireability-09 2234773 m, 60695 m/sec, 12728921 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 38/448 16/32 SmartHome-PT-17-CTLFireability-09 2477876 m, 48620 m/sec, 14365388 t fired, .

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# running tasks: 1 of 4 Visible: 11
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SmartHome-PT-17-CTLFireability-08: DISJ true findpath
SmartHome-PT-17-CTLFireability-11: CTL false CTL model checker
SmartHome-PT-17-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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24 CTL EXCL 43/448 18/32 SmartHome-PT-17-CTLFireability-09 2768256 m, 58076 m/sec, 16216996 t fired, .

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SmartHome-PT-17-CTLFireability-11: CTL false CTL model checker
SmartHome-PT-17-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 48/448 20/32 SmartHome-PT-17-CTLFireability-09 3172884 m, 80925 m/sec, 17973657 t fired, .

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SmartHome-PT-17-CTLFireability-11: CTL false CTL model checker
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SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 53/448 22/32 SmartHome-PT-17-CTLFireability-09 3446983 m, 54819 m/sec, 19593357 t fired, .

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SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 58/448 25/32 SmartHome-PT-17-CTLFireability-09 3915125 m, 93628 m/sec, 21265499 t fired, .

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SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 63/448 29/32 SmartHome-PT-17-CTLFireability-09 4453200 m, 107615 m/sec, 22888547 t fired, .

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SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 68/448 31/32 SmartHome-PT-17-CTLFireability-09 4819224 m, 73204 m/sec, 24648034 t fired, .

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lola: CANCELED task # 24 (type EXCL) for SmartHome-PT-17-CTLFireability-09 (memory limit exceeded)
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SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 86 secs. Pages in use: 32
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lola: LAUNCH task # 12 (type EXCL) for 9 SmartHome-PT-17-CTLFireability-06
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lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL) for SmartHome-PT-17-CTLFireability-06
lola: result : false
lola: markings : 152
lola: fired transitions : 168
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 SmartHome-PT-17-CTLFireability-04
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lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-17-CTLFireability-06: CONJ false CTL model checker
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SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/585 3/32 SmartHome-PT-17-CTLFireability-04 321631 m, 64326 m/sec, 2026423 t fired, .

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SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/585 4/32 SmartHome-PT-17-CTLFireability-04 618662 m, 59406 m/sec, 4214961 t fired, .

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SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 15/585 6/32 SmartHome-PT-17-CTLFireability-04 944323 m, 65132 m/sec, 6398200 t fired, .

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SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 20/585 8/32 SmartHome-PT-17-CTLFireability-04 1279881 m, 67111 m/sec, 8438647 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 25/585 11/32 SmartHome-PT-17-CTLFireability-04 1630090 m, 70041 m/sec, 10509860 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 30/585 13/32 SmartHome-PT-17-CTLFireability-04 1969376 m, 67857 m/sec, 12495774 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 35/585 15/32 SmartHome-PT-17-CTLFireability-04 2270821 m, 60289 m/sec, 14699716 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 40/585 17/32 SmartHome-PT-17-CTLFireability-04 2575774 m, 60990 m/sec, 16793673 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 45/585 19/32 SmartHome-PT-17-CTLFireability-04 2888444 m, 62534 m/sec, 18826113 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 50/585 21/32 SmartHome-PT-17-CTLFireability-04 3174248 m, 57160 m/sec, 20966056 t fired, .

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SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 55/585 22/32 SmartHome-PT-17-CTLFireability-04 3430421 m, 51234 m/sec, 23089482 t fired, .

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SmartHome-PT-17-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 60/585 24/32 SmartHome-PT-17-CTLFireability-04 3688772 m, 51670 m/sec, 25352795 t fired, .

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SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 65/585 25/32 SmartHome-PT-17-CTLFireability-04 3949629 m, 52171 m/sec, 27577070 t fired, .

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SmartHome-PT-17-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 70/585 27/32 SmartHome-PT-17-CTLFireability-04 4204781 m, 51030 m/sec, 29806141 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 75/585 29/32 SmartHome-PT-17-CTLFireability-04 4539319 m, 66907 m/sec, 31763064 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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7 CTL EXCL 80/585 31/32 SmartHome-PT-17-CTLFireability-04 4836819 m, 59500 m/sec, 33780268 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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4 CTL EXCL 5/685 2/32 SmartHome-PT-17-CTLFireability-01 282431 m, 56486 m/sec, 1837938 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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4 CTL EXCL 10/685 4/32 SmartHome-PT-17-CTLFireability-01 519493 m, 47412 m/sec, 3804608 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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4 CTL EXCL 15/685 5/32 SmartHome-PT-17-CTLFireability-01 747869 m, 45675 m/sec, 5742191 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-17-CTLFireability-15: DISJ 0 1 0 0 4 0 0 5

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4 CTL EXCL 20/685 7/32 SmartHome-PT-17-CTLFireability-01 977614 m, 45949 m/sec, 7699718 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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4 CTL EXCL 25/685 8/32 SmartHome-PT-17-CTLFireability-01 1244123 m, 53301 m/sec, 9549791 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 30/685 10/32 SmartHome-PT-17-CTLFireability-01 1518748 m, 54925 m/sec, 11493426 t fired, .

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SmartHome-PT-17-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 35/685 12/32 SmartHome-PT-17-CTLFireability-01 1758931 m, 48036 m/sec, 13382256 t fired, .

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SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 40/685 13/32 SmartHome-PT-17-CTLFireability-01 2006662 m, 49546 m/sec, 15271052 t fired, .

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4 CTL EXCL 45/685 14/32 SmartHome-PT-17-CTLFireability-01 2226599 m, 43987 m/sec, 17174785 t fired, .

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SmartHome-PT-17-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 50/685 16/32 SmartHome-PT-17-CTLFireability-01 2427539 m, 40188 m/sec, 19018497 t fired, .

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4 CTL EXCL 55/685 17/32 SmartHome-PT-17-CTLFireability-01 2655044 m, 45501 m/sec, 20918341 t fired, .

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4 CTL EXCL 60/685 19/32 SmartHome-PT-17-CTLFireability-01 2921770 m, 53345 m/sec, 22831058 t fired, .

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4 CTL EXCL 65/685 21/32 SmartHome-PT-17-CTLFireability-01 3192955 m, 54237 m/sec, 24544122 t fired, .

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4 CTL EXCL 70/685 22/32 SmartHome-PT-17-CTLFireability-01 3415493 m, 44507 m/sec, 26227925 t fired, .

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4 CTL EXCL 75/685 24/32 SmartHome-PT-17-CTLFireability-01 3671042 m, 51109 m/sec, 27882149 t fired, .

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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmartHome-PT-17"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmartHome-PT-17, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647200282"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmartHome-PT-17.tgz
mv SmartHome-PT-17 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;