Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647100210.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmartHome-PT-08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647100210
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 528K
-rw-r--r-- 1 mcc users 6.9K Feb 26 05:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 26 05:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 26 05:46 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 05:46 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 17:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 05:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Feb 26 05:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Feb 26 05:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 26 05:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 64K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmartHome-PT-08-CTLFireability-00
FORMULA_NAME SmartHome-PT-08-CTLFireability-01
FORMULA_NAME SmartHome-PT-08-CTLFireability-02
FORMULA_NAME SmartHome-PT-08-CTLFireability-03
FORMULA_NAME SmartHome-PT-08-CTLFireability-04
FORMULA_NAME SmartHome-PT-08-CTLFireability-05
FORMULA_NAME SmartHome-PT-08-CTLFireability-06
FORMULA_NAME SmartHome-PT-08-CTLFireability-07
FORMULA_NAME SmartHome-PT-08-CTLFireability-08
FORMULA_NAME SmartHome-PT-08-CTLFireability-09
FORMULA_NAME SmartHome-PT-08-CTLFireability-10
FORMULA_NAME SmartHome-PT-08-CTLFireability-11
FORMULA_NAME SmartHome-PT-08-CTLFireability-12
FORMULA_NAME SmartHome-PT-08-CTLFireability-13
FORMULA_NAME SmartHome-PT-08-CTLFireability-14
FORMULA_NAME SmartHome-PT-08-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679202671492

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmartHome-PT-08
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 05:11:14] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 05:11:14] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 05:11:15] [INFO ] Load time of PNML (sax parser for PT used): 130 ms
[2023-03-19 05:11:15] [INFO ] Transformed 252 places.
[2023-03-19 05:11:15] [INFO ] Transformed 291 transitions.
[2023-03-19 05:11:15] [INFO ] Found NUPN structural information;
[2023-03-19 05:11:15] [INFO ] Parsed PT model containing 252 places and 291 transitions and 664 arcs in 279 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 22 ms.
Initial state reduction rules removed 2 formulas.
Deduced a syphon composed of 20 places in 8 ms
Reduce places removed 20 places and 21 transitions.
FORMULA SmartHome-PT-08-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmartHome-PT-08-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 80 out of 232 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 232/232 places, 270/270 transitions.
Discarding 47 places :
Symmetric choice reduction at 0 with 47 rule applications. Total rules 47 place count 185 transition count 223
Iterating global reduction 0 with 47 rules applied. Total rules applied 94 place count 185 transition count 223
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 97 place count 185 transition count 220
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 103 place count 179 transition count 214
Iterating global reduction 1 with 6 rules applied. Total rules applied 109 place count 179 transition count 214
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 112 place count 176 transition count 211
Iterating global reduction 1 with 3 rules applied. Total rules applied 115 place count 176 transition count 211
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 116 place count 175 transition count 210
Iterating global reduction 1 with 1 rules applied. Total rules applied 117 place count 175 transition count 210
Applied a total of 117 rules in 122 ms. Remains 175 /232 variables (removed 57) and now considering 210/270 (removed 60) transitions.
// Phase 1: matrix 210 rows 175 cols
[2023-03-19 05:11:15] [INFO ] Computed 11 place invariants in 20 ms
[2023-03-19 05:11:15] [INFO ] Implicit Places using invariants in 424 ms returned []
[2023-03-19 05:11:15] [INFO ] Invariant cache hit.
[2023-03-19 05:11:16] [INFO ] Implicit Places using invariants and state equation in 319 ms returned []
Implicit Place search using SMT with State Equation took 810 ms to find 0 implicit places.
[2023-03-19 05:11:16] [INFO ] Invariant cache hit.
[2023-03-19 05:11:16] [INFO ] Dead Transitions using invariants and state equation in 303 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 175/232 places, 210/270 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1240 ms. Remains : 175/232 places, 210/270 transitions.
Support contains 80 out of 175 places after structural reductions.
[2023-03-19 05:11:16] [INFO ] Flatten gal took : 59 ms
[2023-03-19 05:11:16] [INFO ] Flatten gal took : 26 ms
[2023-03-19 05:11:17] [INFO ] Input system was already deterministic with 210 transitions.
Support contains 79 out of 175 places (down from 80) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 63 resets, run finished after 873 ms. (steps per millisecond=11 ) properties (out of 59) seen :45
Incomplete Best-First random walk after 10001 steps, including 8 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 14) seen :1
Incomplete Best-First random walk after 10001 steps, including 7 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 10 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10000 steps, including 10 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 52 resets, run finished after 80 ms. (steps per millisecond=125 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 8 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 13) seen :1
Incomplete Best-First random walk after 10001 steps, including 11 resets, run finished after 78 ms. (steps per millisecond=128 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 10 resets, run finished after 72 ms. (steps per millisecond=138 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 10 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 12) seen :2
Incomplete Best-First random walk after 10001 steps, including 7 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 10) seen :1
Incomplete Best-First random walk after 10001 steps, including 4 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 9) seen :0
Running SMT prover for 9 properties.
[2023-03-19 05:11:18] [INFO ] Invariant cache hit.
[2023-03-19 05:11:18] [INFO ] [Real]Absence check using 11 positive place invariants in 8 ms returned sat
[2023-03-19 05:11:19] [INFO ] After 187ms SMT Verify possible using state equation in real domain returned unsat :2 sat :2 real:5
[2023-03-19 05:11:19] [INFO ] After 268ms SMT Verify possible using trap constraints in real domain returned unsat :2 sat :1 real:6
Attempting to minimize the solution found.
Minimization took 27 ms.
[2023-03-19 05:11:19] [INFO ] After 559ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:7
[2023-03-19 05:11:19] [INFO ] [Nat]Absence check using 11 positive place invariants in 8 ms returned sat
[2023-03-19 05:11:19] [INFO ] After 236ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :7
[2023-03-19 05:11:19] [INFO ] Deduced a trap composed of 41 places in 74 ms of which 1 ms to minimize.
[2023-03-19 05:11:19] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 96 ms
[2023-03-19 05:11:19] [INFO ] Deduced a trap composed of 35 places in 60 ms of which 1 ms to minimize.
[2023-03-19 05:11:19] [INFO ] Deduced a trap composed of 22 places in 39 ms of which 1 ms to minimize.
[2023-03-19 05:11:19] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 134 ms
[2023-03-19 05:11:19] [INFO ] After 619ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :7
Attempting to minimize the solution found.
Minimization took 102 ms.
[2023-03-19 05:11:20] [INFO ] After 916ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :7
Fused 9 Parikh solutions to 7 different solutions.
Parikh walk visited 1 properties in 43 ms.
Support contains 19 out of 175 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 175/175 places, 210/210 transitions.
Graph (trivial) has 141 edges and 175 vertex of which 32 / 175 are part of one of the 3 SCC in 4 ms
Free SCC test removed 29 places
Drop transitions removed 41 transitions
Reduce isomorphic transitions removed 41 transitions.
Drop transitions removed 46 transitions
Trivial Post-agglo rules discarded 46 transitions
Performed 46 trivial Post agglomeration. Transition count delta: 46
Iterating post reduction 0 with 46 rules applied. Total rules applied 47 place count 146 transition count 123
Reduce places removed 46 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 55 rules applied. Total rules applied 102 place count 100 transition count 114
Reduce places removed 5 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 2 with 9 rules applied. Total rules applied 111 place count 95 transition count 110
Reduce places removed 2 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 3 with 4 rules applied. Total rules applied 115 place count 93 transition count 108
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 118 place count 91 transition count 107
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 7 Pre rules applied. Total rules applied 118 place count 91 transition count 100
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 5 with 14 rules applied. Total rules applied 132 place count 84 transition count 100
Discarding 11 places :
Symmetric choice reduction at 5 with 11 rule applications. Total rules 143 place count 73 transition count 89
Iterating global reduction 5 with 11 rules applied. Total rules applied 154 place count 73 transition count 89
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 5 with 5 rules applied. Total rules applied 159 place count 73 transition count 84
Discarding 2 places :
Symmetric choice reduction at 6 with 2 rule applications. Total rules 161 place count 71 transition count 82
Iterating global reduction 6 with 2 rules applied. Total rules applied 163 place count 71 transition count 82
Performed 26 Post agglomeration using F-continuation condition with reduction of 4 identical transitions.
Deduced a syphon composed of 26 places in 0 ms
Reduce places removed 26 places and 0 transitions.
Iterating global reduction 6 with 52 rules applied. Total rules applied 215 place count 45 transition count 52
Drop transitions removed 3 transitions
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 6 with 6 rules applied. Total rules applied 221 place count 45 transition count 46
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 7 with 6 rules applied. Total rules applied 227 place count 45 transition count 40
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 228 place count 44 transition count 40
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 8 with 1 rules applied. Total rules applied 229 place count 43 transition count 39
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 230 place count 42 transition count 39
Free-agglomeration rule applied 2 times.
Iterating global reduction 9 with 2 rules applied. Total rules applied 232 place count 42 transition count 37
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 9 with 2 rules applied. Total rules applied 234 place count 40 transition count 37
Applied a total of 234 rules in 64 ms. Remains 40 /175 variables (removed 135) and now considering 37/210 (removed 173) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 64 ms. Remains : 40/175 places, 37/210 transitions.
Incomplete random walk after 10000 steps, including 423 resets, run finished after 195 ms. (steps per millisecond=51 ) properties (out of 6) seen :2
Incomplete Best-First random walk after 10001 steps, including 66 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 85 ms. (steps per millisecond=117 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 68 ms. (steps per millisecond=147 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
// Phase 1: matrix 37 rows 40 cols
[2023-03-19 05:11:20] [INFO ] Computed 9 place invariants in 1 ms
[2023-03-19 05:11:20] [INFO ] [Real]Absence check using 9 positive place invariants in 5 ms returned sat
[2023-03-19 05:11:20] [INFO ] After 28ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:3
[2023-03-19 05:11:20] [INFO ] After 36ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :1 real:3
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-19 05:11:20] [INFO ] After 92ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :1 real:3
[2023-03-19 05:11:20] [INFO ] [Nat]Absence check using 9 positive place invariants in 4 ms returned sat
[2023-03-19 05:11:20] [INFO ] After 35ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-19 05:11:20] [INFO ] Deduced a trap composed of 5 places in 29 ms of which 0 ms to minimize.
[2023-03-19 05:11:20] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 36 ms
[2023-03-19 05:11:20] [INFO ] After 96ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 17 ms.
[2023-03-19 05:11:20] [INFO ] After 161ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Parikh walk visited 0 properties in 6 ms.
Support contains 16 out of 40 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 40/40 places, 37/37 transitions.
Graph (trivial) has 2 edges and 40 vertex of which 2 / 40 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Applied a total of 1 rules in 3 ms. Remains 39 /40 variables (removed 1) and now considering 35/37 (removed 2) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3 ms. Remains : 39/40 places, 35/37 transitions.
Incomplete random walk after 10000 steps, including 500 resets, run finished after 148 ms. (steps per millisecond=67 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 221 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
// Phase 1: matrix 35 rows 39 cols
[2023-03-19 05:11:21] [INFO ] Computed 9 place invariants in 1 ms
[2023-03-19 05:11:21] [INFO ] [Real]Absence check using 9 positive place invariants in 3 ms returned sat
[2023-03-19 05:11:21] [INFO ] After 23ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:2
[2023-03-19 05:11:21] [INFO ] State equation strengthened by 5 read => feed constraints.
[2023-03-19 05:11:21] [INFO ] After 7ms SMT Verify possible using 5 Read/Feed constraints in real domain returned unsat :0 sat :1 real:2
[2023-03-19 05:11:21] [INFO ] After 14ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :1 real:2
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-19 05:11:21] [INFO ] After 81ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :1 real:2
[2023-03-19 05:11:21] [INFO ] [Nat]Absence check using 9 positive place invariants in 3 ms returned sat
[2023-03-19 05:11:21] [INFO ] After 32ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-19 05:11:21] [INFO ] After 16ms SMT Verify possible using 5 Read/Feed constraints in natural domain returned unsat :0 sat :3
[2023-03-19 05:11:21] [INFO ] Deduced a trap composed of 4 places in 26 ms of which 0 ms to minimize.
[2023-03-19 05:11:21] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 33 ms
[2023-03-19 05:11:21] [INFO ] After 67ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 15 ms.
[2023-03-19 05:11:21] [INFO ] After 157ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Parikh walk visited 0 properties in 3 ms.
Support contains 13 out of 39 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 39/39 places, 35/35 transitions.
Graph (trivial) has 3 edges and 39 vertex of which 2 / 39 are part of one of the 1 SCC in 1 ms
Free SCC test removed 1 places
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 2 Pre rules applied. Total rules applied 1 place count 38 transition count 31
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 5 place count 36 transition count 31
Applied a total of 5 rules in 5 ms. Remains 36 /39 variables (removed 3) and now considering 31/35 (removed 4) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 5 ms. Remains : 36/39 places, 31/35 transitions.
Incomplete random walk after 10000 steps, including 573 resets, run finished after 99 ms. (steps per millisecond=101 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 248 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 59 ms. (steps per millisecond=169 ) properties (out of 3) seen :0
Finished probabilistic random walk after 10345 steps, run visited all 3 properties in 65 ms. (steps per millisecond=159 )
Probabilistic random walk after 10345 steps, saw 2208 distinct states, run finished after 66 ms. (steps per millisecond=156 ) properties seen :3
Successfully simplified 2 atomic propositions for a total of 14 simplifications.
[2023-03-19 05:11:21] [INFO ] Flatten gal took : 23 ms
[2023-03-19 05:11:21] [INFO ] Flatten gal took : 21 ms
[2023-03-19 05:11:21] [INFO ] Input system was already deterministic with 210 transitions.
Support contains 71 out of 175 places (down from 75) after GAL structural reductions.
Computed a total of 19 stabilizing places and 19 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 151 transition count 186
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 151 transition count 186
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 50 place count 151 transition count 184
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 60 place count 141 transition count 174
Iterating global reduction 1 with 10 rules applied. Total rules applied 70 place count 141 transition count 174
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 71 place count 141 transition count 173
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 77 place count 135 transition count 167
Iterating global reduction 2 with 6 rules applied. Total rules applied 83 place count 135 transition count 167
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 84 place count 134 transition count 166
Iterating global reduction 2 with 1 rules applied. Total rules applied 85 place count 134 transition count 166
Applied a total of 85 rules in 25 ms. Remains 134 /175 variables (removed 41) and now considering 166/210 (removed 44) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 25 ms. Remains : 134/175 places, 166/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 15 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 16 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 166 transitions.
Starting structural reductions in LTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 151 transition count 186
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 151 transition count 186
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 51 place count 151 transition count 183
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 61 place count 141 transition count 173
Iterating global reduction 1 with 10 rules applied. Total rules applied 71 place count 141 transition count 173
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 72 place count 141 transition count 172
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 79 place count 134 transition count 165
Iterating global reduction 2 with 7 rules applied. Total rules applied 86 place count 134 transition count 165
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 87 place count 133 transition count 164
Iterating global reduction 2 with 1 rules applied. Total rules applied 88 place count 133 transition count 164
Applied a total of 88 rules in 22 ms. Remains 133 /175 variables (removed 42) and now considering 164/210 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 133/175 places, 164/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 14 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 16 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 164 transitions.
Starting structural reductions in LTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Discarding 22 places :
Symmetric choice reduction at 0 with 22 rule applications. Total rules 22 place count 153 transition count 188
Iterating global reduction 0 with 22 rules applied. Total rules applied 44 place count 153 transition count 188
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 45 place count 153 transition count 187
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 55 place count 143 transition count 177
Iterating global reduction 1 with 10 rules applied. Total rules applied 65 place count 143 transition count 177
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 66 place count 143 transition count 176
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 73 place count 136 transition count 169
Iterating global reduction 2 with 7 rules applied. Total rules applied 80 place count 136 transition count 169
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 81 place count 135 transition count 168
Iterating global reduction 2 with 1 rules applied. Total rules applied 82 place count 135 transition count 168
Applied a total of 82 rules in 20 ms. Remains 135 /175 variables (removed 40) and now considering 168/210 (removed 42) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 135/175 places, 168/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 15 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 16 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 168 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Graph (trivial) has 137 edges and 175 vertex of which 21 / 175 are part of one of the 2 SCC in 0 ms
Free SCC test removed 19 places
Ensure Unique test removed 25 transitions
Reduce isomorphic transitions removed 25 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 52 transitions
Trivial Post-agglo rules discarded 52 transitions
Performed 52 trivial Post agglomeration. Transition count delta: 52
Iterating post reduction 0 with 52 rules applied. Total rules applied 53 place count 155 transition count 132
Reduce places removed 52 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 61 rules applied. Total rules applied 114 place count 103 transition count 123
Reduce places removed 5 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 7 rules applied. Total rules applied 121 place count 98 transition count 121
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 2 rules applied. Total rules applied 123 place count 97 transition count 120
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 124 place count 96 transition count 120
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 7 Pre rules applied. Total rules applied 124 place count 96 transition count 113
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 5 with 14 rules applied. Total rules applied 138 place count 89 transition count 113
Discarding 16 places :
Symmetric choice reduction at 5 with 16 rule applications. Total rules 154 place count 73 transition count 97
Iterating global reduction 5 with 16 rules applied. Total rules applied 170 place count 73 transition count 97
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 5 with 7 rules applied. Total rules applied 177 place count 73 transition count 90
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 178 place count 72 transition count 90
Discarding 2 places :
Symmetric choice reduction at 7 with 2 rule applications. Total rules 180 place count 70 transition count 88
Iterating global reduction 7 with 2 rules applied. Total rules applied 182 place count 70 transition count 88
Performed 19 Post agglomeration using F-continuation condition with reduction of 1 identical transitions.
Deduced a syphon composed of 19 places in 0 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 7 with 38 rules applied. Total rules applied 220 place count 51 transition count 68
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 7 with 6 rules applied. Total rules applied 226 place count 51 transition count 62
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 8 with 4 rules applied. Total rules applied 230 place count 49 transition count 60
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 232 place count 48 transition count 59
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 9 with 6 rules applied. Total rules applied 238 place count 48 transition count 53
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 9 with 1 rules applied. Total rules applied 239 place count 47 transition count 52
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 240 place count 46 transition count 52
Applied a total of 240 rules in 51 ms. Remains 46 /175 variables (removed 129) and now considering 52/210 (removed 158) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 52 ms. Remains : 46/175 places, 52/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 4 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 4 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 52 transitions.
Starting structural reductions in LTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 152 transition count 187
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 152 transition count 187
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 48 place count 152 transition count 185
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 57 place count 143 transition count 176
Iterating global reduction 1 with 9 rules applied. Total rules applied 66 place count 143 transition count 176
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 67 place count 143 transition count 175
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 73 place count 137 transition count 169
Iterating global reduction 2 with 6 rules applied. Total rules applied 79 place count 137 transition count 169
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 80 place count 136 transition count 168
Iterating global reduction 2 with 1 rules applied. Total rules applied 81 place count 136 transition count 168
Applied a total of 81 rules in 15 ms. Remains 136 /175 variables (removed 39) and now considering 168/210 (removed 42) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 136/175 places, 168/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 10 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 10 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 168 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Graph (trivial) has 154 edges and 175 vertex of which 44 / 175 are part of one of the 5 SCC in 1 ms
Free SCC test removed 39 places
Ensure Unique test removed 50 transitions
Reduce isomorphic transitions removed 50 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 43 transitions
Trivial Post-agglo rules discarded 43 transitions
Performed 43 trivial Post agglomeration. Transition count delta: 43
Iterating post reduction 0 with 43 rules applied. Total rules applied 44 place count 135 transition count 116
Reduce places removed 43 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 53 rules applied. Total rules applied 97 place count 92 transition count 106
Reduce places removed 5 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 7 rules applied. Total rules applied 104 place count 87 transition count 104
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 2 rules applied. Total rules applied 106 place count 86 transition count 103
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 107 place count 85 transition count 103
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 8 Pre rules applied. Total rules applied 107 place count 85 transition count 95
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 5 with 16 rules applied. Total rules applied 123 place count 77 transition count 95
Discarding 11 places :
Symmetric choice reduction at 5 with 11 rule applications. Total rules 134 place count 66 transition count 84
Iterating global reduction 5 with 11 rules applied. Total rules applied 145 place count 66 transition count 84
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 148 place count 66 transition count 81
Performed 17 Post agglomeration using F-continuation condition.Transition count delta: 17
Deduced a syphon composed of 17 places in 0 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 6 with 34 rules applied. Total rules applied 182 place count 49 transition count 64
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 6 with 2 rules applied. Total rules applied 184 place count 49 transition count 62
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 7 with 4 rules applied. Total rules applied 188 place count 47 transition count 60
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 7 with 6 rules applied. Total rules applied 194 place count 47 transition count 54
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 7 with 1 rules applied. Total rules applied 195 place count 47 transition count 53
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 196 place count 46 transition count 53
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 9 with 1 rules applied. Total rules applied 197 place count 45 transition count 52
Reduce places removed 1 places and 0 transitions.
Graph (trivial) has 17 edges and 44 vertex of which 2 / 44 are part of one of the 1 SCC in 1 ms
Free SCC test removed 1 places
Iterating post reduction 9 with 2 rules applied. Total rules applied 199 place count 43 transition count 52
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 10 with 2 rules applied. Total rules applied 201 place count 43 transition count 50
Applied a total of 201 rules in 36 ms. Remains 43 /175 variables (removed 132) and now considering 50/210 (removed 160) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 36 ms. Remains : 43/175 places, 50/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 3 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 3 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 50 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Graph (trivial) has 167 edges and 175 vertex of which 55 / 175 are part of one of the 5 SCC in 1 ms
Free SCC test removed 50 places
Ensure Unique test removed 65 transitions
Reduce isomorphic transitions removed 65 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 44 transitions
Trivial Post-agglo rules discarded 44 transitions
Performed 44 trivial Post agglomeration. Transition count delta: 44
Iterating post reduction 0 with 44 rules applied. Total rules applied 45 place count 124 transition count 100
Reduce places removed 44 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 1 with 57 rules applied. Total rules applied 102 place count 80 transition count 87
Reduce places removed 7 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 2 with 11 rules applied. Total rules applied 113 place count 73 transition count 83
Reduce places removed 2 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 3 rules applied. Total rules applied 116 place count 71 transition count 82
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 118 place count 70 transition count 81
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 7 Pre rules applied. Total rules applied 118 place count 70 transition count 74
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 5 with 14 rules applied. Total rules applied 132 place count 63 transition count 74
Discarding 11 places :
Symmetric choice reduction at 5 with 11 rule applications. Total rules 143 place count 52 transition count 63
Iterating global reduction 5 with 11 rules applied. Total rules applied 154 place count 52 transition count 63
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 157 place count 52 transition count 60
Performed 17 Post agglomeration using F-continuation condition.Transition count delta: 17
Deduced a syphon composed of 17 places in 0 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 6 with 34 rules applied. Total rules applied 191 place count 35 transition count 43
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 6 with 2 rules applied. Total rules applied 193 place count 35 transition count 41
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 7 with 4 rules applied. Total rules applied 197 place count 33 transition count 39
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 7 with 10 rules applied. Total rules applied 207 place count 33 transition count 29
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 7 with 2 rules applied. Total rules applied 209 place count 31 transition count 29
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 211 place count 29 transition count 27
Applied a total of 211 rules in 26 ms. Remains 29 /175 variables (removed 146) and now considering 27/210 (removed 183) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 29/175 places, 27/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 2 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 2 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 27 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Graph (trivial) has 133 edges and 175 vertex of which 22 / 175 are part of one of the 2 SCC in 1 ms
Free SCC test removed 20 places
Ensure Unique test removed 26 transitions
Reduce isomorphic transitions removed 26 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 47 transitions
Trivial Post-agglo rules discarded 47 transitions
Performed 47 trivial Post agglomeration. Transition count delta: 47
Iterating post reduction 0 with 47 rules applied. Total rules applied 48 place count 154 transition count 136
Reduce places removed 47 places and 0 transitions.
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 1 with 54 rules applied. Total rules applied 102 place count 107 transition count 129
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 2 with 8 rules applied. Total rules applied 110 place count 103 transition count 125
Reduce places removed 2 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 3 with 4 rules applied. Total rules applied 114 place count 101 transition count 123
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 117 place count 99 transition count 122
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 10 Pre rules applied. Total rules applied 117 place count 99 transition count 112
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 5 with 20 rules applied. Total rules applied 137 place count 89 transition count 112
Discarding 13 places :
Symmetric choice reduction at 5 with 13 rule applications. Total rules 150 place count 76 transition count 99
Iterating global reduction 5 with 13 rules applied. Total rules applied 163 place count 76 transition count 99
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 5 with 6 rules applied. Total rules applied 169 place count 76 transition count 93
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 170 place count 75 transition count 93
Discarding 1 places :
Symmetric choice reduction at 7 with 1 rule applications. Total rules 171 place count 74 transition count 92
Iterating global reduction 7 with 1 rules applied. Total rules applied 172 place count 74 transition count 92
Performed 18 Post agglomeration using F-continuation condition with reduction of 1 identical transitions.
Deduced a syphon composed of 18 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 7 with 36 rules applied. Total rules applied 208 place count 56 transition count 73
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 7 with 4 rules applied. Total rules applied 212 place count 56 transition count 69
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 8 with 2 rules applied. Total rules applied 214 place count 55 transition count 68
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 9 with 4 rules applied. Total rules applied 218 place count 53 transition count 66
Drop transitions removed 4 transitions
Redundant transition composition rules discarded 4 transitions
Iterating global reduction 9 with 4 rules applied. Total rules applied 222 place count 53 transition count 62
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 9 with 2 rules applied. Total rules applied 224 place count 53 transition count 60
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 10 with 2 rules applied. Total rules applied 226 place count 51 transition count 60
Applied a total of 226 rules in 31 ms. Remains 51 /175 variables (removed 124) and now considering 60/210 (removed 150) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 51/175 places, 60/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 4 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 4 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 25 place count 150 transition count 185
Iterating global reduction 0 with 25 rules applied. Total rules applied 50 place count 150 transition count 185
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 53 place count 150 transition count 182
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 63 place count 140 transition count 172
Iterating global reduction 1 with 10 rules applied. Total rules applied 73 place count 140 transition count 172
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 74 place count 140 transition count 171
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 81 place count 133 transition count 164
Iterating global reduction 2 with 7 rules applied. Total rules applied 88 place count 133 transition count 164
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 89 place count 132 transition count 163
Iterating global reduction 2 with 1 rules applied. Total rules applied 90 place count 132 transition count 163
Applied a total of 90 rules in 18 ms. Remains 132 /175 variables (removed 43) and now considering 163/210 (removed 47) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 132/175 places, 163/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 163 transitions.
Starting structural reductions in LTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 152 transition count 187
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 152 transition count 187
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 48 place count 152 transition count 185
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 58 place count 142 transition count 175
Iterating global reduction 1 with 10 rules applied. Total rules applied 68 place count 142 transition count 175
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 69 place count 142 transition count 174
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 76 place count 135 transition count 167
Iterating global reduction 2 with 7 rules applied. Total rules applied 83 place count 135 transition count 167
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 84 place count 134 transition count 166
Iterating global reduction 2 with 1 rules applied. Total rules applied 85 place count 134 transition count 166
Applied a total of 85 rules in 16 ms. Remains 134 /175 variables (removed 41) and now considering 166/210 (removed 44) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 134/175 places, 166/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 166 transitions.
Starting structural reductions in LTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 151 transition count 186
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 151 transition count 186
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 51 place count 151 transition count 183
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 59 place count 143 transition count 175
Iterating global reduction 1 with 8 rules applied. Total rules applied 67 place count 143 transition count 175
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 68 place count 143 transition count 174
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 74 place count 137 transition count 168
Iterating global reduction 2 with 6 rules applied. Total rules applied 80 place count 137 transition count 168
Applied a total of 80 rules in 14 ms. Remains 137 /175 variables (removed 38) and now considering 168/210 (removed 42) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 137/175 places, 168/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 168 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Graph (trivial) has 144 edges and 175 vertex of which 38 / 175 are part of one of the 4 SCC in 0 ms
Free SCC test removed 34 places
Ensure Unique test removed 43 transitions
Reduce isomorphic transitions removed 43 transitions.
Drop transitions removed 47 transitions
Trivial Post-agglo rules discarded 47 transitions
Performed 47 trivial Post agglomeration. Transition count delta: 47
Iterating post reduction 0 with 47 rules applied. Total rules applied 48 place count 141 transition count 120
Reduce places removed 47 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 1 with 54 rules applied. Total rules applied 102 place count 94 transition count 113
Reduce places removed 3 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 5 rules applied. Total rules applied 107 place count 91 transition count 111
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 109 place count 89 transition count 111
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 9 Pre rules applied. Total rules applied 109 place count 89 transition count 102
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 4 with 18 rules applied. Total rules applied 127 place count 80 transition count 102
Discarding 12 places :
Symmetric choice reduction at 4 with 12 rule applications. Total rules 139 place count 68 transition count 90
Iterating global reduction 4 with 12 rules applied. Total rules applied 151 place count 68 transition count 90
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 4 with 5 rules applied. Total rules applied 156 place count 68 transition count 85
Discarding 2 places :
Symmetric choice reduction at 5 with 2 rule applications. Total rules 158 place count 66 transition count 83
Iterating global reduction 5 with 2 rules applied. Total rules applied 160 place count 66 transition count 83
Performed 20 Post agglomeration using F-continuation condition with reduction of 1 identical transitions.
Deduced a syphon composed of 20 places in 0 ms
Reduce places removed 20 places and 0 transitions.
Iterating global reduction 5 with 40 rules applied. Total rules applied 200 place count 46 transition count 62
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 5 with 8 rules applied. Total rules applied 208 place count 46 transition count 54
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 6 with 4 rules applied. Total rules applied 212 place count 44 transition count 52
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 7 with 6 rules applied. Total rules applied 218 place count 41 transition count 49
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 7 with 5 rules applied. Total rules applied 223 place count 41 transition count 44
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 224 place count 40 transition count 44
Applied a total of 224 rules in 22 ms. Remains 40 /175 variables (removed 135) and now considering 44/210 (removed 166) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 40/175 places, 44/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 3 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 3 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 44 transitions.
Starting structural reductions in LTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 151 transition count 186
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 151 transition count 186
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 51 place count 151 transition count 183
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 60 place count 142 transition count 174
Iterating global reduction 1 with 9 rules applied. Total rules applied 69 place count 142 transition count 174
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 70 place count 142 transition count 173
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 74 place count 138 transition count 169
Iterating global reduction 2 with 4 rules applied. Total rules applied 78 place count 138 transition count 169
Applied a total of 78 rules in 13 ms. Remains 138 /175 variables (removed 37) and now considering 169/210 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 138/175 places, 169/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 169 transitions.
Starting structural reductions in LTL mode, iteration 0 : 175/175 places, 210/210 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 155 transition count 190
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 155 transition count 190
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 43 place count 155 transition count 187
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 49 place count 149 transition count 181
Iterating global reduction 1 with 6 rules applied. Total rules applied 55 place count 149 transition count 181
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 56 place count 149 transition count 180
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 60 place count 145 transition count 176
Iterating global reduction 2 with 4 rules applied. Total rules applied 64 place count 145 transition count 176
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 65 place count 144 transition count 175
Iterating global reduction 2 with 1 rules applied. Total rules applied 66 place count 144 transition count 175
Applied a total of 66 rules in 16 ms. Remains 144 /175 variables (removed 31) and now considering 175/210 (removed 35) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 144/175 places, 175/210 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:11:22] [INFO ] Input system was already deterministic with 175 transitions.
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 10 ms
[2023-03-19 05:11:22] [INFO ] Flatten gal took : 10 ms
[2023-03-19 05:11:22] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-19 05:11:22] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 175 places, 210 transitions and 496 arcs took 3 ms.
Total runtime 7961 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmartHome-PT-08
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/370
CTLFireability

FORMULA SmartHome-PT-08-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-08-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679202951177

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/370/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/370/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/370/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 4 (type EXCL) for 3 SmartHome-PT-08-CTLFireability-01
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/257 2/32 SmartHome-PT-08-CTLFireability-01 258302 m, 51660 m/sec, 2473908 t fired, .

Time elapsed: 5 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/257 3/32 SmartHome-PT-08-CTLFireability-01 490561 m, 46451 m/sec, 5072116 t fired, .

Time elapsed: 10 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/257 4/32 SmartHome-PT-08-CTLFireability-01 683657 m, 38619 m/sec, 7584433 t fired, .

Time elapsed: 15 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/257 5/32 SmartHome-PT-08-CTLFireability-01 919518 m, 47172 m/sec, 10195492 t fired, .

Time elapsed: 20 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/257 6/32 SmartHome-PT-08-CTLFireability-01 1134264 m, 42949 m/sec, 12963979 t fired, .

Time elapsed: 25 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/257 7/32 SmartHome-PT-08-CTLFireability-01 1369491 m, 47045 m/sec, 15738808 t fired, .

Time elapsed: 30 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/257 8/32 SmartHome-PT-08-CTLFireability-01 1605674 m, 47236 m/sec, 18223857 t fired, .

Time elapsed: 35 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/257 9/32 SmartHome-PT-08-CTLFireability-01 1791149 m, 37095 m/sec, 20609661 t fired, .

Time elapsed: 40 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/257 9/32 SmartHome-PT-08-CTLFireability-01 1963766 m, 34523 m/sec, 22969801 t fired, .

Time elapsed: 45 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 50/257 10/32 SmartHome-PT-08-CTLFireability-01 2159390 m, 39124 m/sec, 25465728 t fired, .

Time elapsed: 50 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 55/257 11/32 SmartHome-PT-08-CTLFireability-01 2323116 m, 32745 m/sec, 27894249 t fired, .

Time elapsed: 55 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 60/257 12/32 SmartHome-PT-08-CTLFireability-01 2481766 m, 31730 m/sec, 30337025 t fired, .

Time elapsed: 60 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 65/257 13/32 SmartHome-PT-08-CTLFireability-01 2688194 m, 41285 m/sec, 32797080 t fired, .

Time elapsed: 65 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 70/257 14/32 SmartHome-PT-08-CTLFireability-01 2867398 m, 35840 m/sec, 35352132 t fired, .

Time elapsed: 70 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 75/257 14/32 SmartHome-PT-08-CTLFireability-01 3030856 m, 32691 m/sec, 37699937 t fired, .

Time elapsed: 75 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 80/257 15/32 SmartHome-PT-08-CTLFireability-01 3164303 m, 26689 m/sec, 39983586 t fired, .

Time elapsed: 80 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 85/257 16/32 SmartHome-PT-08-CTLFireability-01 3302363 m, 27612 m/sec, 42201927 t fired, .

Time elapsed: 85 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 90/257 16/32 SmartHome-PT-08-CTLFireability-01 3444197 m, 28366 m/sec, 44604949 t fired, .

Time elapsed: 90 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 95/257 17/32 SmartHome-PT-08-CTLFireability-01 3719559 m, 55072 m/sec, 47058828 t fired, .

Time elapsed: 95 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 100/257 19/32 SmartHome-PT-08-CTLFireability-01 3977508 m, 51589 m/sec, 49652077 t fired, .

Time elapsed: 100 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 105/257 20/32 SmartHome-PT-08-CTLFireability-01 4191764 m, 42851 m/sec, 52212746 t fired, .

Time elapsed: 105 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 110/257 21/32 SmartHome-PT-08-CTLFireability-01 4402484 m, 42144 m/sec, 54608644 t fired, .

Time elapsed: 110 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 115/257 21/32 SmartHome-PT-08-CTLFireability-01 4567652 m, 33033 m/sec, 56937414 t fired, .

Time elapsed: 115 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 120/257 22/32 SmartHome-PT-08-CTLFireability-01 4744434 m, 35356 m/sec, 59333232 t fired, .

Time elapsed: 120 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 125/257 23/32 SmartHome-PT-08-CTLFireability-01 4919429 m, 34999 m/sec, 61656487 t fired, .

Time elapsed: 125 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 130/257 24/32 SmartHome-PT-08-CTLFireability-01 5059055 m, 27925 m/sec, 63959223 t fired, .

Time elapsed: 130 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 135/257 25/32 SmartHome-PT-08-CTLFireability-01 5435463 m, 75281 m/sec, 66255068 t fired, .

Time elapsed: 135 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 140/257 27/32 SmartHome-PT-08-CTLFireability-01 5743819 m, 61671 m/sec, 68640309 t fired, .

Time elapsed: 140 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 145/257 28/32 SmartHome-PT-08-CTLFireability-01 6011481 m, 53532 m/sec, 71000460 t fired, .

Time elapsed: 145 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 150/257 29/32 SmartHome-PT-08-CTLFireability-01 6277718 m, 53247 m/sec, 73285443 t fired, .

Time elapsed: 150 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 155/257 30/32 SmartHome-PT-08-CTLFireability-01 6501747 m, 44805 m/sec, 75526003 t fired, .

Time elapsed: 155 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 160/257 31/32 SmartHome-PT-08-CTLFireability-01 6675094 m, 34669 m/sec, 77719579 t fired, .

Time elapsed: 160 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 165/257 31/32 SmartHome-PT-08-CTLFireability-01 6814089 m, 27799 m/sec, 79910205 t fired, .

Time elapsed: 165 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 170/257 32/32 SmartHome-PT-08-CTLFireability-01 6944682 m, 26118 m/sec, 82190765 t fired, .

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 175/257 32/32 SmartHome-PT-08-CTLFireability-01 7061363 m, 23336 m/sec, 84469400 t fired, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 4 (type EXCL) for SmartHome-PT-08-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 40 (type EXCL) for 39 SmartHome-PT-08-CTLFireability-15
lola: time limit : 263 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for SmartHome-PT-08-CTLFireability-15
lola: result : false
lola: markings : 18
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 SmartHome-PT-08-CTLFireability-14
lola: time limit : 285 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for SmartHome-PT-08-CTLFireability-14
lola: result : false
lola: markings : 54
lola: fired transitions : 54
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 SmartHome-PT-08-CTLFireability-10
lola: time limit : 310 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for SmartHome-PT-08-CTLFireability-10
lola: result : false
lola: markings : 546
lola: fired transitions : 2343
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 SmartHome-PT-08-CTLFireability-09
lola: time limit : 342 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/342 2/32 SmartHome-PT-08-CTLFireability-09 417158 m, 83431 m/sec, 2186754 t fired, .

Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/342 4/32 SmartHome-PT-08-CTLFireability-09 830566 m, 82681 m/sec, 4454741 t fired, .

Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/342 6/32 SmartHome-PT-08-CTLFireability-09 1232974 m, 80481 m/sec, 6848466 t fired, .

Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/342 8/32 SmartHome-PT-08-CTLFireability-09 1662551 m, 85915 m/sec, 9177760 t fired, .

Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/342 10/32 SmartHome-PT-08-CTLFireability-09 2067885 m, 81066 m/sec, 11420195 t fired, .

Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 30/342 12/32 SmartHome-PT-08-CTLFireability-09 2437029 m, 73828 m/sec, 13724856 t fired, .

Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 35/342 14/32 SmartHome-PT-08-CTLFireability-09 2852016 m, 82997 m/sec, 16098814 t fired, .

Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 40/342 15/32 SmartHome-PT-08-CTLFireability-09 3233186 m, 76234 m/sec, 18508740 t fired, .

Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 45/342 17/32 SmartHome-PT-08-CTLFireability-09 3704681 m, 94299 m/sec, 20876429 t fired, .

Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 50/342 19/32 SmartHome-PT-08-CTLFireability-09 4140233 m, 87110 m/sec, 23202987 t fired, .

Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 55/342 21/32 SmartHome-PT-08-CTLFireability-09 4541035 m, 80160 m/sec, 25436214 t fired, .

Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 60/342 23/32 SmartHome-PT-08-CTLFireability-09 4906148 m, 73022 m/sec, 27693759 t fired, .

Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 65/342 25/32 SmartHome-PT-08-CTLFireability-09 5490770 m, 116924 m/sec, 29802188 t fired, .

Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 70/342 28/32 SmartHome-PT-08-CTLFireability-09 6087918 m, 119429 m/sec, 31634302 t fired, .

Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 75/342 30/32 SmartHome-PT-08-CTLFireability-09 6502923 m, 83001 m/sec, 33527456 t fired, .

Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 80/342 31/32 SmartHome-PT-08-CTLFireability-09 6826680 m, 64751 m/sec, 35567112 t fired, .

Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 28 (type EXCL) for SmartHome-PT-08-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 25 (type EXCL) for 24 SmartHome-PT-08-CTLFireability-08
lola: time limit : 370 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for SmartHome-PT-08-CTLFireability-08
lola: result : true
lola: markings : 736
lola: fired transitions : 1016
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 SmartHome-PT-08-CTLFireability-04
lola: time limit : 416 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for SmartHome-PT-08-CTLFireability-04
lola: result : true
lola: markings : 51361
lola: fired transitions : 227381
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 SmartHome-PT-08-CTLFireability-02
lola: time limit : 476 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for SmartHome-PT-08-CTLFireability-02
lola: result : true
lola: markings : 2898
lola: fired transitions : 4052
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 SmartHome-PT-08-CTLFireability-00
lola: time limit : 555 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for SmartHome-PT-08-CTLFireability-00
lola: result : false
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 SmartHome-PT-08-CTLFireability-06
lola: time limit : 666 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for SmartHome-PT-08-CTLFireability-06
lola: result : false
lola: markings : 3338
lola: fired transitions : 35016
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 SmartHome-PT-08-CTLFireability-05
lola: time limit : 833 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for SmartHome-PT-08-CTLFireability-05
lola: result : false
lola: markings : 725
lola: fired transitions : 2509
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 SmartHome-PT-08-CTLFireability-07
lola: time limit : 1111 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for SmartHome-PT-08-CTLFireability-07
lola: result : true
lola: markings : 283
lola: fired transitions : 517
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 SmartHome-PT-08-CTLFireability-03
lola: time limit : 1667 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for SmartHome-PT-08-CTLFireability-03
lola: result : false
lola: markings : 455
lola: fired transitions : 1468
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 SmartHome-PT-08-CTLFireability-11
lola: time limit : 3334 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for SmartHome-PT-08-CTLFireability-11
lola: result : true
lola: markings : 75734
lola: fired transitions : 292794
lola: time used : 1.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-08-CTLFireability-00: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-01: CTL unknown AGGR
SmartHome-PT-08-CTLFireability-02: CTL true CTL model checker
SmartHome-PT-08-CTLFireability-03: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-04: CTL true CTL model checker
SmartHome-PT-08-CTLFireability-05: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-06: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-07: CTL true CTL model checker
SmartHome-PT-08-CTLFireability-08: CTL true CTL model checker
SmartHome-PT-08-CTLFireability-09: CTL unknown AGGR
SmartHome-PT-08-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-11: CTL true CTL model checker
SmartHome-PT-08-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-08-CTLFireability-15: CTL false CTL model checker


Time elapsed: 267 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmartHome-PT-08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmartHome-PT-08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647100210"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmartHome-PT-08.tgz
mv SmartHome-PT-08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;