Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647000186.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmartHome-PT-05, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647000186
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 576K
-rw-r--r-- 1 mcc users 5.5K Feb 26 05:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 55K Feb 26 05:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 26 05:43 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 26 05:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 17:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 17:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 26 05:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 189K Feb 26 05:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.6K Feb 26 05:45 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Feb 26 05:45 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 54K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmartHome-PT-05-CTLFireability-00
FORMULA_NAME SmartHome-PT-05-CTLFireability-01
FORMULA_NAME SmartHome-PT-05-CTLFireability-02
FORMULA_NAME SmartHome-PT-05-CTLFireability-03
FORMULA_NAME SmartHome-PT-05-CTLFireability-04
FORMULA_NAME SmartHome-PT-05-CTLFireability-05
FORMULA_NAME SmartHome-PT-05-CTLFireability-06
FORMULA_NAME SmartHome-PT-05-CTLFireability-07
FORMULA_NAME SmartHome-PT-05-CTLFireability-08
FORMULA_NAME SmartHome-PT-05-CTLFireability-09
FORMULA_NAME SmartHome-PT-05-CTLFireability-10
FORMULA_NAME SmartHome-PT-05-CTLFireability-11
FORMULA_NAME SmartHome-PT-05-CTLFireability-12
FORMULA_NAME SmartHome-PT-05-CTLFireability-13
FORMULA_NAME SmartHome-PT-05-CTLFireability-14
FORMULA_NAME SmartHome-PT-05-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679201887449

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmartHome-PT-05
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 04:58:10] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 04:58:10] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 04:58:10] [INFO ] Load time of PNML (sax parser for PT used): 100 ms
[2023-03-19 04:58:10] [INFO ] Transformed 213 places.
[2023-03-19 04:58:10] [INFO ] Transformed 245 transitions.
[2023-03-19 04:58:10] [INFO ] Found NUPN structural information;
[2023-03-19 04:58:10] [INFO ] Parsed PT model containing 213 places and 245 transitions and 557 arcs in 218 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 20 ms.
Deduced a syphon composed of 17 places in 5 ms
Reduce places removed 17 places and 18 transitions.
Support contains 82 out of 196 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 196/196 places, 227/227 transitions.
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 30 place count 166 transition count 197
Iterating global reduction 0 with 30 rules applied. Total rules applied 60 place count 166 transition count 197
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 62 place count 166 transition count 195
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 64 place count 164 transition count 193
Iterating global reduction 1 with 2 rules applied. Total rules applied 66 place count 164 transition count 193
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 68 place count 162 transition count 191
Iterating global reduction 1 with 2 rules applied. Total rules applied 70 place count 162 transition count 191
Applied a total of 70 rules in 67 ms. Remains 162 /196 variables (removed 34) and now considering 191/227 (removed 36) transitions.
// Phase 1: matrix 191 rows 162 cols
[2023-03-19 04:58:10] [INFO ] Computed 10 place invariants in 26 ms
[2023-03-19 04:58:11] [INFO ] Implicit Places using invariants in 354 ms returned []
[2023-03-19 04:58:11] [INFO ] Invariant cache hit.
[2023-03-19 04:58:11] [INFO ] Implicit Places using invariants and state equation in 251 ms returned []
Implicit Place search using SMT with State Equation took 658 ms to find 0 implicit places.
[2023-03-19 04:58:11] [INFO ] Invariant cache hit.
[2023-03-19 04:58:11] [INFO ] Dead Transitions using invariants and state equation in 410 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 162/196 places, 191/227 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1141 ms. Remains : 162/196 places, 191/227 transitions.
Support contains 82 out of 162 places after structural reductions.
[2023-03-19 04:58:12] [INFO ] Flatten gal took : 89 ms
[2023-03-19 04:58:12] [INFO ] Flatten gal took : 31 ms
[2023-03-19 04:58:12] [INFO ] Input system was already deterministic with 191 transitions.
Support contains 77 out of 162 places (down from 82) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 71 resets, run finished after 976 ms. (steps per millisecond=10 ) properties (out of 68) seen :62
Incomplete Best-First random walk after 10001 steps, including 12 resets, run finished after 88 ms. (steps per millisecond=113 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10000 steps, including 10 resets, run finished after 58 ms. (steps per millisecond=172 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 10 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 12 resets, run finished after 82 ms. (steps per millisecond=121 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 10 resets, run finished after 119 ms. (steps per millisecond=84 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 10 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 3) seen :1
Running SMT prover for 2 properties.
[2023-03-19 04:58:13] [INFO ] Invariant cache hit.
[2023-03-19 04:58:14] [INFO ] [Real]Absence check using 10 positive place invariants in 6 ms returned sat
[2023-03-19 04:58:14] [INFO ] After 227ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:1
[2023-03-19 04:58:14] [INFO ] [Nat]Absence check using 10 positive place invariants in 6 ms returned sat
[2023-03-19 04:58:14] [INFO ] After 109ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :1
[2023-03-19 04:58:14] [INFO ] After 143ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :1
Attempting to minimize the solution found.
Minimization took 24 ms.
[2023-03-19 04:58:14] [INFO ] After 248ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :1
Fused 2 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 4 ms.
Support contains 2 out of 162 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 162/162 places, 191/191 transitions.
Graph (trivial) has 151 edges and 162 vertex of which 47 / 162 are part of one of the 4 SCC in 5 ms
Free SCC test removed 43 places
Drop transitions removed 59 transitions
Reduce isomorphic transitions removed 59 transitions.
Drop transitions removed 45 transitions
Trivial Post-agglo rules discarded 45 transitions
Performed 45 trivial Post agglomeration. Transition count delta: 45
Iterating post reduction 0 with 45 rules applied. Total rules applied 46 place count 119 transition count 87
Reduce places removed 45 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 54 rules applied. Total rules applied 100 place count 74 transition count 78
Reduce places removed 5 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 7 rules applied. Total rules applied 107 place count 69 transition count 76
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 2 rules applied. Total rules applied 109 place count 68 transition count 75
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 110 place count 67 transition count 75
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 6 Pre rules applied. Total rules applied 110 place count 67 transition count 69
Deduced a syphon composed of 6 places in 1 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 5 with 12 rules applied. Total rules applied 122 place count 61 transition count 69
Discarding 13 places :
Symmetric choice reduction at 5 with 13 rule applications. Total rules 135 place count 48 transition count 56
Iterating global reduction 5 with 13 rules applied. Total rules applied 148 place count 48 transition count 56
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 5 with 4 rules applied. Total rules applied 152 place count 48 transition count 52
Performed 21 Post agglomeration using F-continuation condition with reduction of 3 identical transitions.
Deduced a syphon composed of 21 places in 0 ms
Reduce places removed 21 places and 0 transitions.
Iterating global reduction 6 with 42 rules applied. Total rules applied 194 place count 27 transition count 28
Drop transitions removed 6 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 6 with 7 rules applied. Total rules applied 201 place count 27 transition count 21
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 7 with 2 rules applied. Total rules applied 203 place count 27 transition count 19
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 7 with 2 rules applied. Total rules applied 205 place count 25 transition count 19
Free-agglomeration rule applied 4 times.
Iterating global reduction 8 with 4 rules applied. Total rules applied 209 place count 25 transition count 15
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 8 with 4 rules applied. Total rules applied 213 place count 21 transition count 15
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 9 with 1 rules applied. Total rules applied 214 place count 20 transition count 14
Reduce places removed 4 places and 0 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 9 with 6 rules applied. Total rules applied 220 place count 16 transition count 12
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 10 with 2 rules applied. Total rules applied 222 place count 14 transition count 12
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 11 with 3 Pre rules applied. Total rules applied 222 place count 14 transition count 9
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 11 with 6 rules applied. Total rules applied 228 place count 11 transition count 9
Applied a total of 228 rules in 62 ms. Remains 11 /162 variables (removed 151) and now considering 9/191 (removed 182) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 62 ms. Remains : 11/162 places, 9/191 transitions.
Finished random walk after 60 steps, including 5 resets, run visited all 1 properties in 1 ms. (steps per millisecond=60 )
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 19 ms
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 27 ms
[2023-03-19 04:58:14] [INFO ] Input system was already deterministic with 191 transitions.
Support contains 75 out of 162 places (down from 76) after GAL structural reductions.
Computed a total of 24 stabilizing places and 24 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Graph (trivial) has 156 edges and 162 vertex of which 61 / 162 are part of one of the 5 SCC in 1 ms
Free SCC test removed 56 places
Ensure Unique test removed 71 transitions
Reduce isomorphic transitions removed 71 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 40 transitions
Trivial Post-agglo rules discarded 40 transitions
Performed 40 trivial Post agglomeration. Transition count delta: 40
Iterating post reduction 0 with 40 rules applied. Total rules applied 41 place count 105 transition count 79
Reduce places removed 40 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 51 rules applied. Total rules applied 92 place count 65 transition count 68
Reduce places removed 5 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 6 rules applied. Total rules applied 98 place count 60 transition count 67
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 99 place count 59 transition count 67
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 3 Pre rules applied. Total rules applied 99 place count 59 transition count 64
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 4 with 6 rules applied. Total rules applied 105 place count 56 transition count 64
Discarding 12 places :
Symmetric choice reduction at 4 with 12 rule applications. Total rules 117 place count 44 transition count 52
Iterating global reduction 4 with 12 rules applied. Total rules applied 129 place count 44 transition count 52
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 132 place count 44 transition count 49
Performed 15 Post agglomeration using F-continuation condition.Transition count delta: 15
Deduced a syphon composed of 15 places in 0 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 5 with 30 rules applied. Total rules applied 162 place count 29 transition count 34
Drop transitions removed 8 transitions
Redundant transition composition rules discarded 8 transitions
Iterating global reduction 5 with 8 rules applied. Total rules applied 170 place count 29 transition count 26
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 172 place count 27 transition count 26
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 174 place count 25 transition count 24
Applied a total of 174 rules in 31 ms. Remains 25 /162 variables (removed 137) and now considering 24/191 (removed 167) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 25/162 places, 24/191 transitions.
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:58:14] [INFO ] Input system was already deterministic with 24 transitions.
Finished random walk after 30 steps, including 4 resets, run visited all 1 properties in 2 ms. (steps per millisecond=15 )
FORMULA SmartHome-PT-05-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 25 place count 137 transition count 166
Iterating global reduction 0 with 25 rules applied. Total rules applied 50 place count 137 transition count 166
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 53 place count 137 transition count 163
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 63 place count 127 transition count 153
Iterating global reduction 1 with 10 rules applied. Total rules applied 73 place count 127 transition count 153
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 74 place count 127 transition count 152
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 83 place count 118 transition count 143
Iterating global reduction 2 with 9 rules applied. Total rules applied 92 place count 118 transition count 143
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 96 place count 114 transition count 139
Iterating global reduction 2 with 4 rules applied. Total rules applied 100 place count 114 transition count 139
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 101 place count 113 transition count 138
Iterating global reduction 2 with 1 rules applied. Total rules applied 102 place count 113 transition count 138
Applied a total of 102 rules in 39 ms. Remains 113 /162 variables (removed 49) and now considering 138/191 (removed 53) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 39 ms. Remains : 113/162 places, 138/191 transitions.
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 11 ms
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 12 ms
[2023-03-19 04:58:14] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 25 place count 137 transition count 166
Iterating global reduction 0 with 25 rules applied. Total rules applied 50 place count 137 transition count 166
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 53 place count 137 transition count 163
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 63 place count 127 transition count 153
Iterating global reduction 1 with 10 rules applied. Total rules applied 73 place count 127 transition count 153
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 74 place count 127 transition count 152
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 83 place count 118 transition count 143
Iterating global reduction 2 with 9 rules applied. Total rules applied 92 place count 118 transition count 143
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 95 place count 115 transition count 140
Iterating global reduction 2 with 3 rules applied. Total rules applied 98 place count 115 transition count 140
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 99 place count 114 transition count 139
Iterating global reduction 2 with 1 rules applied. Total rules applied 100 place count 114 transition count 139
Applied a total of 100 rules in 21 ms. Remains 114 /162 variables (removed 48) and now considering 139/191 (removed 52) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 114/162 places, 139/191 transitions.
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 11 ms
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 20 ms
[2023-03-19 04:58:14] [INFO ] Input system was already deterministic with 139 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Graph (trivial) has 146 edges and 162 vertex of which 51 / 162 are part of one of the 5 SCC in 0 ms
Free SCC test removed 46 places
Ensure Unique test removed 58 transitions
Reduce isomorphic transitions removed 58 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 43 transitions
Trivial Post-agglo rules discarded 43 transitions
Performed 43 trivial Post agglomeration. Transition count delta: 43
Iterating post reduction 0 with 43 rules applied. Total rules applied 44 place count 115 transition count 89
Reduce places removed 43 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 1 with 53 rules applied. Total rules applied 97 place count 72 transition count 79
Reduce places removed 4 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 6 rules applied. Total rules applied 103 place count 68 transition count 77
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 105 place count 66 transition count 77
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 4 Pre rules applied. Total rules applied 105 place count 66 transition count 73
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 4 with 8 rules applied. Total rules applied 113 place count 62 transition count 73
Discarding 10 places :
Symmetric choice reduction at 4 with 10 rule applications. Total rules 123 place count 52 transition count 63
Iterating global reduction 4 with 10 rules applied. Total rules applied 133 place count 52 transition count 63
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 136 place count 52 transition count 60
Performed 13 Post agglomeration using F-continuation condition.Transition count delta: 13
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 5 with 26 rules applied. Total rules applied 162 place count 39 transition count 47
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 5 with 6 rules applied. Total rules applied 168 place count 39 transition count 41
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 169 place count 38 transition count 41
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 6 with 1 rules applied. Total rules applied 170 place count 38 transition count 41
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 6 with 1 rules applied. Total rules applied 171 place count 38 transition count 40
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 173 place count 36 transition count 38
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 174 place count 35 transition count 38
Applied a total of 174 rules in 32 ms. Remains 35 /162 variables (removed 127) and now considering 38/191 (removed 153) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 33 ms. Remains : 35/162 places, 38/191 transitions.
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:58:14] [INFO ] Input system was already deterministic with 38 transitions.
Starting structural reductions in LTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 145 transition count 174
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 145 transition count 174
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 36 place count 145 transition count 172
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 42 place count 139 transition count 166
Iterating global reduction 1 with 6 rules applied. Total rules applied 48 place count 139 transition count 166
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 49 place count 139 transition count 165
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 53 place count 135 transition count 161
Iterating global reduction 2 with 4 rules applied. Total rules applied 57 place count 135 transition count 161
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 58 place count 134 transition count 160
Iterating global reduction 2 with 1 rules applied. Total rules applied 59 place count 134 transition count 160
Applied a total of 59 rules in 15 ms. Remains 134 /162 variables (removed 28) and now considering 160/191 (removed 31) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 134/162 places, 160/191 transitions.
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 12 ms
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 12 ms
[2023-03-19 04:58:14] [INFO ] Input system was already deterministic with 160 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Graph (trivial) has 140 edges and 162 vertex of which 34 / 162 are part of one of the 3 SCC in 1 ms
Free SCC test removed 31 places
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 50 transitions
Trivial Post-agglo rules discarded 50 transitions
Performed 50 trivial Post agglomeration. Transition count delta: 50
Iterating post reduction 0 with 50 rules applied. Total rules applied 51 place count 130 transition count 100
Reduce places removed 50 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 1 with 62 rules applied. Total rules applied 113 place count 80 transition count 88
Reduce places removed 7 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 9 rules applied. Total rules applied 122 place count 73 transition count 86
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 2 rules applied. Total rules applied 124 place count 72 transition count 85
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 125 place count 71 transition count 85
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 7 Pre rules applied. Total rules applied 125 place count 71 transition count 78
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 5 with 14 rules applied. Total rules applied 139 place count 64 transition count 78
Discarding 14 places :
Symmetric choice reduction at 5 with 14 rule applications. Total rules 153 place count 50 transition count 64
Iterating global reduction 5 with 14 rules applied. Total rules applied 167 place count 50 transition count 64
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 5 with 5 rules applied. Total rules applied 172 place count 50 transition count 59
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 2 rules applied. Total rules applied 174 place count 49 transition count 58
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: 14
Deduced a syphon composed of 14 places in 0 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 7 with 28 rules applied. Total rules applied 202 place count 35 transition count 44
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 7 with 3 rules applied. Total rules applied 205 place count 35 transition count 41
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 8 with 3 rules applied. Total rules applied 208 place count 34 transition count 39
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 9 with 2 rules applied. Total rules applied 210 place count 33 transition count 38
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 212 place count 32 transition count 37
Drop transitions removed 4 transitions
Redundant transition composition rules discarded 4 transitions
Iterating global reduction 10 with 4 rules applied. Total rules applied 216 place count 32 transition count 33
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 10 with 1 rules applied. Total rules applied 217 place count 31 transition count 32
Applied a total of 217 rules in 21 ms. Remains 31 /162 variables (removed 131) and now considering 32/191 (removed 159) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 21 ms. Remains : 31/162 places, 32/191 transitions.
[2023-03-19 04:58:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Graph (trivial) has 140 edges and 162 vertex of which 21 / 162 are part of one of the 4 SCC in 0 ms
Free SCC test removed 17 places
Ensure Unique test removed 23 transitions
Reduce isomorphic transitions removed 23 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 57 transitions
Trivial Post-agglo rules discarded 57 transitions
Performed 57 trivial Post agglomeration. Transition count delta: 57
Iterating post reduction 0 with 57 rules applied. Total rules applied 58 place count 144 transition count 110
Reduce places removed 57 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 1 with 70 rules applied. Total rules applied 128 place count 87 transition count 97
Reduce places removed 7 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 9 rules applied. Total rules applied 137 place count 80 transition count 95
Reduce places removed 1 places and 0 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Iterating post reduction 3 with 5 rules applied. Total rules applied 142 place count 79 transition count 91
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 4 with 6 rules applied. Total rules applied 148 place count 75 transition count 89
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 149 place count 74 transition count 89
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 6 Pre rules applied. Total rules applied 149 place count 74 transition count 83
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 6 with 12 rules applied. Total rules applied 161 place count 68 transition count 83
Discarding 11 places :
Symmetric choice reduction at 6 with 11 rule applications. Total rules 172 place count 57 transition count 72
Iterating global reduction 6 with 11 rules applied. Total rules applied 183 place count 57 transition count 72
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 6 with 3 rules applied. Total rules applied 186 place count 57 transition count 69
Performed 16 Post agglomeration using F-continuation condition.Transition count delta: 16
Deduced a syphon composed of 16 places in 0 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 7 with 32 rules applied. Total rules applied 218 place count 41 transition count 53
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 7 with 3 rules applied. Total rules applied 221 place count 41 transition count 50
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 8 with 3 rules applied. Total rules applied 224 place count 40 transition count 48
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 9 with 2 rules applied. Total rules applied 226 place count 39 transition count 47
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 10 with 5 rules applied. Total rules applied 231 place count 39 transition count 42
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 233 place count 37 transition count 40
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 10 with 2 rules applied. Total rules applied 235 place count 35 transition count 40
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 11 with 1 rules applied. Total rules applied 236 place count 35 transition count 39
Applied a total of 236 rules in 22 ms. Remains 35 /162 variables (removed 127) and now considering 39/191 (removed 152) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 35/162 places, 39/191 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 39 transitions.
Starting structural reductions in LTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 136 transition count 165
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 136 transition count 165
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 55 place count 136 transition count 162
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 64 place count 127 transition count 153
Iterating global reduction 1 with 9 rules applied. Total rules applied 73 place count 127 transition count 153
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 74 place count 127 transition count 152
Discarding 8 places :
Symmetric choice reduction at 2 with 8 rule applications. Total rules 82 place count 119 transition count 144
Iterating global reduction 2 with 8 rules applied. Total rules applied 90 place count 119 transition count 144
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 93 place count 116 transition count 141
Iterating global reduction 2 with 3 rules applied. Total rules applied 96 place count 116 transition count 141
Applied a total of 96 rules in 12 ms. Remains 116 /162 variables (removed 46) and now considering 141/191 (removed 50) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 116/162 places, 141/191 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 8 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 141 transitions.
Starting structural reductions in LTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Discarding 22 places :
Symmetric choice reduction at 0 with 22 rule applications. Total rules 22 place count 140 transition count 169
Iterating global reduction 0 with 22 rules applied. Total rules applied 44 place count 140 transition count 169
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 47 place count 140 transition count 166
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 53 place count 134 transition count 160
Iterating global reduction 1 with 6 rules applied. Total rules applied 59 place count 134 transition count 160
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 60 place count 134 transition count 159
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 64 place count 130 transition count 155
Iterating global reduction 2 with 4 rules applied. Total rules applied 68 place count 130 transition count 155
Applied a total of 68 rules in 9 ms. Remains 130 /162 variables (removed 32) and now considering 155/191 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 130/162 places, 155/191 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 14 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 8 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 155 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Graph (trivial) has 150 edges and 162 vertex of which 50 / 162 are part of one of the 5 SCC in 0 ms
Free SCC test removed 45 places
Ensure Unique test removed 57 transitions
Reduce isomorphic transitions removed 57 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 42 transitions
Trivial Post-agglo rules discarded 42 transitions
Performed 42 trivial Post agglomeration. Transition count delta: 42
Iterating post reduction 0 with 42 rules applied. Total rules applied 43 place count 116 transition count 91
Reduce places removed 42 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 1 with 51 rules applied. Total rules applied 94 place count 74 transition count 82
Reduce places removed 4 places and 0 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 2 with 7 rules applied. Total rules applied 101 place count 70 transition count 79
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 104 place count 67 transition count 79
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 4 Pre rules applied. Total rules applied 104 place count 67 transition count 75
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 4 with 8 rules applied. Total rules applied 112 place count 63 transition count 75
Discarding 11 places :
Symmetric choice reduction at 4 with 11 rule applications. Total rules 123 place count 52 transition count 64
Iterating global reduction 4 with 11 rules applied. Total rules applied 134 place count 52 transition count 64
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 137 place count 52 transition count 61
Performed 16 Post agglomeration using F-continuation condition.Transition count delta: 16
Deduced a syphon composed of 16 places in 0 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 5 with 32 rules applied. Total rules applied 169 place count 36 transition count 45
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 5 with 3 rules applied. Total rules applied 172 place count 36 transition count 42
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 173 place count 35 transition count 42
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 7 with 2 rules applied. Total rules applied 175 place count 34 transition count 41
Drop transitions removed 8 transitions
Redundant transition composition rules discarded 8 transitions
Iterating global reduction 7 with 8 rules applied. Total rules applied 183 place count 34 transition count 33
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 7 with 2 rules applied. Total rules applied 185 place count 32 transition count 33
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 187 place count 30 transition count 31
Applied a total of 187 rules in 14 ms. Remains 30 /162 variables (removed 132) and now considering 31/191 (removed 160) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 30/162 places, 31/191 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Graph (trivial) has 156 edges and 162 vertex of which 69 / 162 are part of one of the 5 SCC in 1 ms
Free SCC test removed 64 places
Ensure Unique test removed 81 transitions
Reduce isomorphic transitions removed 81 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 35 transitions
Trivial Post-agglo rules discarded 35 transitions
Performed 35 trivial Post agglomeration. Transition count delta: 35
Iterating post reduction 0 with 35 rules applied. Total rules applied 36 place count 97 transition count 74
Reduce places removed 35 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 1 with 42 rules applied. Total rules applied 78 place count 62 transition count 67
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 81 place count 59 transition count 67
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 4 Pre rules applied. Total rules applied 81 place count 59 transition count 63
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 89 place count 55 transition count 63
Discarding 11 places :
Symmetric choice reduction at 3 with 11 rule applications. Total rules 100 place count 44 transition count 52
Iterating global reduction 3 with 11 rules applied. Total rules applied 111 place count 44 transition count 52
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 114 place count 44 transition count 49
Performed 15 Post agglomeration using F-continuation condition.Transition count delta: 15
Deduced a syphon composed of 15 places in 0 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 4 with 30 rules applied. Total rules applied 144 place count 29 transition count 34
Drop transitions removed 7 transitions
Redundant transition composition rules discarded 7 transitions
Iterating global reduction 4 with 7 rules applied. Total rules applied 151 place count 29 transition count 27
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 152 place count 28 transition count 27
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 5 with 1 rules applied. Total rules applied 153 place count 28 transition count 27
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 5 with 1 rules applied. Total rules applied 154 place count 28 transition count 26
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 156 place count 26 transition count 24
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 157 place count 25 transition count 24
Applied a total of 157 rules in 13 ms. Remains 25 /162 variables (removed 137) and now considering 24/191 (removed 167) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 25/162 places, 24/191 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 24 transitions.
Starting structural reductions in LTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 25 place count 137 transition count 166
Iterating global reduction 0 with 25 rules applied. Total rules applied 50 place count 137 transition count 166
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 53 place count 137 transition count 163
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 63 place count 127 transition count 153
Iterating global reduction 1 with 10 rules applied. Total rules applied 73 place count 127 transition count 153
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 74 place count 127 transition count 152
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 83 place count 118 transition count 143
Iterating global reduction 2 with 9 rules applied. Total rules applied 92 place count 118 transition count 143
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 96 place count 114 transition count 139
Iterating global reduction 2 with 4 rules applied. Total rules applied 100 place count 114 transition count 139
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 101 place count 113 transition count 138
Iterating global reduction 2 with 1 rules applied. Total rules applied 102 place count 113 transition count 138
Applied a total of 102 rules in 12 ms. Remains 113 /162 variables (removed 49) and now considering 138/191 (removed 53) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 113/162 places, 138/191 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Discarding 22 places :
Symmetric choice reduction at 0 with 22 rule applications. Total rules 22 place count 140 transition count 169
Iterating global reduction 0 with 22 rules applied. Total rules applied 44 place count 140 transition count 169
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 47 place count 140 transition count 166
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 54 place count 133 transition count 159
Iterating global reduction 1 with 7 rules applied. Total rules applied 61 place count 133 transition count 159
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 62 place count 133 transition count 158
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 68 place count 127 transition count 152
Iterating global reduction 2 with 6 rules applied. Total rules applied 74 place count 127 transition count 152
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 75 place count 126 transition count 151
Iterating global reduction 2 with 1 rules applied. Total rules applied 76 place count 126 transition count 151
Applied a total of 76 rules in 11 ms. Remains 126 /162 variables (removed 36) and now considering 151/191 (removed 40) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 126/162 places, 151/191 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 151 transitions.
Starting structural reductions in LTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 136 transition count 165
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 136 transition count 165
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 55 place count 136 transition count 162
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 65 place count 126 transition count 152
Iterating global reduction 1 with 10 rules applied. Total rules applied 75 place count 126 transition count 152
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 76 place count 126 transition count 151
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 85 place count 117 transition count 142
Iterating global reduction 2 with 9 rules applied. Total rules applied 94 place count 117 transition count 142
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 97 place count 114 transition count 139
Iterating global reduction 2 with 3 rules applied. Total rules applied 100 place count 114 transition count 139
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 101 place count 113 transition count 138
Iterating global reduction 2 with 1 rules applied. Total rules applied 102 place count 113 transition count 138
Applied a total of 102 rules in 11 ms. Remains 113 /162 variables (removed 49) and now considering 138/191 (removed 53) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 113/162 places, 138/191 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 138 transition count 167
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 138 transition count 167
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 51 place count 138 transition count 164
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 60 place count 129 transition count 155
Iterating global reduction 1 with 9 rules applied. Total rules applied 69 place count 129 transition count 155
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 70 place count 129 transition count 154
Discarding 8 places :
Symmetric choice reduction at 2 with 8 rule applications. Total rules 78 place count 121 transition count 146
Iterating global reduction 2 with 8 rules applied. Total rules applied 86 place count 121 transition count 146
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 89 place count 118 transition count 143
Iterating global reduction 2 with 3 rules applied. Total rules applied 92 place count 118 transition count 143
Applied a total of 92 rules in 12 ms. Remains 118 /162 variables (removed 44) and now considering 143/191 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 118/162 places, 143/191 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 8 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 8 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 143 transitions.
Starting structural reductions in LTL mode, iteration 0 : 162/162 places, 191/191 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 136 transition count 165
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 136 transition count 165
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 55 place count 136 transition count 162
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 65 place count 126 transition count 152
Iterating global reduction 1 with 10 rules applied. Total rules applied 75 place count 126 transition count 152
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 76 place count 126 transition count 151
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 85 place count 117 transition count 142
Iterating global reduction 2 with 9 rules applied. Total rules applied 94 place count 117 transition count 142
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 98 place count 113 transition count 138
Iterating global reduction 2 with 4 rules applied. Total rules applied 102 place count 113 transition count 138
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 103 place count 112 transition count 137
Iterating global reduction 2 with 1 rules applied. Total rules applied 104 place count 112 transition count 137
Applied a total of 104 rules in 13 ms. Remains 112 /162 variables (removed 50) and now considering 137/191 (removed 54) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 112/162 places, 137/191 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 8 ms
[2023-03-19 04:58:15] [INFO ] Input system was already deterministic with 137 transitions.
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 11 ms
[2023-03-19 04:58:15] [INFO ] Flatten gal took : 12 ms
[2023-03-19 04:58:15] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-19 04:58:15] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 162 places, 191 transitions and 445 arcs took 2 ms.
Total runtime 5180 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmartHome-PT-05
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/369
CTLFireability

FORMULA SmartHome-PT-05-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-05-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-05-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-05-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-05-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-05-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-05-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-05-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-05-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-05-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679202322997

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/369/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/369/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/369/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type EXCL) for 24 SmartHome-PT-05-CTLFireability-09
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 49 (type FNDP) for 24 SmartHome-PT-05-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type EQUN) for 24 SmartHome-PT-05-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SRCH) for 24 SmartHome-PT-05-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 51 (type EXCL) for SmartHome-PT-05-CTLFireability-09
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 49 (type FNDP) for SmartHome-PT-05-CTLFireability-09 (obsolete)
lola: CANCELED task # 50 (type EQUN) for SmartHome-PT-05-CTLFireability-09 (obsolete)
lola: CANCELED task # 52 (type SRCH) for SmartHome-PT-05-CTLFireability-09 (obsolete)
lola: LAUNCH task # 40 (type EXCL) for 39 SmartHome-PT-05-CTLFireability-14
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type FNDP) for SmartHome-PT-05-CTLFireability-09
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 40 (type EXCL) for SmartHome-PT-05-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 52 (type SRCH) for SmartHome-PT-05-CTLFireability-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 SmartHome-PT-05-CTLFireability-12
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for SmartHome-PT-05-CTLFireability-12
lola: result : true
lola: markings : 179
lola: fired transitions : 211
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 SmartHome-PT-05-CTLFireability-11
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: try reading problem file /home/mcc/execution/369/CTLFireability-50.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 50 (type EQUN) for SmartHome-PT-05-CTLFireability-09
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-05-CTLFireability-09: EF true state space
SmartHome-PT-05-CTLFireability-12: CTL true CTL model checker
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SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/276 3/32 SmartHome-PT-05-CTLFireability-11 548768 m, 109753 m/sec, 2621848 t fired, .

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SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

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31 CTL EXCL 10/276 5/32 SmartHome-PT-05-CTLFireability-11 1020816 m, 94409 m/sec, 5368907 t fired, .

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SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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31 CTL EXCL 15/276 7/32 SmartHome-PT-05-CTLFireability-11 1493347 m, 94506 m/sec, 8113996 t fired, .

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SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

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31 CTL EXCL 20/276 9/32 SmartHome-PT-05-CTLFireability-11 1961354 m, 93601 m/sec, 10974473 t fired, .

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31 CTL EXCL 25/276 12/32 SmartHome-PT-05-CTLFireability-11 2553693 m, 118467 m/sec, 13935524 t fired, .

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31 CTL EXCL 30/276 14/32 SmartHome-PT-05-CTLFireability-11 3095061 m, 108273 m/sec, 16707020 t fired, .

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SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 35/276 16/32 SmartHome-PT-05-CTLFireability-11 3550799 m, 91147 m/sec, 19370523 t fired, .

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SmartHome-PT-05-CTLFireability-12: CTL true CTL model checker
SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 40/276 19/32 SmartHome-PT-05-CTLFireability-11 4037072 m, 97254 m/sec, 22027453 t fired, .

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SmartHome-PT-05-CTLFireability-12: CTL true CTL model checker
SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 45/276 21/32 SmartHome-PT-05-CTLFireability-11 4547027 m, 101991 m/sec, 24791955 t fired, .

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SmartHome-PT-05-CTLFireability-12: CTL true CTL model checker
SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 50/276 24/32 SmartHome-PT-05-CTLFireability-11 5186676 m, 127929 m/sec, 27422125 t fired, .

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SmartHome-PT-05-CTLFireability-12: CTL true CTL model checker
SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 55/276 27/32 SmartHome-PT-05-CTLFireability-11 5860574 m, 134779 m/sec, 29521824 t fired, .

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SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 60/276 29/32 SmartHome-PT-05-CTLFireability-11 6394767 m, 106838 m/sec, 31579998 t fired, .

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SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 65/276 31/32 SmartHome-PT-05-CTLFireability-11 6812301 m, 83506 m/sec, 33868750 t fired, .

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SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: FINISHED task # 47 (type EXCL) for SmartHome-PT-05-CTLFireability-15
lola: result : true
lola: markings : 1
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lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 42 SmartHome-PT-05-CTLFireability-15
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SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 5/320 3/32 SmartHome-PT-05-CTLFireability-15 605453 m, 121090 m/sec, 2926461 t fired, .

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SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 10/320 7/32 SmartHome-PT-05-CTLFireability-15 1320469 m, 143003 m/sec, 6037114 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 15/320 10/32 SmartHome-PT-05-CTLFireability-15 2038484 m, 143603 m/sec, 8924767 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 20/320 13/32 SmartHome-PT-05-CTLFireability-15 2696065 m, 131516 m/sec, 11664363 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

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45 CTL EXCL 25/320 16/32 SmartHome-PT-05-CTLFireability-15 3348792 m, 130545 m/sec, 14353905 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

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45 CTL EXCL 30/320 18/32 SmartHome-PT-05-CTLFireability-15 3881128 m, 106467 m/sec, 17049789 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

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45 CTL EXCL 35/320 20/32 SmartHome-PT-05-CTLFireability-15 4328362 m, 89446 m/sec, 19705972 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

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45 CTL EXCL 40/320 22/32 SmartHome-PT-05-CTLFireability-15 4737427 m, 81813 m/sec, 22232053 t fired, .

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SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 45/320 24/32 SmartHome-PT-05-CTLFireability-15 5126416 m, 77797 m/sec, 24964075 t fired, .

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SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker

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SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 50/320 26/32 SmartHome-PT-05-CTLFireability-15 5675566 m, 109830 m/sec, 27635785 t fired, .

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SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 55/320 29/32 SmartHome-PT-05-CTLFireability-15 6284817 m, 121850 m/sec, 30395398 t fired, .

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SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

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45 CTL EXCL 60/320 32/32 SmartHome-PT-05-CTLFireability-15 6994241 m, 141884 m/sec, 33184387 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: result : false
lola: markings : 76
lola: fired transitions : 190
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lola: memory pages used : 1
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lola: result : true
lola: markings : 3780
lola: fired transitions : 6123
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 SmartHome-PT-05-CTLFireability-07
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SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/433 3/32 SmartHome-PT-05-CTLFireability-07 572851 m, 114570 m/sec, 2451111 t fired, .

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SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/433 6/32 SmartHome-PT-05-CTLFireability-07 1245602 m, 134550 m/sec, 5122615 t fired, .

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SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 15/433 10/32 SmartHome-PT-05-CTLFireability-07 1922349 m, 135349 m/sec, 7374766 t fired, .

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SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 20/433 12/32 SmartHome-PT-05-CTLFireability-07 2453715 m, 106273 m/sec, 9611404 t fired, .

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SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 25/433 14/32 SmartHome-PT-05-CTLFireability-07 2860261 m, 81309 m/sec, 11830104 t fired, .

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SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 30/433 15/32 SmartHome-PT-05-CTLFireability-07 3102592 m, 48466 m/sec, 13859217 t fired, .

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SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 35/433 16/32 SmartHome-PT-05-CTLFireability-07 3339599 m, 47401 m/sec, 16144692 t fired, .

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SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 40/433 20/32 SmartHome-PT-05-CTLFireability-07 4054197 m, 142919 m/sec, 18624820 t fired, .

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SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 45/433 22/32 SmartHome-PT-05-CTLFireability-07 4613957 m, 111952 m/sec, 20735368 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 50/433 25/32 SmartHome-PT-05-CTLFireability-07 5111290 m, 99466 m/sec, 22942079 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 55/433 26/32 SmartHome-PT-05-CTLFireability-07 5421470 m, 62036 m/sec, 24984927 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 60/433 27/32 SmartHome-PT-05-CTLFireability-07 5630668 m, 41839 m/sec, 26974424 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 65/433 29/32 SmartHome-PT-05-CTLFireability-07 5956752 m, 65216 m/sec, 29332054 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 70/433 31/32 SmartHome-PT-05-CTLFireability-07 6376586 m, 83966 m/sec, 31489347 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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19 CTL EXCL 75/433 32/32 SmartHome-PT-05-CTLFireability-07 6722943 m, 69271 m/sec, 33165819 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
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SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 5/483 3/32 SmartHome-PT-05-CTLFireability-04 632053 m, 126410 m/sec, 2447082 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
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SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 10/483 6/32 SmartHome-PT-05-CTLFireability-04 1301783 m, 133946 m/sec, 5063824 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
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SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 15/483 9/32 SmartHome-PT-05-CTLFireability-04 1950568 m, 129757 m/sec, 7777767 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
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10 CTL EXCL 20/483 11/32 SmartHome-PT-05-CTLFireability-04 2304011 m, 70688 m/sec, 10450754 t fired, .

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10 CTL EXCL 25/483 11/32 SmartHome-PT-05-CTLFireability-04 2315578 m, 2313 m/sec, 12900941 t fired, .

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SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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10 CTL EXCL 30/483 11/32 SmartHome-PT-05-CTLFireability-04 2326449 m, 2174 m/sec, 15401079 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 55/483 11/32 SmartHome-PT-05-CTLFireability-04 2395801 m, 1937 m/sec, 26748143 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 60/483 11/32 SmartHome-PT-05-CTLFireability-04 2407369 m, 2313 m/sec, 29080852 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 65/483 11/32 SmartHome-PT-05-CTLFireability-04 2421921 m, 2910 m/sec, 31434982 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 70/483 11/32 SmartHome-PT-05-CTLFireability-04 2435641 m, 2744 m/sec, 33813760 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 75/483 11/32 SmartHome-PT-05-CTLFireability-04 2457531 m, 4378 m/sec, 36289154 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 80/483 14/32 SmartHome-PT-05-CTLFireability-04 3060890 m, 120671 m/sec, 39003641 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 85/483 18/32 SmartHome-PT-05-CTLFireability-04 3885149 m, 164851 m/sec, 41567417 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 90/483 22/32 SmartHome-PT-05-CTLFireability-04 4670262 m, 157022 m/sec, 43876042 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 95/483 25/32 SmartHome-PT-05-CTLFireability-04 5401513 m, 146250 m/sec, 46095005 t fired, .

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SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 100/483 28/32 SmartHome-PT-05-CTLFireability-04 6092894 m, 138276 m/sec, 48266522 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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10 CTL EXCL 105/483 31/32 SmartHome-PT-05-CTLFireability-04 6660468 m, 113514 m/sec, 50452562 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/654 2/32 SmartHome-PT-05-CTLFireability-01 383756 m, 76751 m/sec, 2564709 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/654 4/32 SmartHome-PT-05-CTLFireability-01 725033 m, 68255 m/sec, 5249731 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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1 CTL EXCL 15/654 5/32 SmartHome-PT-05-CTLFireability-01 1070395 m, 69072 m/sec, 7842411 t fired, .

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SmartHome-PT-05-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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1 CTL EXCL 20/654 7/32 SmartHome-PT-05-CTLFireability-01 1417110 m, 69343 m/sec, 10418390 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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1 CTL EXCL 30/654 10/32 SmartHome-PT-05-CTLFireability-01 2095196 m, 67752 m/sec, 15925030 t fired, .

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SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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1 CTL EXCL 35/654 12/32 SmartHome-PT-05-CTLFireability-01 2494987 m, 79958 m/sec, 18782384 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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1 CTL EXCL 45/654 15/32 SmartHome-PT-05-CTLFireability-01 3244273 m, 69540 m/sec, 24129387 t fired, .

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-15: CONJ 0 0 0 0 3 0 1 0

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SmartHome-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-05-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
SmartHome-PT-05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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lola: fired transitions : 91
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 SmartHome-PT-05-CTLFireability-05
lola: time limit : 1058 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for SmartHome-PT-05-CTLFireability-05
lola: result : true
lola: markings : 135
lola: fired transitions : 443
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 SmartHome-PT-05-CTLFireability-03
lola: time limit : 1587 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for SmartHome-PT-05-CTLFireability-03
lola: result : true
lola: markings : 7635
lola: fired transitions : 19050
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 SmartHome-PT-05-CTLFireability-06
lola: time limit : 3174 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for SmartHome-PT-05-CTLFireability-06
lola: result : false
lola: markings : 42074
lola: fired transitions : 403902
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-05-CTLFireability-01: CTL unknown AGGR
SmartHome-PT-05-CTLFireability-02: CTL true CTL model checker
SmartHome-PT-05-CTLFireability-03: CTL true CTL model checker
SmartHome-PT-05-CTLFireability-04: CTL unknown AGGR
SmartHome-PT-05-CTLFireability-05: CTL true CTL model checker
SmartHome-PT-05-CTLFireability-06: CTL false CTL model checker
SmartHome-PT-05-CTLFireability-07: CTL unknown AGGR
SmartHome-PT-05-CTLFireability-08: CTL true CTL model checker
SmartHome-PT-05-CTLFireability-09: EF true state space
SmartHome-PT-05-CTLFireability-10: AFAG false CTL model checker
SmartHome-PT-05-CTLFireability-11: CTL unknown AGGR
SmartHome-PT-05-CTLFireability-12: CTL true CTL model checker
SmartHome-PT-05-CTLFireability-13: CTL false CTL model checker
SmartHome-PT-05-CTLFireability-14: CTL true CTL model checker
SmartHome-PT-05-CTLFireability-15: CONJ unknown CONJ


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmartHome-PT-05"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmartHome-PT-05, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647000186"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmartHome-PT-05.tgz
mv SmartHome-PT-05 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;