Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647000177.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmartHome-PT-04, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647000177
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 476K
-rw-r--r-- 1 mcc users 6.2K Feb 26 05:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K Feb 26 05:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 05:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 26 05:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 17:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 17:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.8K Feb 26 05:43 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 92K Feb 26 05:43 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 05:43 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Feb 26 05:43 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 35K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmartHome-PT-04-CTLCardinality-00
FORMULA_NAME SmartHome-PT-04-CTLCardinality-01
FORMULA_NAME SmartHome-PT-04-CTLCardinality-02
FORMULA_NAME SmartHome-PT-04-CTLCardinality-03
FORMULA_NAME SmartHome-PT-04-CTLCardinality-04
FORMULA_NAME SmartHome-PT-04-CTLCardinality-05
FORMULA_NAME SmartHome-PT-04-CTLCardinality-06
FORMULA_NAME SmartHome-PT-04-CTLCardinality-07
FORMULA_NAME SmartHome-PT-04-CTLCardinality-08
FORMULA_NAME SmartHome-PT-04-CTLCardinality-09
FORMULA_NAME SmartHome-PT-04-CTLCardinality-10
FORMULA_NAME SmartHome-PT-04-CTLCardinality-11
FORMULA_NAME SmartHome-PT-04-CTLCardinality-12
FORMULA_NAME SmartHome-PT-04-CTLCardinality-13
FORMULA_NAME SmartHome-PT-04-CTLCardinality-14
FORMULA_NAME SmartHome-PT-04-CTLCardinality-15

=== Now, execution of the tool begins

BK_START 1679201771426

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmartHome-PT-04
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 04:56:14] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 04:56:14] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 04:56:15] [INFO ] Load time of PNML (sax parser for PT used): 101 ms
[2023-03-19 04:56:15] [INFO ] Transformed 139 places.
[2023-03-19 04:56:15] [INFO ] Transformed 159 transitions.
[2023-03-19 04:56:15] [INFO ] Found NUPN structural information;
[2023-03-19 04:56:15] [INFO ] Parsed PT model containing 139 places and 159 transitions and 361 arcs in 248 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 26 ms.
Initial state reduction rules removed 2 formulas.
Deduced a syphon composed of 17 places in 5 ms
Reduce places removed 17 places and 19 transitions.
FORMULA SmartHome-PT-04-CTLCardinality-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmartHome-PT-04-CTLCardinality-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmartHome-PT-04-CTLCardinality-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmartHome-PT-04-CTLCardinality-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmartHome-PT-04-CTLCardinality-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 46 out of 122 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 140/140 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 102 transition count 120
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 102 transition count 120
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 41 place count 102 transition count 119
Applied a total of 41 rules in 44 ms. Remains 102 /122 variables (removed 20) and now considering 119/140 (removed 21) transitions.
// Phase 1: matrix 119 rows 102 cols
[2023-03-19 04:56:15] [INFO ] Computed 7 place invariants in 16 ms
[2023-03-19 04:56:15] [INFO ] Implicit Places using invariants in 337 ms returned []
[2023-03-19 04:56:15] [INFO ] Invariant cache hit.
[2023-03-19 04:56:15] [INFO ] Implicit Places using invariants and state equation in 216 ms returned []
Implicit Place search using SMT with State Equation took 613 ms to find 0 implicit places.
[2023-03-19 04:56:15] [INFO ] Invariant cache hit.
[2023-03-19 04:56:16] [INFO ] Dead Transitions using invariants and state equation in 197 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 102/122 places, 119/140 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 868 ms. Remains : 102/122 places, 119/140 transitions.
Support contains 46 out of 102 places after structural reductions.
[2023-03-19 04:56:16] [INFO ] Flatten gal took : 65 ms
[2023-03-19 04:56:16] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA SmartHome-PT-04-CTLCardinality-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 04:56:16] [INFO ] Flatten gal took : 30 ms
[2023-03-19 04:56:16] [INFO ] Input system was already deterministic with 119 transitions.
Support contains 42 out of 102 places (down from 46) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 104 resets, run finished after 483 ms. (steps per millisecond=20 ) properties (out of 29) seen :28
Incomplete Best-First random walk after 10001 steps, including 23 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-19 04:56:17] [INFO ] Invariant cache hit.
[2023-03-19 04:56:17] [INFO ] After 89ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 04:56:17] [INFO ] [Nat]Absence check using 7 positive place invariants in 5 ms returned sat
[2023-03-19 04:56:17] [INFO ] After 118ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 04:56:17] [INFO ] Deduced a trap composed of 29 places in 99 ms of which 5 ms to minimize.
[2023-03-19 04:56:17] [INFO ] Deduced a trap composed of 28 places in 56 ms of which 1 ms to minimize.
[2023-03-19 04:56:17] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 200 ms
[2023-03-19 04:56:17] [INFO ] After 332ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 13 ms.
[2023-03-19 04:56:17] [INFO ] After 440ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 4 ms.
Support contains 2 out of 102 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 102/102 places, 119/119 transitions.
Graph (trivial) has 94 edges and 102 vertex of which 45 / 102 are part of one of the 3 SCC in 5 ms
Free SCC test removed 42 places
Drop transitions removed 56 transitions
Reduce isomorphic transitions removed 56 transitions.
Graph (complete) has 104 edges and 60 vertex of which 57 are kept as prefixes of interest. Removing 3 places using SCC suffix rule.1 ms
Discarding 3 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Drop transitions removed 18 transitions
Trivial Post-agglo rules discarded 18 transitions
Performed 18 trivial Post agglomeration. Transition count delta: 18
Iterating post reduction 0 with 21 rules applied. Total rules applied 23 place count 57 transition count 40
Reduce places removed 18 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 21 rules applied. Total rules applied 44 place count 39 transition count 37
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 2 rules applied. Total rules applied 46 place count 38 transition count 36
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 47 place count 37 transition count 36
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 4 Pre rules applied. Total rules applied 47 place count 37 transition count 32
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 4 with 8 rules applied. Total rules applied 55 place count 33 transition count 32
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 59 place count 29 transition count 28
Iterating global reduction 4 with 4 rules applied. Total rules applied 63 place count 29 transition count 28
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 65 place count 29 transition count 26
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 5 with 18 rules applied. Total rules applied 83 place count 20 transition count 17
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 84 place count 20 transition count 16
Free-agglomeration rule applied 3 times.
Iterating global reduction 6 with 3 rules applied. Total rules applied 87 place count 20 transition count 13
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 6 with 3 rules applied. Total rules applied 90 place count 17 transition count 13
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 7 with 1 rules applied. Total rules applied 91 place count 16 transition count 12
Reduce places removed 3 places and 0 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 7 with 5 rules applied. Total rules applied 96 place count 13 transition count 10
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 8 with 2 rules applied. Total rules applied 98 place count 11 transition count 10
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 9 with 3 Pre rules applied. Total rules applied 98 place count 11 transition count 7
Deduced a syphon composed of 3 places in 0 ms
Ensure Unique test removed 1 places
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 9 with 7 rules applied. Total rules applied 105 place count 7 transition count 7
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 9 with 1 Pre rules applied. Total rules applied 105 place count 7 transition count 6
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 107 place count 6 transition count 6
Free-agglomeration rule applied 1 times.
Iterating global reduction 9 with 1 rules applied. Total rules applied 108 place count 6 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 109 place count 5 transition count 5
Applied a total of 109 rules in 50 ms. Remains 5 /102 variables (removed 97) and now considering 5/119 (removed 114) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 50 ms. Remains : 5/102 places, 5/119 transitions.
Finished random walk after 14 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=14 )
[2023-03-19 04:56:17] [INFO ] Flatten gal took : 17 ms
[2023-03-19 04:56:17] [INFO ] Flatten gal took : 17 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 119 transitions.
Computed a total of 15 stabilizing places and 15 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 119/119 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 91 transition count 108
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 91 transition count 108
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 23 place count 91 transition count 107
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 26 place count 88 transition count 104
Iterating global reduction 1 with 3 rules applied. Total rules applied 29 place count 88 transition count 104
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 31 place count 86 transition count 102
Iterating global reduction 1 with 2 rules applied. Total rules applied 33 place count 86 transition count 102
Applied a total of 33 rules in 28 ms. Remains 86 /102 variables (removed 16) and now considering 102/119 (removed 17) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 86/102 places, 102/119 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 12 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 13 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 102 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 119/119 transitions.
Graph (trivial) has 97 edges and 102 vertex of which 45 / 102 are part of one of the 3 SCC in 1 ms
Free SCC test removed 42 places
Ensure Unique test removed 53 transitions
Reduce isomorphic transitions removed 53 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 20 transitions
Trivial Post-agglo rules discarded 20 transitions
Performed 20 trivial Post agglomeration. Transition count delta: 20
Iterating post reduction 0 with 20 rules applied. Total rules applied 21 place count 59 transition count 45
Reduce places removed 20 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 24 rules applied. Total rules applied 45 place count 39 transition count 41
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 47 place count 37 transition count 41
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 3 Pre rules applied. Total rules applied 47 place count 37 transition count 38
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 6 rules applied. Total rules applied 53 place count 34 transition count 38
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 59 place count 28 transition count 32
Iterating global reduction 3 with 6 rules applied. Total rules applied 65 place count 28 transition count 32
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 67 place count 28 transition count 30
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 4 with 14 rules applied. Total rules applied 81 place count 21 transition count 23
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 4 with 5 rules applied. Total rules applied 86 place count 21 transition count 18
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 88 place count 19 transition count 18
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 1 Pre rules applied. Total rules applied 88 place count 19 transition count 17
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 90 place count 18 transition count 17
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 5 with 1 rules applied. Total rules applied 91 place count 17 transition count 16
Applied a total of 91 rules in 25 ms. Remains 17 /102 variables (removed 85) and now considering 16/119 (removed 103) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 17/102 places, 16/119 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 119/119 transitions.
Graph (trivial) has 89 edges and 102 vertex of which 45 / 102 are part of one of the 3 SCC in 1 ms
Free SCC test removed 42 places
Ensure Unique test removed 53 transitions
Reduce isomorphic transitions removed 53 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 16 transitions
Trivial Post-agglo rules discarded 16 transitions
Performed 16 trivial Post agglomeration. Transition count delta: 16
Iterating post reduction 0 with 16 rules applied. Total rules applied 17 place count 59 transition count 49
Reduce places removed 16 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 1 with 20 rules applied. Total rules applied 37 place count 43 transition count 45
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 39 place count 41 transition count 45
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 5 Pre rules applied. Total rules applied 39 place count 41 transition count 40
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 10 rules applied. Total rules applied 49 place count 36 transition count 40
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 53 place count 32 transition count 36
Iterating global reduction 3 with 4 rules applied. Total rules applied 57 place count 32 transition count 36
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 59 place count 32 transition count 34
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 4 with 16 rules applied. Total rules applied 75 place count 24 transition count 26
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 4 with 3 rules applied. Total rules applied 78 place count 24 transition count 23
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 79 place count 23 transition count 23
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 5 with 1 rules applied. Total rules applied 80 place count 22 transition count 22
Applied a total of 80 rules in 23 ms. Remains 22 /102 variables (removed 80) and now considering 22/119 (removed 97) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 22/102 places, 22/119 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 119/119 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 91 transition count 108
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 91 transition count 108
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 24 place count 91 transition count 106
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 28 place count 87 transition count 102
Iterating global reduction 1 with 4 rules applied. Total rules applied 32 place count 87 transition count 102
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 34 place count 85 transition count 100
Iterating global reduction 1 with 2 rules applied. Total rules applied 36 place count 85 transition count 100
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 37 place count 84 transition count 99
Iterating global reduction 1 with 1 rules applied. Total rules applied 38 place count 84 transition count 99
Applied a total of 38 rules in 28 ms. Remains 84 /102 variables (removed 18) and now considering 99/119 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 84/102 places, 99/119 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 12 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 11 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 99 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 119/119 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 88 transition count 105
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 88 transition count 105
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 30 place count 88 transition count 103
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 35 place count 83 transition count 98
Iterating global reduction 1 with 5 rules applied. Total rules applied 40 place count 83 transition count 98
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 45 place count 78 transition count 93
Iterating global reduction 1 with 5 rules applied. Total rules applied 50 place count 78 transition count 93
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 51 place count 77 transition count 92
Iterating global reduction 1 with 1 rules applied. Total rules applied 52 place count 77 transition count 92
Applied a total of 52 rules in 15 ms. Remains 77 /102 variables (removed 25) and now considering 92/119 (removed 27) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 77/102 places, 92/119 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 9 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 10 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 92 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 119/119 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 87 transition count 104
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 87 transition count 104
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 32 place count 87 transition count 102
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 38 place count 81 transition count 96
Iterating global reduction 1 with 6 rules applied. Total rules applied 44 place count 81 transition count 96
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 49 place count 76 transition count 91
Iterating global reduction 1 with 5 rules applied. Total rules applied 54 place count 76 transition count 91
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 55 place count 75 transition count 90
Iterating global reduction 1 with 1 rules applied. Total rules applied 56 place count 75 transition count 90
Applied a total of 56 rules in 11 ms. Remains 75 /102 variables (removed 27) and now considering 90/119 (removed 29) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 75/102 places, 90/119 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 9 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 9 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 90 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 119/119 transitions.
Graph (trivial) has 92 edges and 102 vertex of which 37 / 102 are part of one of the 3 SCC in 1 ms
Free SCC test removed 34 places
Ensure Unique test removed 43 transitions
Reduce isomorphic transitions removed 43 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition count delta: 22
Iterating post reduction 0 with 22 rules applied. Total rules applied 23 place count 67 transition count 53
Reduce places removed 22 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 1 with 27 rules applied. Total rules applied 50 place count 45 transition count 48
Reduce places removed 3 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 5 rules applied. Total rules applied 55 place count 42 transition count 46
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 58 place count 40 transition count 45
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 4 Pre rules applied. Total rules applied 58 place count 40 transition count 41
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 4 with 8 rules applied. Total rules applied 66 place count 36 transition count 41
Discarding 5 places :
Symmetric choice reduction at 4 with 5 rule applications. Total rules 71 place count 31 transition count 36
Iterating global reduction 4 with 5 rules applied. Total rules applied 76 place count 31 transition count 36
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 78 place count 31 transition count 34
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 5 with 18 rules applied. Total rules applied 96 place count 22 transition count 25
Drop transitions removed 4 transitions
Redundant transition composition rules discarded 4 transitions
Iterating global reduction 5 with 4 rules applied. Total rules applied 100 place count 22 transition count 21
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 101 place count 21 transition count 21
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 103 place count 19 transition count 19
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 104 place count 18 transition count 19
Applied a total of 104 rules in 21 ms. Remains 18 /102 variables (removed 84) and now considering 19/119 (removed 100) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 18/102 places, 19/119 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 19 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 119/119 transitions.
Discarding 10 places :
Symmetric choice reduction at 0 with 10 rule applications. Total rules 10 place count 92 transition count 109
Iterating global reduction 0 with 10 rules applied. Total rules applied 20 place count 92 transition count 109
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 22 place count 92 transition count 107
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 26 place count 88 transition count 103
Iterating global reduction 1 with 4 rules applied. Total rules applied 30 place count 88 transition count 103
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 33 place count 85 transition count 100
Iterating global reduction 1 with 3 rules applied. Total rules applied 36 place count 85 transition count 100
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 37 place count 84 transition count 99
Iterating global reduction 1 with 1 rules applied. Total rules applied 38 place count 84 transition count 99
Applied a total of 38 rules in 10 ms. Remains 84 /102 variables (removed 18) and now considering 99/119 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 84/102 places, 99/119 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 9 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 8 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 99 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 119/119 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 87 transition count 104
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 87 transition count 104
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 32 place count 87 transition count 102
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 38 place count 81 transition count 96
Iterating global reduction 1 with 6 rules applied. Total rules applied 44 place count 81 transition count 96
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 49 place count 76 transition count 91
Iterating global reduction 1 with 5 rules applied. Total rules applied 54 place count 76 transition count 91
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 55 place count 75 transition count 90
Iterating global reduction 1 with 1 rules applied. Total rules applied 56 place count 75 transition count 90
Applied a total of 56 rules in 6 ms. Remains 75 /102 variables (removed 27) and now considering 90/119 (removed 29) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 75/102 places, 90/119 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 90 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 119/119 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 89 transition count 106
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 89 transition count 106
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 27 place count 89 transition count 105
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 31 place count 85 transition count 101
Iterating global reduction 1 with 4 rules applied. Total rules applied 35 place count 85 transition count 101
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 37 place count 83 transition count 99
Iterating global reduction 1 with 2 rules applied. Total rules applied 39 place count 83 transition count 99
Applied a total of 39 rules in 5 ms. Remains 83 /102 variables (removed 19) and now considering 99/119 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 83/102 places, 99/119 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:56:18] [INFO ] Input system was already deterministic with 99 transitions.
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:56:18] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:56:18] [INFO ] Export to MCC of 10 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 2 ms.
[2023-03-19 04:56:18] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 102 places, 119 transitions and 279 arcs took 1 ms.
Total runtime 3631 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmartHome-PT-04
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376

FORMULA SmartHome-PT-04-CTLCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679201801365

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 29 (type CNST) for 28 SmartHome-PT-04-CTLCardinality-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 29 (type CNST) for SmartHome-PT-04-CTLCardinality-12
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 4 (type EXCL) for 3 SmartHome-PT-04-CTLCardinality-04
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH INITIAL
lola: LAUNCH task # 20 (type CNST) for 15 SmartHome-PT-04-CTLCardinality-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 20 (type CNST) for SmartHome-PT-04-CTLCardinality-08
lola: result : true
lola: FINISHED task # 4 (type EXCL) for SmartHome-PT-04-CTLCardinality-04
lola: result : true
lola: markings : 82
lola: fired transitions : 287
lola: time used : 0.000000
lola: Created skeleton in 0.000000 secs.
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 SmartHome-PT-04-CTLCardinality-06
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 35 (type FNDP) for 25 SmartHome-PT-04-CTLCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 35 (type FNDP) for SmartHome-PT-04-CTLCardinality-11
lola: result : true
lola: fired transitions : 23
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 10 (type EXCL) for SmartHome-PT-04-CTLCardinality-06
lola: result : false
lola: markings : 6750
lola: fired transitions : 24245
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 SmartHome-PT-04-CTLCardinality-15
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for SmartHome-PT-04-CTLCardinality-15
lola: result : false
lola: markings : 12428
lola: fired transitions : 36658
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 SmartHome-PT-04-CTLCardinality-07
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for SmartHome-PT-04-CTLCardinality-07
lola: result : true
lola: markings : 380
lola: fired transitions : 1075
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 SmartHome-PT-04-CTLCardinality-03
lola: time limit : 1199 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-04-CTLCardinality-04: AGEF true tscc_search
SmartHome-PT-04-CTLCardinality-06: CTL false CTL model checker
SmartHome-PT-04-CTLCardinality-07: CTL true CTL model checker
SmartHome-PT-04-CTLCardinality-08: DISJ true preprocessing
SmartHome-PT-04-CTLCardinality-11: EF DL true findpath
SmartHome-PT-04-CTLCardinality-12: INITIAL false preprocessing
SmartHome-PT-04-CTLCardinality-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-04-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-04-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLCardinality-10: AGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/1199 2/32 SmartHome-PT-04-CTLCardinality-03 432123 m, 86424 m/sec, 3245394 t fired, .

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# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-04-CTLCardinality-04: AGEF true tscc_search
SmartHome-PT-04-CTLCardinality-06: CTL false CTL model checker
SmartHome-PT-04-CTLCardinality-07: CTL true CTL model checker
SmartHome-PT-04-CTLCardinality-08: DISJ true preprocessing
SmartHome-PT-04-CTLCardinality-11: EF DL true findpath
SmartHome-PT-04-CTLCardinality-12: INITIAL false preprocessing
SmartHome-PT-04-CTLCardinality-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-04-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-04-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLCardinality-10: AGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/1199 4/32 SmartHome-PT-04-CTLCardinality-03 868313 m, 87238 m/sec, 6540536 t fired, .

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SmartHome-PT-04-CTLCardinality-04: AGEF true tscc_search
SmartHome-PT-04-CTLCardinality-06: CTL false CTL model checker
SmartHome-PT-04-CTLCardinality-07: CTL true CTL model checker
SmartHome-PT-04-CTLCardinality-08: DISJ true preprocessing
SmartHome-PT-04-CTLCardinality-11: EF DL true findpath
SmartHome-PT-04-CTLCardinality-12: INITIAL false preprocessing
SmartHome-PT-04-CTLCardinality-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-04-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-04-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLCardinality-10: AGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/1199 6/32 SmartHome-PT-04-CTLCardinality-03 1305300 m, 87397 m/sec, 9956591 t fired, .

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# running tasks: 1 of 4 Visible: 10
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SmartHome-PT-04-CTLCardinality-04: AGEF true tscc_search
SmartHome-PT-04-CTLCardinality-06: CTL false CTL model checker
SmartHome-PT-04-CTLCardinality-07: CTL true CTL model checker
SmartHome-PT-04-CTLCardinality-08: DISJ true preprocessing
SmartHome-PT-04-CTLCardinality-11: EF DL true findpath
SmartHome-PT-04-CTLCardinality-12: INITIAL false preprocessing
SmartHome-PT-04-CTLCardinality-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-04-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-04-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLCardinality-10: AGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/1199 8/32 SmartHome-PT-04-CTLCardinality-03 1737496 m, 86439 m/sec, 13338195 t fired, .

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# running tasks: 1 of 4 Visible: 10
lola: FINISHED task # 1 (type EXCL) for SmartHome-PT-04-CTLCardinality-03
lola: result : false
lola: markings : 1866110
lola: fired transitions : 14277395
lola: time used : 21.000000
lola: memory pages used : 8
lola: LAUNCH task # 23 (type EXCL) for 22 SmartHome-PT-04-CTLCardinality-10
lola: time limit : 1789 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for SmartHome-PT-04-CTLCardinality-10
lola: result : true
lola: markings : 240
lola: fired transitions : 881
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 SmartHome-PT-04-CTLCardinality-05
lola: time limit : 3578 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for SmartHome-PT-04-CTLCardinality-05
lola: result : true
lola: markings : 26
lola: fired transitions : 71
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-04-CTLCardinality-03: CTL false CTL model checker
SmartHome-PT-04-CTLCardinality-04: AGEF true tscc_search
SmartHome-PT-04-CTLCardinality-05: CTL true CTL model checker
SmartHome-PT-04-CTLCardinality-06: CTL false CTL model checker
SmartHome-PT-04-CTLCardinality-07: CTL true CTL model checker
SmartHome-PT-04-CTLCardinality-08: DISJ true preprocessing
SmartHome-PT-04-CTLCardinality-10: AGEF true tscc_search
SmartHome-PT-04-CTLCardinality-11: EF DL true findpath
SmartHome-PT-04-CTLCardinality-12: INITIAL false preprocessing
SmartHome-PT-04-CTLCardinality-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmartHome-PT-04"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmartHome-PT-04, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647000177"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmartHome-PT-04.tgz
mv SmartHome-PT-04 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;