About the Execution of LoLa+red for SmallOperatingSystem-PT-MT4096DC2048
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6327.991 | 176734.00 | 161667.00 | 1189.90 | ??TF???TTFT?F??T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647000130.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT4096DC2048, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647000130
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 448K
-rw-r--r-- 1 mcc users 8.6K Feb 25 12:48 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K Feb 25 12:48 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 25 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 25 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 12:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 105K Feb 25 12:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.5K Feb 25 12:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 12:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679195955006
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT4096DC2048
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 03:19:17] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 03:19:17] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 03:19:17] [INFO ] Load time of PNML (sax parser for PT used): 26 ms
[2023-03-19 03:19:17] [INFO ] Transformed 9 places.
[2023-03-19 03:19:17] [INFO ] Transformed 8 transitions.
[2023-03-19 03:19:17] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 114 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 17 ms.
Initial state reduction rules removed 1 formulas.
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 12 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 03:19:17] [INFO ] Computed 4 place invariants in 5 ms
[2023-03-19 03:19:17] [INFO ] Implicit Places using invariants in 167 ms returned []
[2023-03-19 03:19:17] [INFO ] Invariant cache hit.
[2023-03-19 03:19:18] [INFO ] Implicit Places using invariants and state equation in 54 ms returned []
Implicit Place search using SMT with State Equation took 263 ms to find 0 implicit places.
[2023-03-19 03:19:18] [INFO ] Invariant cache hit.
[2023-03-19 03:19:18] [INFO ] Dead Transitions using invariants and state equation in 45 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 322 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 03:19:18] [INFO ] Flatten gal took : 19 ms
[2023-03-19 03:19:18] [INFO ] Flatten gal took : 7 ms
[2023-03-19 03:19:18] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10247 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=409 ) properties (out of 29) seen :16
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 13) seen :12
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-19 03:19:18] [INFO ] Invariant cache hit.
[2023-03-19 03:19:18] [INFO ] [Real]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-19 03:19:18] [INFO ] After 40ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 03:19:18] [INFO ] [Nat]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-19 03:19:18] [INFO ] After 13ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 03:19:18] [INFO ] After 26ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 8 ms.
[2023-03-19 03:19:18] [INFO ] After 103ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished Parikh walk after 16380 steps, including 0 resets, run visited all 1 properties in 175 ms. (steps per millisecond=93 )
Parikh walk visited 1 properties in 184 ms.
[2023-03-19 03:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 14 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 5 place count 5 transition count 6
Applied a total of 5 rules in 22 ms. Remains 5 /9 variables (removed 4) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 5/9 places, 6/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 11 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 2 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 4 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 3 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 6 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 5 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 4 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 6 transition count 7
Applied a total of 3 rules in 10 ms. Remains 6 /9 variables (removed 3) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 6/9 places, 7/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 17 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 12 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 0 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 9 ms
[2023-03-19 03:19:19] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:19:19] [INFO ] Flatten gal took : 7 ms
[2023-03-19 03:19:19] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 03:19:19] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 1 ms.
Total runtime 1939 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT4096DC2048
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679196131740
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 13 (type EXCL) for 12 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 51 (type FNDP) for 27 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type EQUN) for 27 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SRCH) for 27 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 54 (type SRCH) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 51 (type FNDP) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 (obsolete)
lola: CANCELED task # 52 (type EQUN) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 51 (type FNDP) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/373/CTLFireability-52.sara.
lola: FINISHED task # 52 (type EQUN) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/239 14/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04 3297357 m, 659471 m/sec, 7140744 t fired, .
Time elapsed: 6 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/239 28/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04 6731855 m, 686899 m/sec, 14580282 t fired, .
Time elapsed: 11 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 13 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 16 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 47 (type EXCL) for 46 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 39 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14
lola: result : false
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 39 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14
lola: time limit : 298 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 1 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/298 13/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14 3010680 m, 602136 m/sec, 9530562 t fired, .
Time elapsed: 21 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 1 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/298 24/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14 5738926 m, 545649 m/sec, 18168418 t fired, .
Time elapsed: 26 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 42 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 31 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 37 (type EXCL) for 36 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13
lola: time limit : 324 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/324 8/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13 1846862 m, 369372 m/sec, 8233850 t fired, .
Time elapsed: 36 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/324 14/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13 3432151 m, 317057 m/sec, 15327287 t fired, .
Time elapsed: 41 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/324 20/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13 4957534 m, 305076 m/sec, 22159362 t fired, .
Time elapsed: 46 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/324 27/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13 6500191 m, 308531 m/sec, 29070239 t fired, .
Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 37 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 31 (type EXCL) for 30 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10
lola: time limit : 354 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07
lola: time limit : 393 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05
lola: time limit : 443 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/443 6/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05 1305825 m, 261165 m/sec, 8346435 t fired, .
Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/443 11/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05 2506987 m, 240232 m/sec, 16075234 t fired, .
Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/443 15/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05 3683601 m, 235322 m/sec, 23656920 t fired, .
Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/443 20/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05 4819886 m, 227257 m/sec, 30985007 t fired, .
Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/443 24/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05 5938088 m, 223640 m/sec, 38199667 t fired, .
Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 30/443 29/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05 7125508 m, 237484 m/sec, 45866852 t fired, .
Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 16 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 10 (type EXCL) for 9 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03
lola: time limit : 501 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03
lola: result : false
lola: markings : 4112
lola: fired transitions : 4174
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00
lola: time limit : 584 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/584 7/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00 1602198 m, 320439 m/sec, 7105293 t fired, .
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/584 13/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00 3083904 m, 296341 m/sec, 13715319 t fired, .
Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/584 19/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00 4512812 m, 285781 m/sec, 20098784 t fired, .
Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/584 24/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00 5907730 m, 278983 m/sec, 26333232 t fired, .
Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/584 30/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00 7359787 m, 290411 m/sec, 32827110 t fired, .
Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 1 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 49 (type EXCL) for 3 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01
lola: time limit : 695 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 AGEF EXCL 5/695 11/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01 2996046 m, 599209 m/sec, 8382225 t fired, .
Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 AGEF EXCL 10/695 21/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01 5573616 m, 515514 m/sec, 15598017 t fired, .
Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 AGEF EXCL 15/695 30/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01 8059090 m, 497094 m/sec, 22557176 t fired, .
Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 49 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 7 (type EXCL) for 6 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02
lola: time limit : 864 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02
lola: result : true
lola: markings : 4097
lola: fired transitions : 6151
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08
lola: time limit : 1153 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08
lola: result : true
lola: markings : 3
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11
lola: time limit : 1729 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/1729 15/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11 3513333 m, 702666 m/sec, 7608251 t fired, .
Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/1729 30/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11 7086772 m, 714687 m/sec, 15349413 t fired, .
Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 34 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 19 (type EXCL) for 18 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06
lola: time limit : 3444 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/3444 17/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06 3890463 m, 778092 m/sec, 8425237 t fired, .
Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/3444 31/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06 7427947 m, 707496 m/sec, 16087848 t fired, .
Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 19 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: Portfolio finished: no open tasks 15
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: EFAG unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: AG false search / frozen tokens
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: LTL/CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: DISJ unknown DISJ
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
Time elapsed: 171 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT4096DC2048"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT4096DC2048, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647000130"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT4096DC2048.tgz
mv SmallOperatingSystem-PT-MT4096DC2048 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;