Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912646900122.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT4096DC1024, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912646900122
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 8.8K Feb 25 12:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 25 12:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Feb 25 12:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 25 12:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.5K Feb 25 12:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 25 12:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 25 12:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 97K Feb 25 12:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679194076322

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT4096DC1024
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 02:47:59] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 02:47:59] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 02:47:59] [INFO ] Load time of PNML (sax parser for PT used): 29 ms
[2023-03-19 02:47:59] [INFO ] Transformed 9 places.
[2023-03-19 02:47:59] [INFO ] Transformed 8 transitions.
[2023-03-19 02:47:59] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 134 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Initial state reduction rules removed 1 formulas.
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 13 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 02:48:00] [INFO ] Computed 4 place invariants in 7 ms
[2023-03-19 02:48:00] [INFO ] Implicit Places using invariants in 196 ms returned []
[2023-03-19 02:48:00] [INFO ] Invariant cache hit.
[2023-03-19 02:48:00] [INFO ] Implicit Places using invariants and state equation in 56 ms returned []
Implicit Place search using SMT with State Equation took 310 ms to find 0 implicit places.
[2023-03-19 02:48:00] [INFO ] Invariant cache hit.
[2023-03-19 02:48:00] [INFO ] Dead Transitions using invariants and state equation in 48 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 373 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 02:48:00] [INFO ] Flatten gal took : 28 ms
[2023-03-19 02:48:00] [INFO ] Flatten gal took : 10 ms
[2023-03-19 02:48:00] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10252 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=186 ) properties (out of 29) seen :8
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=22 ) properties (out of 21) seen :19
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-19 02:48:01] [INFO ] Invariant cache hit.
[2023-03-19 02:48:01] [INFO ] After 36ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 2 atomic propositions for a total of 15 simplifications.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 5 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 5 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 5 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 9 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 3 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 2 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 3 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 5 place count 6 transition count 6
Applied a total of 5 rules in 7 ms. Remains 6 /9 variables (removed 3) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 6/9 places, 6/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:48:01] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 4 ms
[2023-03-19 02:48:01] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:48:01] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 02:48:01] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 0 ms.
Total runtime 1650 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT4096DC1024
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679194283230

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:810
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/225 7/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01 1571153 m, 314230 m/sec, 7068701 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

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4 CTL EXCL 20/225 26/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01 6269772 m, 312689 m/sec, 28211775 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

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4 CTL EXCL 25/225 32/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01 7900686 m, 326182 m/sec, 35550387 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
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34 CTL EXCL 10/324 14/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 3299383 m, 336685 m/sec, 9076056 t fired, .

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22 CTL EXCL 50/354 30/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07 7334304 m, 140260 m/sec, 60145672 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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lola: FINISHED task # 19 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06
lola: result : true
lola: markings : 525826
lola: fired transitions : 542215
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 4/436 15/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05 3590498 m, 718099 m/sec, 7775145 t fired, .

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lola: result : true
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lola: time used : 0.000000
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 0/580 1/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 201352 m, 40270 m/sec, 859937 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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1 CTL EXCL 5/580 7/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 1504655 m, 260660 m/sec, 6466754 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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1 CTL EXCL 10/580 12/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 2820493 m, 263167 m/sec, 12181096 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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1 CTL EXCL 15/580 17/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 4092001 m, 254301 m/sec, 17693017 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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1 CTL EXCL 20/580 22/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 5320754 m, 245750 m/sec, 23014143 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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1 CTL EXCL 25/580 27/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 6499224 m, 235694 m/sec, 28113102 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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1 CTL EXCL 30/580 32/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 7694404 m, 239036 m/sec, 33281390 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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lola: result : true
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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13 CTL EXCL 5/1722 6/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 1420447 m, 284089 m/sec, 7787336 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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13 CTL EXCL 10/1722 12/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 2892623 m, 294435 m/sec, 15869133 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/1722 18/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 4304032 m, 282281 m/sec, 23619683 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

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13 CTL EXCL 20/1722 23/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 5672553 m, 273704 m/sec, 31135109 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/1722 29/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 7111721 m, 287833 m/sec, 39040061 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: time limit : 3415 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/3415 12/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08 2900741 m, 580148 m/sec, 7209250 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/3415 23/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08 5489082 m, 517668 m/sec, 13657382 t fired, .

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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT4096DC1024"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT4096DC1024, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912646900122"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT4096DC1024.tgz
mv SmallOperatingSystem-PT-MT4096DC1024 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;