Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912646900113.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT2048DC1024, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912646900113
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 8.9K Feb 25 12:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 78K Feb 25 12:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 25 12:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 25 12:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 12:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 99K Feb 25 12:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 12:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Feb 25 12:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-00
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-01
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-02
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-03
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-04
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-05
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-06
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-10
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-15

=== Now, execution of the tool begins

BK_START 1679193451190

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT2048DC1024
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 02:37:35] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 02:37:35] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 02:37:35] [INFO ] Load time of PNML (sax parser for PT used): 26 ms
[2023-03-19 02:37:35] [INFO ] Transformed 9 places.
[2023-03-19 02:37:35] [INFO ] Transformed 8 transitions.
[2023-03-19 02:37:35] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 139 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 21 ms.
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 13 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 02:37:35] [INFO ] Computed 4 place invariants in 4 ms
[2023-03-19 02:37:35] [INFO ] Implicit Places using invariants in 179 ms returned []
[2023-03-19 02:37:35] [INFO ] Invariant cache hit.
[2023-03-19 02:37:35] [INFO ] Implicit Places using invariants and state equation in 46 ms returned []
Implicit Place search using SMT with State Equation took 266 ms to find 0 implicit places.
[2023-03-19 02:37:35] [INFO ] Invariant cache hit.
[2023-03-19 02:37:35] [INFO ] Dead Transitions using invariants and state equation in 66 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 349 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 02:37:35] [INFO ] Flatten gal took : 29 ms
[2023-03-19 02:37:35] [INFO ] Flatten gal took : 10 ms
[2023-03-19 02:37:36] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10252 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=222 ) properties (out of 73) seen :40
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 96 ms. (steps per millisecond=10 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=14 ) properties (out of 33) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=19 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 86 ms. (steps per millisecond=11 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 63 ms. (steps per millisecond=15 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 32) seen :0
Running SMT prover for 32 properties.
[2023-03-19 02:37:37] [INFO ] Invariant cache hit.
[2023-03-19 02:37:37] [INFO ] [Real]Absence check using 4 positive place invariants in 1 ms returned sat
[2023-03-19 02:37:37] [INFO ] After 110ms SMT Verify possible using all constraints in real domain returned unsat :5 sat :0 real:27
[2023-03-19 02:37:37] [INFO ] [Nat]Absence check using 4 positive place invariants in 1 ms returned sat
[2023-03-19 02:37:37] [INFO ] After 37ms SMT Verify possible using state equation in natural domain returned unsat :19 sat :13
[2023-03-19 02:37:37] [INFO ] After 81ms SMT Verify possible using trap constraints in natural domain returned unsat :19 sat :13
Attempting to minimize the solution found.
Minimization took 30 ms.
[2023-03-19 02:37:37] [INFO ] After 242ms SMT Verify possible using all constraints in natural domain returned unsat :19 sat :13
Fused 32 Parikh solutions to 13 different solutions.
Finished Parikh walk after 7655 steps, including 0 resets, run visited all 1 properties in 11 ms. (steps per millisecond=695 )
Parikh walk visited 13 properties in 1728 ms.
Successfully simplified 19 atomic propositions for a total of 16 simplifications.
FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 02:37:39] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 5 ms
FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 3 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 5 place count 5 transition count 6
Applied a total of 5 rules in 8 ms. Remains 5 /9 variables (removed 4) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 5/9 places, 6/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 1025 steps, including 0 resets, run visited all 1 properties in 5 ms. (steps per millisecond=205 )
FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 8 transition count 6
Reduce places removed 3 places and 0 transitions.
Graph (trivial) has 3 edges and 5 vertex of which 2 / 5 are part of one of the 1 SCC in 2 ms
Free SCC test removed 1 places
Iterating post reduction 1 with 4 rules applied. Total rules applied 6 place count 4 transition count 6
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 7 place count 4 transition count 5
Applied a total of 7 rules in 5 ms. Remains 4 /9 variables (removed 5) and now considering 5/8 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 4/9 places, 5/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Applied a total of 0 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 0 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 0 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Input system was already deterministic with 7 transitions.
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:37:39] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:37:39] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 2 ms.
[2023-03-19 02:37:39] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 1 ms.
Total runtime 4422 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT2048DC1024
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679193616054

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 1 (type EXCL) for 0 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-01
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-01
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 17 (type EXCL) for 16 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:746
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-01: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-05: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08: AFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

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17 CTL EXCL 5/257 19/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07 4596520 m, 919304 m/sec, 7379554 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-05: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08: AFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
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lola: FINISHED task # 45 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-15
lola: result : true
lola: markings : 3
lola: fired transitions : 3
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lola: time limit : 299 sec
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-01: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-05: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08: AFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 1 0 1 0 0 0

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42 CTL EXCL 5/299 12/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14 2897268 m, 579453 m/sec, 9412078 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-05: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08: AFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-10: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/299 24/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14 5908709 m, 602288 m/sec, 19199312 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-05: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08: AFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-05: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

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39 CTL EXCL 5/325 5/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13 1041762 m, 208352 m/sec, 3455478 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

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39 CTL EXCL 10/325 9/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13 2106794 m, 213006 m/sec, 6992639 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-05: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

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39 CTL EXCL 15/325 13/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13 3148433 m, 208327 m/sec, 10448605 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

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39 CTL EXCL 20/325 17/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13 4196718 m, 209657 m/sec, 13924816 t fired, .

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39 CTL EXCL 30/325 26/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13 6274995 m, 206618 m/sec, 20812485 t fired, .

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39 CTL EXCL 35/325 30/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13 7299539 m, 204908 m/sec, 24207477 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

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20 CTL EXCL 4/1163 10/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08 2282442 m, 456488 m/sec, 5669935 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

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20 CTL EXCL 9/1163 21/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08 5190745 m, 581660 m/sec, 12914124 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL true CTL model checker
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

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36 CTL EXCL 5/1737 9/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12 2230003 m, 446000 m/sec, 7769045 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08: AFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12: DISJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

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36 CTL EXCL 10/1737 18/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12 4347534 m, 423506 m/sec, 15160410 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL true CTL model checker
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08: AFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12: DISJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

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36 CTL EXCL 15/1737 25/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12 6235406 m, 377574 m/sec, 21752816 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL true CTL model checker
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL true CTL model checker
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08: AFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/3455 17/32 SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-05 3963914 m, 792782 m/sec, 8584566 t fired, .

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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL true CTL model checker
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SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08: AFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-01: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-03: AGEFAG false tscc_search
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-05: DISJ unknown DISJ
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-07: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-08: AFAG unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-09: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-11: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-12: DISJ unknown DISJ
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-13: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-14: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLCardinality-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT2048DC1024"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT2048DC1024, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912646900113"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT2048DC1024.tgz
mv SmallOperatingSystem-PT-MT2048DC1024 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;