About the Execution of LoLa+red for SmallOperatingSystem-PT-MT1024DC0512
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1440.128 | 28821.00 | 92375.00 | 550.70 | TFTFFTTFFFFTFTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912646900103.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT1024DC0512, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912646900103
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 7.2K Feb 25 12:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K Feb 25 12:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 12:46 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 12:46 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 25 12:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 123K Feb 25 12:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Feb 25 12:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 25 12:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-15
=== Now, execution of the tool begins
BK_START 1679192767402
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT1024DC0512
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 02:26:10] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 02:26:10] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 02:26:11] [INFO ] Load time of PNML (sax parser for PT used): 43 ms
[2023-03-19 02:26:11] [INFO ] Transformed 9 places.
[2023-03-19 02:26:11] [INFO ] Transformed 8 transitions.
[2023-03-19 02:26:11] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 195 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityFireability.xml in 29 ms.
Working with output stream class java.io.PrintStream
Initial state reduction rules removed 4 formulas.
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10772 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=291 ) properties (out of 11) seen :9
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-15 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-09 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-08 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-06 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-04 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-01 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 76 ms. (steps per millisecond=131 ) properties (out of 2) seen :1
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11 TRUE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 02:26:11] [INFO ] Computed 4 place invariants in 5 ms
[2023-03-19 02:26:11] [INFO ] After 201ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-13 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
All properties solved without resorting to model-checking.
Total runtime 878 ms.
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT1024DC0512
BK_EXAMINATION: ReachabilityFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityFireability
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679192796223
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH INITIAL
lola: LAUNCH task # 40 (type CNST) for 39 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 66 (type EXCL) for 3 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-01
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 54 (type FNDP) for 9 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 9 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 40 (type CNST) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-13
lola: result : true
lola: LAUNCH task # 48 (type FNDP) for 0 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 54 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 56 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03 (obsolete)
lola: LAUNCH task # 79 (type FNDP) for 21 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 104 (type EQUN) for 21 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 66 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-01
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: result : true
lola: markings : 513
lola: fired transitions : 512
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 103 (type EXCL) for 15 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-05
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 79 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 104 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07 (obsolete)
lola: LAUNCH task # 120 (type FNDP) for 30 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 121 (type EQUN) for 30 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 120 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 103 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-05
lola: result : true
lola: markings : 513
lola: fired transitions : 512
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 121 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10 (obsolete)
lola: LAUNCH task # 85 (type EXCL) for 6 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-02
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 124 (type FNDP) for 36 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 125 (type EQUN) for 36 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 85 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-02
lola: result : true
lola: markings : 513
lola: fired transitions : 512
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 73 (type EXCL) for 12 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-04
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 48 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-00
lola: result : true
lola: fired transitions : 511
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 106 (type FNDP) for 42 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 73 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-04
lola: result : true
lola: markings : 513
lola: fired transitions : 512
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 133 (type EXCL) for 24 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-08
lola: time limit : 514 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-56.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-104.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-121.sara.
lola: FINISHED task # 133 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-08
lola: result : true
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 143 (type EXCL) for 45 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-15
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 143 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-15
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 111 (type EXCL) for 18 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-06
lola: time limit : 720 sec
lola: memory limit: 32 pages
lola: FINISHED task # 106 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 88 (type FNDP) for 27 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 111 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-06
lola: result : true
lola: markings : 513
lola: fired transitions : 512
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 98 (type EXCL) for 33 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11
lola: time limit : 1200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 88 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-09
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 94 (type FNDP) for 33 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 98 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11
lola: result : true
lola: markings : 6
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 94 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11 (obsolete)
lola: LAUNCH task # 135 (type EXCL) for 36 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 134 (type SRCH) for 36 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 94 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 104 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07
lola: result : true
lola: FINISHED task # 121 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10
lola: result : true
lola: CANCELED task # 134 (type SRCH) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-00: EF true findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-01: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-02: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-04: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-05: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-06: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-08: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-09: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-13: INITIAL true preprocessing
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-14: EF true findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12: EF 0 1 3 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
124 EF FNDP 5/1799 0/5 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 4800916 t fired, 5 attempts, .
125 EF STEQ 5/3599 0/5 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 sara not yet started (preprocessing).
135 EF EXCL 5/3600 7/32 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 1768005 m, 353601 m/sec, 2602819 t fired, .
Time elapsed: 5 secs. Pages in use: 10
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 139 (type SRCH) for 36 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 139 (type SRCH) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-125.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-00: EF true findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-01: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-02: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-04: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-05: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-06: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-08: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-09: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-13: INITIAL true preprocessing
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-14: EF true findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12: EF 0 0 3 0 2 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
124 EF FNDP 10/3600 0/5 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 11099943 t fired, 12 attempts, .
125 EF STEQ 10/3600 0/5 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 sara is running.
135 EF EXCL 10/3600 16/32 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 4264436 m, 499286 m/sec, 6116361 t fired, .
Time elapsed: 10 secs. Pages in use: 16
# running tasks: 3 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-00: EF true findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-01: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-02: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-04: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-05: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-06: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-08: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-09: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-13: INITIAL true preprocessing
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-14: EF true findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12: EF 0 0 3 0 2 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
124 EF FNDP 15/3600 0/5 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 17571652 t fired, 18 attempts, .
125 EF STEQ 15/3600 0/5 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 sara is running.
135 EF EXCL 15/3600 26/32 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 6905417 m, 528196 m/sec, 9810396 t fired, .
Time elapsed: 15 secs. Pages in use: 26
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 135 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 (memory limit exceeded)
lola: FINISHED task # 56 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-00: EF true findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-01: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-02: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-04: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-05: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-06: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-08: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-09: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-13: INITIAL true preprocessing
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-14: EF true findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12: EF 0 0 2 0 2 0 2 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
124 EF FNDP 20/3600 0/5 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 24233286 t fired, 25 attempts, .
125 EF STEQ 20/3600 0/5 SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 sara is running.
Time elapsed: 20 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: FINISHED task # 125 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12
lola: result : false
lola: CANCELED task # 124 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-00: EF true findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-01: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-02: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-03: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-04: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-05: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-06: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-07: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-08: AG false tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-09: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-10: AG false findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-11: EF true tandem / relaxed
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-12: EF false state equation
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-13: INITIAL true preprocessing
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-14: EF true findpath
SmallOperatingSystem-PT-MT1024DC0512-ReachabilityFireability-15: EF true tandem / relaxed
Time elapsed: 23 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT1024DC0512"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT1024DC0512, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912646900103"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT1024DC0512.tgz
mv SmallOperatingSystem-PT-MT1024DC0512 execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;