About the Execution of LoLa+red for SmallOperatingSystem-PT-MT1024DC0512
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
6655.376 | 220202.00 | 207500.00 | 1183.10 | TT??T?TT????T?F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912646900097.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT1024DC0512, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912646900097
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 7.2K Feb 25 12:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K Feb 25 12:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 12:46 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 12:46 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 25 12:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 123K Feb 25 12:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Feb 25 12:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 25 12:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-00
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-07
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-12
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-14
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15
=== Now, execution of the tool begins
BK_START 1679191862941
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT1024DC0512
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 02:11:06] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 02:11:06] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 02:11:07] [INFO ] Load time of PNML (sax parser for PT used): 41 ms
[2023-03-19 02:11:07] [INFO ] Transformed 9 places.
[2023-03-19 02:11:07] [INFO ] Transformed 8 transitions.
[2023-03-19 02:11:07] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 197 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 28 ms.
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 18 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 02:11:07] [INFO ] Computed 4 place invariants in 6 ms
[2023-03-19 02:11:07] [INFO ] Implicit Places using invariants in 225 ms returned []
[2023-03-19 02:11:07] [INFO ] Invariant cache hit.
[2023-03-19 02:11:07] [INFO ] Implicit Places using invariants and state equation in 55 ms returned []
Implicit Place search using SMT with State Equation took 338 ms to find 0 implicit places.
[2023-03-19 02:11:07] [INFO ] Invariant cache hit.
[2023-03-19 02:11:07] [INFO ] Dead Transitions using invariants and state equation in 52 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 410 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 02:11:07] [INFO ] Flatten gal took : 28 ms
[2023-03-19 02:11:07] [INFO ] Flatten gal took : 10 ms
[2023-03-19 02:11:07] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10262 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=146 ) properties (out of 68) seen :32
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 72 ms. (steps per millisecond=13 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=23 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=20 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=19 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 36) seen :0
Running SMT prover for 36 properties.
[2023-03-19 02:11:08] [INFO ] Invariant cache hit.
[2023-03-19 02:11:09] [INFO ] [Real]Absence check using 4 positive place invariants in 1 ms returned sat
[2023-03-19 02:11:09] [INFO ] After 22ms SMT Verify possible using state equation in real domain returned unsat :10 sat :1 real:25
[2023-03-19 02:11:09] [INFO ] After 29ms SMT Verify possible using trap constraints in real domain returned unsat :10 sat :0 real:26
[2023-03-19 02:11:09] [INFO ] After 170ms SMT Verify possible using all constraints in real domain returned unsat :10 sat :0 real:26
[2023-03-19 02:11:09] [INFO ] [Nat]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-19 02:11:09] [INFO ] After 50ms SMT Verify possible using state equation in natural domain returned unsat :20 sat :16
[2023-03-19 02:11:09] [INFO ] After 117ms SMT Verify possible using trap constraints in natural domain returned unsat :20 sat :16
Attempting to minimize the solution found.
Minimization took 58 ms.
[2023-03-19 02:11:09] [INFO ] After 351ms SMT Verify possible using all constraints in natural domain returned unsat :20 sat :16
Fused 36 Parikh solutions to 16 different solutions.
Finished Parikh walk after 3030 steps, including 0 resets, run visited all 1 properties in 6 ms. (steps per millisecond=505 )
Parikh walk visited 16 properties in 1475 ms.
Successfully simplified 20 atomic propositions for a total of 16 simplifications.
FORMULA SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 02:11:10] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-19 02:11:10] [INFO ] Flatten gal took : 6 ms
[2023-03-19 02:11:10] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 4 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 11 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 7 transitions.
Finished random walk after 9236 steps, including 2 resets, run visited all 1 properties in 6 ms. (steps per millisecond=1539 )
FORMULA SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 0 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 5 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 5 place count 5 transition count 6
Applied a total of 5 rules in 6 ms. Remains 5 /9 variables (removed 4) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 5/9 places, 6/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Applied a total of 0 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:11:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:11:11] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 3 ms.
[2023-03-19 02:11:11] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 0 ms.
Total runtime 4412 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT1024DC0512
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
FORMULA SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679192083143
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 48 (type EXCL) for 26 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:664
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type FNDP) for 9 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type EQUN) for 9 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 55 (type SRCH) for 9 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type SRCH) for SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04
lola: result : unknown
lola: markings : 5
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 52 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04
lola: result : true
lola: fired transitions : 354
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 53 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04 (obsolete)
lola: FINISHED task # 53 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 1 0 0 1 0 0 0
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48 EXEF EXCL 5/300 11/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08 3147109 m, 629421 m/sec, 8309028 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 1 0 0 1 0 0 0
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48 EXEF EXCL 10/300 21/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08 6427856 m, 656149 m/sec, 16994454 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 1 0 0 1 0 0 0
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48 EXEF EXCL 15/300 32/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08 9592070 m, 632842 m/sec, 25417173 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 1 0 0 1 0 0 0
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lola: time limit : 325 sec
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0
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46 CTL EXCL 5/325 6/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15 1489676 m, 297935 m/sec, 6676172 t fired, .
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46 CTL EXCL 10/325 13/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15 3005481 m, 303161 m/sec, 13480623 t fired, .
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46 CTL EXCL 15/325 19/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15 4587373 m, 316378 m/sec, 20585340 t fired, .
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46 CTL EXCL 20/325 25/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15 5993032 m, 281131 m/sec, 26899979 t fired, .
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46 CTL EXCL 25/325 31/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15 7601083 m, 321610 m/sec, 34123874 t fired, .
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38 CTL EXCL 15/355 17/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11 4213626 m, 266249 m/sec, 21894558 t fired, .
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38 CTL EXCL 25/355 28/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11 6833948 m, 262272 m/sec, 35792306 t fired, .
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33 CTL EXCL 10/391 23/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10 5731849 m, 556648 m/sec, 19553193 t fired, .
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lola: result : true
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21 CTL EXCL 20/500 28/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05 6892361 m, 337736 m/sec, 17154903 t fired, .
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lola: result : false
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 1 0 0 2 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 AGEF EXCL 10/696 17/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09 4477587 m, 436706 m/sec, 16933887 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 1 0 0 2 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 AGEF EXCL 15/696 25/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09 6612363 m, 426955 m/sec, 25156749 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 1 0 0 2 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 AGEF EXCL 20/696 32/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09 8712268 m, 419981 m/sec, 33316083 t fired, .
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lola: CANCELED task # 49 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 1 0 0 2 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 40 (type EXCL) for 35 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11
lola: time limit : 863 sec
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lola: FINISHED task # 40 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11
lola: result : true
lola: markings : 3
lola: fired transitions : 6
lola: time used : 0.000000
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lola: LAUNCH task # 43 (type EXCL) for 42 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13
lola: time limit : 1151 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 EU EXCL 5/1151 10/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13 2775392 m, 555078 m/sec, 6897081 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 EU EXCL 10/1151 19/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13 5574589 m, 559839 m/sec, 13870714 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 EU EXCL 15/1151 28/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13 8444884 m, 574059 m/sec, 21025534 t fired, .
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lola: CANCELED task # 43 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 7 (type EXCL) for 6 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03
lola: time limit : 1717 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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7 CTL EXCL 5/1717 12/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03 2958252 m, 591650 m/sec, 7352036 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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7 CTL EXCL 10/1717 24/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03 5893660 m, 587081 m/sec, 14665722 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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lola: LAUNCH task # 4 (type EXCL) for 3 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 5/3420 7/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02 1513340 m, 302668 m/sec, 5566612 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 10/3420 13/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02 3106479 m, 318627 m/sec, 11375388 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 15/3420 19/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02 4650372 m, 308778 m/sec, 16992468 t fired, .
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/3420 25/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02 6141016 m, 298128 m/sec, 22412089 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 25/3420 31/32 SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02 7680212 m, 307839 m/sec, 28002335 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-01: SP ECTL true LTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-02: CTL unknown AGGR
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-03: CTL unknown AGGR
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-04: DISJ true findpath
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-05: CTL unknown AGGR
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-08: AXAG unknown AGGR
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-09: EFAG unknown AGGR
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-10: CTL unknown AGGR
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-11: CONJ unknown CONJ
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-13: EU unknown AGGR
SmallOperatingSystem-PT-MT1024DC0512-CTLCardinality-15: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT1024DC0512"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT1024DC0512, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912646900097"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT1024DC0512.tgz
mv SmallOperatingSystem-PT-MT1024DC0512 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;