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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r455-smll-167912646900074
Last Updated
May 14, 2023

About the Execution of LoLa+red for SmallOperatingSystem-PT-MT0512DC0128

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
4351.275 132548.00 124974.00 1021.20 T?F??FF?FFTT?FFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912646900074.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT0512DC0128, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912646900074
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 640K
-rw-r--r-- 1 mcc users 9.1K Feb 25 12:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 25 12:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 25 12:42 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 25 12:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 23K Feb 25 12:43 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 213K Feb 25 12:43 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 25 12:43 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 110K Feb 25 12:43 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.2K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679185089265

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT0512DC0128
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 00:18:13] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 00:18:13] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 00:18:13] [INFO ] Load time of PNML (sax parser for PT used): 41 ms
[2023-03-19 00:18:13] [INFO ] Transformed 9 places.
[2023-03-19 00:18:13] [INFO ] Transformed 8 transitions.
[2023-03-19 00:18:13] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 185 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 27 ms.
Initial state reduction rules removed 2 formulas.
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 20 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 00:18:13] [INFO ] Computed 4 place invariants in 7 ms
[2023-03-19 00:18:13] [INFO ] Implicit Places using invariants in 242 ms returned []
[2023-03-19 00:18:13] [INFO ] Invariant cache hit.
[2023-03-19 00:18:13] [INFO ] Implicit Places using invariants and state equation in 76 ms returned []
Implicit Place search using SMT with State Equation took 377 ms to find 0 implicit places.
[2023-03-19 00:18:13] [INFO ] Invariant cache hit.
[2023-03-19 00:18:13] [INFO ] Dead Transitions using invariants and state equation in 49 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 448 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 28 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 10 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10182 steps, including 2 resets, run finished after 64 ms. (steps per millisecond=159 ) properties (out of 28) seen :27
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-19 00:18:14] [INFO ] Invariant cache hit.
[2023-03-19 00:18:14] [INFO ] After 39ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 14 simplifications.
[2023-03-19 00:18:14] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 6 ms
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 6 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 5 place count 6 transition count 6
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 6 transition count 6
Applied a total of 6 rules in 15 ms. Remains 6 /9 variables (removed 3) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 6/9 places, 6/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 3 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:18:14] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 4 ms
[2023-03-19 00:18:14] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:18:14] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-19 00:18:14] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 1 ms.
Total runtime 1847 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT0512DC0128
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679185221813

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 24 (type EXCL) for 23 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 60 (type FNDP) for 0 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type EQUN) for 0 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 63 (type SRCH) for 0 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 24 (type EXCL) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02
lola: result : false
lola: markings : 259
lola: fired transitions : 271
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 42 (type EXCL) for 41 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08
lola: time limit : 144 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type FNDP) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 61 (type EQUN) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01 (obsolete)
lola: CANCELED task # 63 (type SRCH) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 61 (type EQUN) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 64 (type FNDP) for 50 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11
lola: time limit : 32000000 sec
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lola: LAUNCH task # 65 (type EQUN) for 50 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11
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lola: LAUNCH task # 67 (type SRCH) for 50 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11
lola: time limit : 32000000 sec
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 42 (type EXCL) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08
lola: result : false
lola: markings : 257
lola: fired transitions : 899
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 64 (type FNDP) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11
lola: result : true
lola: fired transitions : 127
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 67 (type SRCH) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 65 (type EQUN) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:664
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
sara: try reading problem file /home/mcc/execution/375/CTLFireability-65.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 65 (type EQUN) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 5/276 8/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07 1846095 m, 369219 m/sec, 8229028 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 10/276 15/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07 3724987 m, 375778 m/sec, 16640102 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 15/276 23/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07 5671230 m, 389248 m/sec, 25355627 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 20/276 31/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07 7593895 m, 384533 m/sec, 33971411 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 57 (type EXCL) for 56 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14
lola: result : false
lola: markings : 255
lola: fired transitions : 509
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12
lola: time limit : 325 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 5/325 11/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12 2692711 m, 538542 m/sec, 6697444 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 10/325 20/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12 4852196 m, 431897 m/sec, 12084665 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 15/325 29/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12 7033094 m, 436179 m/sec, 17844035 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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lola: result : false
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 5/395 6/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04 1265989 m, 253197 m/sec, 7009931 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 10/395 11/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04 2539497 m, 254701 m/sec, 14042166 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 15/395 16/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04 3788419 m, 249784 m/sec, 20934514 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 20/395 21/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04 5006103 m, 243536 m/sec, 27652181 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 25/395 26/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04 6234807 m, 245740 m/sec, 34660035 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 30/395 30/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04 7462220 m, 245482 m/sec, 42047092 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 5/440 6/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03 1400218 m, 280043 m/sec, 9148287 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

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27 CTL EXCL 10/440 11/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03 2711474 m, 262251 m/sec, 17699033 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

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27 CTL EXCL 15/440 16/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03 3947340 m, 247173 m/sec, 25753923 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

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27 CTL EXCL 20/440 21/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03 5164698 m, 243471 m/sec, 33686741 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

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27 CTL EXCL 25/440 26/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03 6429159 m, 252892 m/sec, 42267379 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

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27 CTL EXCL 30/440 31/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03 7563456 m, 226859 m/sec, 50241311 t fired, .

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SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 4 0 0 8 0 0 3
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 11 (type EXCL) for 0 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
lola: time limit : 497 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
lola: result : true
lola: markings : 3
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 0 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
lola: time limit : 580 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 71 (type EXCL) for 0 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01
lola: time limit : 871 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 0 1 0 10 0 0 4
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 LTL EXCL 5/871 19/32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01 2785953 m, 557190 m/sec, 6923618 t fired, .

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lola: CANCELED task # 71 (type EXCL) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ 0 0 0 0 10 0 1 4
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 45 (type EXCL) for 44 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09
lola: time limit : 1158 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09
lola: result : false
lola: markings : 129
lola: fired transitions : 128
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 69 (type EXCL) for 32 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05
lola: time limit : 1737 sec
lola: memory limit: 32 pages
lola: FINISHED task # 69 (type EXCL) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05
lola: result : true
lola: markings : 132
lola: fired transitions : 133
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10
lola: time limit : 3475 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10
lola: result : true
lola: markings : 257
lola: fired transitions : 262
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 13

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-01: CONJ unknown CONJ
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-02: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-03: CTL unknown AGGR
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-05: AGAF false state space /EFEG
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-06: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-07: CTL unknown AGGR
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-10: CTL true CTL model checker
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-11: EF true findpath
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-12: CTL unknown AGGR
SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-14: CTL false CTL model checker


Time elapsed: 125 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT0512DC0128"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT0512DC0128, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912646900074"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT0512DC0128.tgz
mv SmallOperatingSystem-PT-MT0512DC0128 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;