fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r454-smll-167912646500506
Last Updated
May 14, 2023

About the Execution of LoLA for StigmergyCommit-PT-09a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5770.808 949802.00 984174.00 2572.40 TF?TF?TF???TFF?T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r454-smll-167912646500506.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is StigmergyCommit-PT-09a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r454-smll-167912646500506
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 51M
-rw-r--r-- 1 mcc users 6.6K Feb 26 10:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 71K Feb 26 10:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 26 10:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 26 10:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.5K Feb 26 11:02 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 85K Feb 26 11:02 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 11:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 92K Feb 26 11:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 51M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-00
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-01
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-02
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-03
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-04
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-05
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-06
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-07
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-08
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-09
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-10
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-11
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-12
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-13
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-14
FORMULA_NAME StigmergyCommit-PT-09a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679401264314

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=StigmergyCommit-PT-09a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT StigmergyCommit-PT-09a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA StigmergyCommit-PT-09a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-09a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-09a-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-09a-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-09a-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-09a-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-09a-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-09a-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-09a-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-09a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679402214116

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-09a-CTLFireability-04: CONJ false CTL model checker
StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
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StigmergyCommit-PT-09a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-09a-CTLFireability-15: CTL 1 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 1/234 1/32 StigmergyCommit-PT-09a-CTLFireability-03 277 m, 55 m/sec, 1079 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-09a-CTLFireability-03: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-04: CONJ false CTL model checker
StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-13: CTL false CTL model checker
StigmergyCommit-PT-09a-CTLFireability-15: CTL true CTL model checker

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StigmergyCommit-PT-09a-CTLFireability-05: DISJ 0 3 0 0 3 0 0 0
StigmergyCommit-PT-09a-CTLFireability-06: EF 0 1 1 0 3 0 0 0
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StigmergyCommit-PT-09a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 5/270 1/32 StigmergyCommit-PT-09a-CTLFireability-14 167567 m, 33513 m/sec, 903642 t fired, .
69 EF STEQ 0/3516 0/5 StigmergyCommit-PT-09a-CTLFireability-06 sara not yet started (preprocessing).

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sara: try reading problem file /home/mcc/execution/CTLFireability-74.sara.
sara: try reading problem file /home/mcc/execution/CTLFireability-79.sara.
sara: place or transition ordering is non-deterministic

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-09a-CTLFireability-03: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-04: CONJ false CTL model checker
StigmergyCommit-PT-09a-CTLFireability-06: EF true findpath
StigmergyCommit-PT-09a-CTLFireability-07: DISJ false DISJ
StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-12: AG false findpath
StigmergyCommit-PT-09a-CTLFireability-13: CTL false CTL model checker
StigmergyCommit-PT-09a-CTLFireability-15: CTL true CTL model checker

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 10/352 2/32 StigmergyCommit-PT-09a-CTLFireability-14 434208 m, 53328 m/sec, 2457375 t fired, .

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StigmergyCommit-PT-09a-CTLFireability-06: EF true findpath
StigmergyCommit-PT-09a-CTLFireability-07: DISJ false DISJ
StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-12: AG false findpath
StigmergyCommit-PT-09a-CTLFireability-13: CTL false CTL model checker
StigmergyCommit-PT-09a-CTLFireability-15: CTL true CTL model checker

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63 CTL EXCL 15/352 4/32 StigmergyCommit-PT-09a-CTLFireability-14 720558 m, 57270 m/sec, 4395542 t fired, .

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StigmergyCommit-PT-09a-CTLFireability-06: EF true findpath
StigmergyCommit-PT-09a-CTLFireability-07: DISJ false DISJ
StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-12: AG false findpath
StigmergyCommit-PT-09a-CTLFireability-13: CTL false CTL model checker
StigmergyCommit-PT-09a-CTLFireability-15: CTL true CTL model checker

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63 CTL EXCL 20/352 5/32 StigmergyCommit-PT-09a-CTLFireability-14 994837 m, 54855 m/sec, 6261686 t fired, .

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StigmergyCommit-PT-09a-CTLFireability-06: EF true findpath
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48 CTL EXCL 5/403 2/32 StigmergyCommit-PT-09a-CTLFireability-09 285161 m, 57032 m/sec, 1594948 t fired, .

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48 CTL EXCL 10/403 3/32 StigmergyCommit-PT-09a-CTLFireability-09 575439 m, 58055 m/sec, 3400103 t fired, .

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48 CTL EXCL 15/403 4/32 StigmergyCommit-PT-09a-CTLFireability-09 856698 m, 56251 m/sec, 5287766 t fired, .

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48 CTL EXCL 20/403 5/32 StigmergyCommit-PT-09a-CTLFireability-09 1137516 m, 56163 m/sec, 7151833 t fired, .

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StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
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StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-12: AG false findpath
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StigmergyCommit-PT-09a-CTLFireability-06: EF true findpath
StigmergyCommit-PT-09a-CTLFireability-07: DISJ false DISJ
StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-12: AG false findpath
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StigmergyCommit-PT-09a-CTLFireability-06: EF true findpath
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StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
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StigmergyCommit-PT-09a-CTLFireability-07: DISJ false DISJ
StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-12: AG false findpath
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StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-12: AG false findpath
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lola: result : false
lola: markings : 1023
lola: fired transitions : 5110
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lola: result : true
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-09a-CTLFireability-00: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-01: EG false state space / EG
StigmergyCommit-PT-09a-CTLFireability-02: CTL unknown AGGR
StigmergyCommit-PT-09a-CTLFireability-03: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-04: CONJ false CTL model checker
StigmergyCommit-PT-09a-CTLFireability-05: DISJ unknown DISJ
StigmergyCommit-PT-09a-CTLFireability-06: EF true findpath
StigmergyCommit-PT-09a-CTLFireability-07: DISJ false DISJ
StigmergyCommit-PT-09a-CTLFireability-08: CTL unknown AGGR
StigmergyCommit-PT-09a-CTLFireability-09: CTL unknown AGGR
StigmergyCommit-PT-09a-CTLFireability-10: CTL unknown AGGR
StigmergyCommit-PT-09a-CTLFireability-11: CTL true CTL model checker
StigmergyCommit-PT-09a-CTLFireability-12: AG false findpath
StigmergyCommit-PT-09a-CTLFireability-13: CTL false CTL model checker
StigmergyCommit-PT-09a-CTLFireability-14: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyCommit-PT-09a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is StigmergyCommit-PT-09a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r454-smll-167912646500506"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/StigmergyCommit-PT-09a.tgz
mv StigmergyCommit-PT-09a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;