fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r454-smll-167912646500474
Last Updated
May 14, 2023

About the Execution of LoLA for StigmergyCommit-PT-07a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3631.140 800308.00 803571.00 2342.20 FFTF?FTFTTFTFFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r454-smll-167912646500474.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is StigmergyCommit-PT-07a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r454-smll-167912646500474
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.9M
-rw-r--r-- 1 mcc users 5.4K Feb 26 11:00 CTLCardinality.txt
-rw-r--r-- 1 mcc users 53K Feb 26 11:00 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 26 10:59 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 26 10:59 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 26 11:01 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 164K Feb 26 11:01 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.0K Feb 26 11:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 26 11:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 5.4M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-00
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-01
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-02
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-03
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-04
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-05
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-06
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-07
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-08
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-09
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-10
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-11
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-12
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-13
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-14
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679379324832

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=StigmergyCommit-PT-07a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT StigmergyCommit-PT-07a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA StigmergyCommit-PT-07a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-07a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679380125140

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:207
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 13 (type EXCL) for 12 StigmergyCommit-PT-07a-CTLFireability-04
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 4/211 1/32 StigmergyCommit-PT-07a-CTLFireability-04 133708 m, 26741 m/sec, 2051489 t fired, .

Time elapsed: 9 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 9/211 2/32 StigmergyCommit-PT-07a-CTLFireability-04 331317 m, 39521 m/sec, 5204984 t fired, .

Time elapsed: 14 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 14/211 3/32 StigmergyCommit-PT-07a-CTLFireability-04 535834 m, 40903 m/sec, 8232932 t fired, .

Time elapsed: 19 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 19/211 4/32 StigmergyCommit-PT-07a-CTLFireability-04 777476 m, 48328 m/sec, 11026582 t fired, .

Time elapsed: 24 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 24/211 5/32 StigmergyCommit-PT-07a-CTLFireability-04 984912 m, 41487 m/sec, 13519999 t fired, .

Time elapsed: 29 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 29/211 6/32 StigmergyCommit-PT-07a-CTLFireability-04 1203935 m, 43804 m/sec, 16269330 t fired, .

Time elapsed: 34 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 34/211 7/32 StigmergyCommit-PT-07a-CTLFireability-04 1463553 m, 51923 m/sec, 19431368 t fired, .

Time elapsed: 39 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 39/211 8/32 StigmergyCommit-PT-07a-CTLFireability-04 1676316 m, 42552 m/sec, 22074706 t fired, .

Time elapsed: 44 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 44/211 9/32 StigmergyCommit-PT-07a-CTLFireability-04 1896909 m, 44118 m/sec, 24843943 t fired, .

Time elapsed: 49 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 49/211 10/32 StigmergyCommit-PT-07a-CTLFireability-04 2136988 m, 48015 m/sec, 27801888 t fired, .

Time elapsed: 54 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 54/211 11/32 StigmergyCommit-PT-07a-CTLFireability-04 2373480 m, 47298 m/sec, 30720145 t fired, .

Time elapsed: 59 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 59/211 12/32 StigmergyCommit-PT-07a-CTLFireability-04 2586984 m, 42700 m/sec, 33386772 t fired, .

Time elapsed: 64 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 64/211 13/32 StigmergyCommit-PT-07a-CTLFireability-04 2818802 m, 46363 m/sec, 36251372 t fired, .

Time elapsed: 69 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 69/211 14/32 StigmergyCommit-PT-07a-CTLFireability-04 3056671 m, 47573 m/sec, 39164409 t fired, .

Time elapsed: 74 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 74/211 15/32 StigmergyCommit-PT-07a-CTLFireability-04 3289131 m, 46492 m/sec, 42084144 t fired, .

Time elapsed: 79 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 79/211 16/32 StigmergyCommit-PT-07a-CTLFireability-04 3518874 m, 45948 m/sec, 44903783 t fired, .

Time elapsed: 84 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 84/211 17/32 StigmergyCommit-PT-07a-CTLFireability-04 3753026 m, 46830 m/sec, 47837515 t fired, .

Time elapsed: 89 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 89/211 18/32 StigmergyCommit-PT-07a-CTLFireability-04 3982255 m, 45845 m/sec, 50646064 t fired, .

Time elapsed: 94 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 94/211 19/32 StigmergyCommit-PT-07a-CTLFireability-04 4202923 m, 44133 m/sec, 53414192 t fired, .

Time elapsed: 99 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 99/211 19/32 StigmergyCommit-PT-07a-CTLFireability-04 4418499 m, 43115 m/sec, 56118548 t fired, .

Time elapsed: 104 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 104/211 20/32 StigmergyCommit-PT-07a-CTLFireability-04 4642889 m, 44878 m/sec, 58877041 t fired, .

Time elapsed: 109 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 109/211 21/32 StigmergyCommit-PT-07a-CTLFireability-04 4860379 m, 43498 m/sec, 61600148 t fired, .

Time elapsed: 114 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 114/211 22/32 StigmergyCommit-PT-07a-CTLFireability-04 5075935 m, 43111 m/sec, 64306618 t fired, .

Time elapsed: 119 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 119/211 23/32 StigmergyCommit-PT-07a-CTLFireability-04 5306883 m, 46189 m/sec, 67146801 t fired, .

Time elapsed: 124 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 124/211 24/32 StigmergyCommit-PT-07a-CTLFireability-04 5538141 m, 46251 m/sec, 70043713 t fired, .

Time elapsed: 129 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 129/211 25/32 StigmergyCommit-PT-07a-CTLFireability-04 5768382 m, 46048 m/sec, 72935774 t fired, .

Time elapsed: 134 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 134/211 26/32 StigmergyCommit-PT-07a-CTLFireability-04 5986540 m, 43631 m/sec, 75605694 t fired, .

Time elapsed: 139 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 139/211 27/32 StigmergyCommit-PT-07a-CTLFireability-04 6231580 m, 49008 m/sec, 78685482 t fired, .

Time elapsed: 144 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 144/211 28/32 StigmergyCommit-PT-07a-CTLFireability-04 6471100 m, 47904 m/sec, 81690959 t fired, .

Time elapsed: 149 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 149/211 29/32 StigmergyCommit-PT-07a-CTLFireability-04 6701030 m, 45986 m/sec, 84580849 t fired, .

Time elapsed: 154 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 154/211 30/32 StigmergyCommit-PT-07a-CTLFireability-04 6947837 m, 49361 m/sec, 87617313 t fired, .

Time elapsed: 159 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 159/211 31/32 StigmergyCommit-PT-07a-CTLFireability-04 7191611 m, 48754 m/sec, 90667925 t fired, .

Time elapsed: 164 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 164/211 32/32 StigmergyCommit-PT-07a-CTLFireability-04 7430389 m, 47755 m/sec, 93649297 t fired, .

Time elapsed: 169 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 174 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 50 (type EXCL) for 49 StigmergyCommit-PT-07a-CTLFireability-15
lola: time limit : 214 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 5/214 1/32 StigmergyCommit-PT-07a-CTLFireability-15 223486 m, 44697 m/sec, 1506173 t fired, .

Time elapsed: 179 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 10/214 2/32 StigmergyCommit-PT-07a-CTLFireability-15 441069 m, 43516 m/sec, 3043382 t fired, .

Time elapsed: 184 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 15/214 3/32 StigmergyCommit-PT-07a-CTLFireability-15 583651 m, 28516 m/sec, 4187984 t fired, .

Time elapsed: 189 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 20/214 4/32 StigmergyCommit-PT-07a-CTLFireability-15 765468 m, 36363 m/sec, 5631368 t fired, .

Time elapsed: 194 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 25/214 5/32 StigmergyCommit-PT-07a-CTLFireability-15 970550 m, 41016 m/sec, 7239909 t fired, .

Time elapsed: 199 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 30/214 6/32 StigmergyCommit-PT-07a-CTLFireability-15 1198745 m, 45639 m/sec, 9009311 t fired, .

Time elapsed: 204 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 35/214 6/32 StigmergyCommit-PT-07a-CTLFireability-15 1392790 m, 38809 m/sec, 10570680 t fired, .

Time elapsed: 209 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 40/214 7/32 StigmergyCommit-PT-07a-CTLFireability-15 1606407 m, 42723 m/sec, 12231724 t fired, .

Time elapsed: 214 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 45/214 8/32 StigmergyCommit-PT-07a-CTLFireability-15 1828920 m, 44502 m/sec, 14015710 t fired, .

Time elapsed: 219 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 50/214 9/32 StigmergyCommit-PT-07a-CTLFireability-15 2040560 m, 42328 m/sec, 15660432 t fired, .

Time elapsed: 224 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 55/214 10/32 StigmergyCommit-PT-07a-CTLFireability-15 2268381 m, 45564 m/sec, 17461365 t fired, .

Time elapsed: 229 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 60/214 11/32 StigmergyCommit-PT-07a-CTLFireability-15 2449657 m, 36255 m/sec, 18893107 t fired, .

Time elapsed: 234 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 65/214 12/32 StigmergyCommit-PT-07a-CTLFireability-15 2657347 m, 41538 m/sec, 20492967 t fired, .

Time elapsed: 239 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 70/214 13/32 StigmergyCommit-PT-07a-CTLFireability-15 2883470 m, 45224 m/sec, 22318196 t fired, .

Time elapsed: 244 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 75/214 14/32 StigmergyCommit-PT-07a-CTLFireability-15 3096657 m, 42637 m/sec, 23964571 t fired, .

Time elapsed: 249 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 80/214 15/32 StigmergyCommit-PT-07a-CTLFireability-15 3327885 m, 46245 m/sec, 25824533 t fired, .

Time elapsed: 254 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 85/214 16/32 StigmergyCommit-PT-07a-CTLFireability-15 3531481 m, 40719 m/sec, 27400348 t fired, .

Time elapsed: 259 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 90/214 16/32 StigmergyCommit-PT-07a-CTLFireability-15 3742705 m, 42244 m/sec, 29099558 t fired, .

Time elapsed: 264 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 95/214 17/32 StigmergyCommit-PT-07a-CTLFireability-15 3954768 m, 42412 m/sec, 30801999 t fired, .

Time elapsed: 269 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 100/214 18/32 StigmergyCommit-PT-07a-CTLFireability-15 4159916 m, 41029 m/sec, 32392228 t fired, .

Time elapsed: 274 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 105/214 19/32 StigmergyCommit-PT-07a-CTLFireability-15 4380218 m, 44060 m/sec, 34163961 t fired, .

Time elapsed: 279 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 110/214 20/32 StigmergyCommit-PT-07a-CTLFireability-15 4597017 m, 43359 m/sec, 35907721 t fired, .

Time elapsed: 284 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 115/214 21/32 StigmergyCommit-PT-07a-CTLFireability-15 4811636 m, 42923 m/sec, 37577271 t fired, .

Time elapsed: 289 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 120/214 22/32 StigmergyCommit-PT-07a-CTLFireability-15 5050330 m, 47738 m/sec, 39496505 t fired, .

Time elapsed: 294 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 125/214 23/32 StigmergyCommit-PT-07a-CTLFireability-15 5286939 m, 47321 m/sec, 41405960 t fired, .

Time elapsed: 299 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 130/214 24/32 StigmergyCommit-PT-07a-CTLFireability-15 5519067 m, 46425 m/sec, 43219452 t fired, .

Time elapsed: 304 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 135/214 25/32 StigmergyCommit-PT-07a-CTLFireability-15 5728187 m, 41824 m/sec, 44904469 t fired, .

Time elapsed: 309 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 140/214 26/32 StigmergyCommit-PT-07a-CTLFireability-15 5951761 m, 44714 m/sec, 46699019 t fired, .

Time elapsed: 314 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 145/214 27/32 StigmergyCommit-PT-07a-CTLFireability-15 6175681 m, 44784 m/sec, 48516310 t fired, .

Time elapsed: 319 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 150/214 28/32 StigmergyCommit-PT-07a-CTLFireability-15 6413466 m, 47557 m/sec, 50391956 t fired, .

Time elapsed: 324 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 155/214 29/32 StigmergyCommit-PT-07a-CTLFireability-15 6617132 m, 40733 m/sec, 52019794 t fired, .

Time elapsed: 329 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 160/214 30/32 StigmergyCommit-PT-07a-CTLFireability-15 6837321 m, 44037 m/sec, 53796626 t fired, .

Time elapsed: 334 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 165/214 31/32 StigmergyCommit-PT-07a-CTLFireability-15 7055964 m, 43728 m/sec, 55560224 t fired, .

Time elapsed: 339 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 170/214 32/32 StigmergyCommit-PT-07a-CTLFireability-15 7282469 m, 45301 m/sec, 57402881 t fired, .

Time elapsed: 344 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 50 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-15
lola: result : false
lola: markings : 7411889
lola: fired transitions : 58471564
lola: time used : 173.000000
lola: memory pages used : 32
lola: LAUNCH task # 47 (type EXCL) for 46 StigmergyCommit-PT-07a-CTLFireability-14
lola: time limit : 216 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 2/216 2/32 StigmergyCommit-PT-07a-CTLFireability-14 281024 m, 56204 m/sec, 1279849 t fired, .

Time elapsed: 349 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 7/216 4/32 StigmergyCommit-PT-07a-CTLFireability-14 838409 m, 111477 m/sec, 4300184 t fired, .

Time elapsed: 354 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 12/216 6/32 StigmergyCommit-PT-07a-CTLFireability-14 1343334 m, 100985 m/sec, 7352661 t fired, .

Time elapsed: 359 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 17/216 8/32 StigmergyCommit-PT-07a-CTLFireability-14 1853633 m, 102059 m/sec, 10424129 t fired, .

Time elapsed: 364 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 47 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-14
lola: result : false
lola: markings : 2234176
lola: fired transitions : 12774302
lola: time used : 21.000000
lola: memory pages used : 10
lola: LAUNCH task # 38 (type EXCL) for 33 StigmergyCommit-PT-07a-CTLFireability-11
lola: time limit : 230 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-11
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 33 StigmergyCommit-PT-07a-CTLFireability-11
lola: time limit : 248 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-11
lola: result : true
lola: markings : 51
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 StigmergyCommit-PT-07a-CTLFireability-07
lola: time limit : 269 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 1/269 1/32 StigmergyCommit-PT-07a-CTLFireability-07 88850 m, 17770 m/sec, 556420 t fired, .

Time elapsed: 369 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 6/269 3/32 StigmergyCommit-PT-07a-CTLFireability-07 478483 m, 77926 m/sec, 3345432 t fired, .

Time elapsed: 374 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 11/269 4/32 StigmergyCommit-PT-07a-CTLFireability-07 837632 m, 71829 m/sec, 6169933 t fired, .

Time elapsed: 379 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 16/269 6/32 StigmergyCommit-PT-07a-CTLFireability-07 1198989 m, 72271 m/sec, 9011405 t fired, .

Time elapsed: 384 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 21/269 7/32 StigmergyCommit-PT-07a-CTLFireability-07 1559406 m, 72083 m/sec, 11851087 t fired, .

Time elapsed: 389 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 26/269 9/32 StigmergyCommit-PT-07a-CTLFireability-07 1915586 m, 71236 m/sec, 14668029 t fired, .

Time elapsed: 394 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 31/269 10/32 StigmergyCommit-PT-07a-CTLFireability-07 2262986 m, 69480 m/sec, 17422962 t fired, .

Time elapsed: 399 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 36/269 12/32 StigmergyCommit-PT-07a-CTLFireability-07 2610127 m, 69428 m/sec, 20116405 t fired, .

Time elapsed: 404 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 41/269 13/32 StigmergyCommit-PT-07a-CTLFireability-07 2957205 m, 69415 m/sec, 22885845 t fired, .

Time elapsed: 409 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 46/269 15/32 StigmergyCommit-PT-07a-CTLFireability-07 3313743 m, 71307 m/sec, 25714718 t fired, .

Time elapsed: 414 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 51/269 16/32 StigmergyCommit-PT-07a-CTLFireability-07 3655481 m, 68347 m/sec, 28397584 t fired, .

Time elapsed: 419 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 56/269 17/32 StigmergyCommit-PT-07a-CTLFireability-07 3978306 m, 64565 m/sec, 30995559 t fired, .

Time elapsed: 424 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 61/269 19/32 StigmergyCommit-PT-07a-CTLFireability-07 4321145 m, 68567 m/sec, 33686493 t fired, .

Time elapsed: 429 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 66/269 20/32 StigmergyCommit-PT-07a-CTLFireability-07 4643055 m, 64382 m/sec, 36285747 t fired, .

Time elapsed: 434 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 71/269 22/32 StigmergyCommit-PT-07a-CTLFireability-07 5004142 m, 72217 m/sec, 39125742 t fired, .

Time elapsed: 439 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 76/269 23/32 StigmergyCommit-PT-07a-CTLFireability-07 5350089 m, 69189 m/sec, 41914052 t fired, .

Time elapsed: 444 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 81/269 25/32 StigmergyCommit-PT-07a-CTLFireability-07 5701775 m, 70337 m/sec, 44691300 t fired, .

Time elapsed: 449 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 86/269 26/32 StigmergyCommit-PT-07a-CTLFireability-07 6042410 m, 68127 m/sec, 47432405 t fired, .

Time elapsed: 454 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 91/269 28/32 StigmergyCommit-PT-07a-CTLFireability-07 6375693 m, 66656 m/sec, 50118403 t fired, .

Time elapsed: 459 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 96/269 29/32 StigmergyCommit-PT-07a-CTLFireability-07 6719816 m, 68824 m/sec, 52851937 t fired, .

Time elapsed: 464 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 101/269 31/32 StigmergyCommit-PT-07a-CTLFireability-07 7045635 m, 65163 m/sec, 55475458 t fired, .

Time elapsed: 469 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 106/269 32/32 StigmergyCommit-PT-07a-CTLFireability-07 7367784 m, 64429 m/sec, 58104585 t fired, .

Time elapsed: 474 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 22 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-07
lola: result : false
lola: markings : 7411887
lola: fired transitions : 58471546
lola: time used : 107.000000
lola: memory pages used : 32
lola: LAUNCH task # 19 (type EXCL) for 18 StigmergyCommit-PT-07a-CTLFireability-06
lola: time limit : 284 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 4/284 3/32 StigmergyCommit-PT-07a-CTLFireability-06 495826 m, 99165 m/sec, 2257579 t fired, .

Time elapsed: 479 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 9/284 5/32 StigmergyCommit-PT-07a-CTLFireability-06 959294 m, 92693 m/sec, 5150198 t fired, .

Time elapsed: 484 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 14/284 7/32 StigmergyCommit-PT-07a-CTLFireability-06 1473230 m, 102787 m/sec, 8137467 t fired, .

Time elapsed: 489 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 19/284 9/32 StigmergyCommit-PT-07a-CTLFireability-06 1978090 m, 100972 m/sec, 11145920 t fired, .

Time elapsed: 494 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 19 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-06
lola: result : true
lola: markings : 2234176
lola: fired transitions : 12774351
lola: time used : 22.000000
lola: memory pages used : 10
lola: LAUNCH task # 16 (type EXCL) for 15 StigmergyCommit-PT-07a-CTLFireability-05
lola: time limit : 310 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 2/310 2/32 StigmergyCommit-PT-07a-CTLFireability-05 284017 m, 56803 m/sec, 1298207 t fired, .

Time elapsed: 499 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 7/310 4/32 StigmergyCommit-PT-07a-CTLFireability-05 836205 m, 110437 m/sec, 4283857 t fired, .

Time elapsed: 504 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 12/310 6/32 StigmergyCommit-PT-07a-CTLFireability-05 1340796 m, 100918 m/sec, 7335391 t fired, .

Time elapsed: 509 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 17/310 8/32 StigmergyCommit-PT-07a-CTLFireability-05 1843865 m, 100613 m/sec, 10376882 t fired, .

Time elapsed: 514 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 22/310 10/32 StigmergyCommit-PT-07a-CTLFireability-05 2234176 m, 78062 m/sec, 13316585 t fired, .

Time elapsed: 519 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 27/310 10/32 StigmergyCommit-PT-07a-CTLFireability-05 2234176 m, 0 m/sec, 16347628 t fired, .

Time elapsed: 524 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 32/310 10/32 StigmergyCommit-PT-07a-CTLFireability-05 2234176 m, 0 m/sec, 19447012 t fired, .

Time elapsed: 529 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 37/310 10/32 StigmergyCommit-PT-07a-CTLFireability-05 2234176 m, 0 m/sec, 22551090 t fired, .

Time elapsed: 534 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 42/310 10/32 StigmergyCommit-PT-07a-CTLFireability-05 2234176 m, 0 m/sec, 25515064 t fired, .

Time elapsed: 539 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 47/310 12/32 StigmergyCommit-PT-07a-CTLFireability-05 2723120 m, 97788 m/sec, 28307460 t fired, .

Time elapsed: 544 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 52/310 14/32 StigmergyCommit-PT-07a-CTLFireability-05 3205680 m, 96512 m/sec, 31164058 t fired, .

Time elapsed: 549 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 57/310 16/32 StigmergyCommit-PT-07a-CTLFireability-05 3704088 m, 99681 m/sec, 34143478 t fired, .

Time elapsed: 554 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 62/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4009158 m, 61014 m/sec, 37002765 t fired, .

Time elapsed: 559 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 67/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4009159 m, 0 m/sec, 40106137 t fired, .

Time elapsed: 564 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 72/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4009160 m, 0 m/sec, 43283755 t fired, .

Time elapsed: 569 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 77/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4009162 m, 0 m/sec, 46673671 t fired, .

Time elapsed: 574 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 82/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4009163 m, 0 m/sec, 49896787 t fired, .

Time elapsed: 579 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 87/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4009166 m, 0 m/sec, 53050967 t fired, .

Time elapsed: 584 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 92/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4009168 m, 0 m/sec, 56424682 t fired, .

Time elapsed: 589 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 97/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4009169 m, 0 m/sec, 59484281 t fired, .

Time elapsed: 594 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 102/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4010477 m, 261 m/sec, 62660365 t fired, .

Time elapsed: 599 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 107/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4010483 m, 1 m/sec, 65868683 t fired, .

Time elapsed: 604 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 112/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4103907 m, 18684 m/sec, 69039218 t fired, .

Time elapsed: 609 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 117/310 18/32 StigmergyCommit-PT-07a-CTLFireability-05 4103917 m, 2 m/sec, 72294120 t fired, .

Time elapsed: 614 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 122/310 19/32 StigmergyCommit-PT-07a-CTLFireability-05 4283335 m, 35883 m/sec, 75351919 t fired, .

Time elapsed: 619 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 127/310 19/32 StigmergyCommit-PT-07a-CTLFireability-05 4283345 m, 2 m/sec, 78408210 t fired, .

Time elapsed: 624 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 132/310 19/32 StigmergyCommit-PT-07a-CTLFireability-05 4353518 m, 14034 m/sec, 81360866 t fired, .

Time elapsed: 629 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 137/310 20/32 StigmergyCommit-PT-07a-CTLFireability-05 4544723 m, 38241 m/sec, 84290582 t fired, .

Time elapsed: 634 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 142/310 20/32 StigmergyCommit-PT-07a-CTLFireability-05 4544979 m, 51 m/sec, 87376544 t fired, .

Time elapsed: 639 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 147/310 20/32 StigmergyCommit-PT-07a-CTLFireability-05 4642266 m, 19457 m/sec, 90328811 t fired, .

Time elapsed: 644 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 152/310 22/32 StigmergyCommit-PT-07a-CTLFireability-05 5081420 m, 87830 m/sec, 93332876 t fired, .

Time elapsed: 649 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 157/310 23/32 StigmergyCommit-PT-07a-CTLFireability-05 5211545 m, 26025 m/sec, 96554523 t fired, .

Time elapsed: 654 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 162/310 23/32 StigmergyCommit-PT-07a-CTLFireability-05 5227391 m, 3169 m/sec, 99832656 t fired, .

Time elapsed: 659 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 167/310 24/32 StigmergyCommit-PT-07a-CTLFireability-05 5414613 m, 37444 m/sec, 102902879 t fired, .

Time elapsed: 664 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 172/310 25/32 StigmergyCommit-PT-07a-CTLFireability-05 5708823 m, 58842 m/sec, 105957825 t fired, .

Time elapsed: 669 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 177/310 27/32 StigmergyCommit-PT-07a-CTLFireability-05 6121707 m, 82576 m/sec, 108874029 t fired, .

Time elapsed: 674 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 182/310 27/32 StigmergyCommit-PT-07a-CTLFireability-05 6223417 m, 20342 m/sec, 112125942 t fired, .

Time elapsed: 679 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 187/310 27/32 StigmergyCommit-PT-07a-CTLFireability-05 6223417 m, 0 m/sec, 115426406 t fired, .

Time elapsed: 684 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 192/310 27/32 StigmergyCommit-PT-07a-CTLFireability-05 6281142 m, 11545 m/sec, 118557269 t fired, .

Time elapsed: 689 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 197/310 28/32 StigmergyCommit-PT-07a-CTLFireability-05 6531325 m, 50036 m/sec, 121714850 t fired, .

Time elapsed: 694 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 202/310 30/32 StigmergyCommit-PT-07a-CTLFireability-05 6944389 m, 82612 m/sec, 124621261 t fired, .

Time elapsed: 699 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 207/310 31/32 StigmergyCommit-PT-07a-CTLFireability-05 7260648 m, 63251 m/sec, 127553638 t fired, .

Time elapsed: 704 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 212/310 31/32 StigmergyCommit-PT-07a-CTLFireability-05 7260648 m, 0 m/sec, 130863089 t fired, .

Time elapsed: 709 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 217/310 31/32 StigmergyCommit-PT-07a-CTLFireability-05 7260648 m, 0 m/sec, 134078645 t fired, .

Time elapsed: 714 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 222/310 32/32 StigmergyCommit-PT-07a-CTLFireability-05 7314665 m, 10803 m/sec, 137253109 t fired, .

Time elapsed: 719 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 16 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-05
lola: result : false
lola: markings : 7411910
lola: fired transitions : 139651311
lola: time used : 226.000000
lola: memory pages used : 32
lola: LAUNCH task # 10 (type EXCL) for 9 StigmergyCommit-PT-07a-CTLFireability-03
lola: time limit : 319 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 1/319 1/32 StigmergyCommit-PT-07a-CTLFireability-03 95932 m, 19186 m/sec, 690713 t fired, .

Time elapsed: 724 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 6/319 3/32 StigmergyCommit-PT-07a-CTLFireability-03 642509 m, 109315 m/sec, 3817844 t fired, .

Time elapsed: 729 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 11/319 5/32 StigmergyCommit-PT-07a-CTLFireability-03 1103621 m, 92222 m/sec, 6867618 t fired, .

Time elapsed: 734 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 16/319 7/32 StigmergyCommit-PT-07a-CTLFireability-03 1542803 m, 87836 m/sec, 9914566 t fired, .

Time elapsed: 739 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 21/319 9/32 StigmergyCommit-PT-07a-CTLFireability-03 1949580 m, 81355 m/sec, 12952167 t fired, .

Time elapsed: 744 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 26/319 11/32 StigmergyCommit-PT-07a-CTLFireability-03 2378638 m, 85811 m/sec, 15891506 t fired, .

Time elapsed: 749 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 10 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-03
lola: result : false
lola: markings : 2496494
lola: fired transitions : 16713356
lola: time used : 28.000000
lola: memory pages used : 11
lola: LAUNCH task # 4 (type EXCL) for 3 StigmergyCommit-PT-07a-CTLFireability-01
lola: time limit : 356 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 3/356 2/32 StigmergyCommit-PT-07a-CTLFireability-01 394245 m, 78849 m/sec, 2347682 t fired, .

Time elapsed: 754 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 8/356 4/32 StigmergyCommit-PT-07a-CTLFireability-01 893299 m, 99810 m/sec, 5385190 t fired, .

Time elapsed: 759 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 13/356 6/32 StigmergyCommit-PT-07a-CTLFireability-01 1338109 m, 88962 m/sec, 8503193 t fired, .

Time elapsed: 764 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 18/356 8/32 StigmergyCommit-PT-07a-CTLFireability-01 1768997 m, 86177 m/sec, 11545837 t fired, .

Time elapsed: 769 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 23/356 10/32 StigmergyCommit-PT-07a-CTLFireability-01 2206691 m, 87538 m/sec, 14599326 t fired, .

Time elapsed: 774 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 28/356 12/32 StigmergyCommit-PT-07a-CTLFireability-01 2632932 m, 85248 m/sec, 17558280 t fired, .

Time elapsed: 779 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 33/356 14/32 StigmergyCommit-PT-07a-CTLFireability-01 3052103 m, 83834 m/sec, 20438203 t fired, .

Time elapsed: 784 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 38/356 15/32 StigmergyCommit-PT-07a-CTLFireability-01 3480014 m, 85582 m/sec, 23382126 t fired, .

Time elapsed: 789 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-09: F 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-10: AFAG 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 43/356 17/32 StigmergyCommit-PT-07a-CTLFireability-01 3917748 m, 87546 m/sec, 26431927 t fired, .

Time elapsed: 794 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 4 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-01
lola: result : false
lola: markings : 4271454
lola: fired transitions : 29154937
lola: time used : 48.000000
lola: memory pages used : 19
lola: LAUNCH task # 52 (type EXCL) for 27 StigmergyCommit-PT-07a-CTLFireability-09
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-09
lola: result : false
lola: markings : 255
lola: fired transitions : 1016
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 StigmergyCommit-PT-07a-CTLFireability-10
lola: time limit : 466 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-10
lola: result : false
lola: markings : 10
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 StigmergyCommit-PT-07a-CTLFireability-12
lola: time limit : 560 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-12
lola: result : false
lola: markings : 9
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 StigmergyCommit-PT-07a-CTLFireability-00
lola: time limit : 700 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-00
lola: result : false
lola: markings : 256
lola: fired transitions : 1027
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 StigmergyCommit-PT-07a-CTLFireability-08
lola: time limit : 933 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-08
lola: result : true
lola: markings : 13448
lola: fired transitions : 155095
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 StigmergyCommit-PT-07a-CTLFireability-02
lola: time limit : 1400 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-00: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-01: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-08: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-09: F true state space / EG
StigmergyCommit-PT-07a-CTLFireability-10: AFAG false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-12: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-07a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-07a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
StigmergyCommit-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 0/1400 1/32 StigmergyCommit-PT-07a-CTLFireability-02 7862 m, 1572 m/sec, 149601 t fired, .

Time elapsed: 799 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 7 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-02
lola: result : true
lola: markings : 13448
lola: fired transitions : 274851
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 StigmergyCommit-PT-07a-CTLFireability-13
lola: time limit : 2801 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-13
lola: result : false
lola: markings : 98383
lola: fired transitions : 721260
lola: time used : 1.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-07a-CTLFireability-00: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-01: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-04: CTL unknown AGGR
StigmergyCommit-PT-07a-CTLFireability-05: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-07: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-08: CTL true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-09: F true state space / EG
StigmergyCommit-PT-07a-CTLFireability-10: AFAG false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-11: DISJ true CTL model checker
StigmergyCommit-PT-07a-CTLFireability-12: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-13: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-07a-CTLFireability-15: CTL false CTL model checker


Time elapsed: 800 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyCommit-PT-07a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is StigmergyCommit-PT-07a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r454-smll-167912646500474"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/StigmergyCommit-PT-07a.tgz
mv StigmergyCommit-PT-07a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;