fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r454-smll-167912646400458
Last Updated
May 14, 2023

About the Execution of LoLA for StigmergyCommit-PT-06a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1075.447 113944.00 116010.00 525.70 TFTFTTTTTTTFTTFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r454-smll-167912646400458.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is StigmergyCommit-PT-06a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r454-smll-167912646400458
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.3M
-rw-r--r-- 1 mcc users 9.5K Feb 26 11:04 CTLCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 26 11:04 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 11:02 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K Feb 26 11:02 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 11:05 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 122K Feb 26 11:05 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.6K Feb 26 11:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 26 11:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 1.8M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-00
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-01
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-02
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-03
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-04
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-05
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-06
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-07
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-08
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-09
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-10
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-11
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-12
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-13
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-14
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679374121733

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=StigmergyCommit-PT-06a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT StigmergyCommit-PT-06a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA StigmergyCommit-PT-06a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA StigmergyCommit-PT-06a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679374235677

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 7 (type EXCL) for 6 StigmergyCommit-PT-06a-CTLFireability-02
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 60 (type FNDP) for 47 StigmergyCommit-PT-06a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type EQUN) for 47 StigmergyCommit-PT-06a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type SRCH) for 47 StigmergyCommit-PT-06a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 60 (type FNDP) for StigmergyCommit-PT-06a-CTLFireability-13
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 61 (type EQUN) for StigmergyCommit-PT-06a-CTLFireability-13 (obsolete)
lola: CANCELED task # 63 (type SRCH) for StigmergyCommit-PT-06a-CTLFireability-13 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/CTLFireability-61.sara.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810

lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 61 (type EQUN) for StigmergyCommit-PT-06a-CTLFireability-13
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 64 (type FNDP) for 47 StigmergyCommit-PT-06a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type EQUN) for 47 StigmergyCommit-PT-06a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SRCH) for 47 StigmergyCommit-PT-06a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 64 (type FNDP) for StigmergyCommit-PT-06a-CTLFireability-13
lola: result : true
lola: fired transitions : 6
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 65 (type EQUN) for StigmergyCommit-PT-06a-CTLFireability-13 (obsolete)
lola: CANCELED task # 67 (type SRCH) for StigmergyCommit-PT-06a-CTLFireability-13 (obsolete)
lola: FINISHED task # 67 (type SRCH) for StigmergyCommit-PT-06a-CTLFireability-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: lola: try reading problem file /home/mcc/execution/CTLFireability-65.sara.
rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 65 (type EQUN) for StigmergyCommit-PT-06a-CTLFireability-13
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-08: EXEF 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 4/211 2/32 StigmergyCommit-PT-06a-CTLFireability-02 433297 m, 86659 m/sec, 2777379 t fired, .

Time elapsed: 6 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-08: EXEF 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 9/211 5/32 StigmergyCommit-PT-06a-CTLFireability-02 957747 m, 104890 m/sec, 5972224 t fired, .

Time elapsed: 11 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 7 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-02
lola: result : true
lola: markings : 1153503
lola: fired transitions : 7186780
lola: time used : 12.000000
lola: memory pages used : 5
lola: LAUNCH task # 58 (type EXCL) for 57 StigmergyCommit-PT-06a-CTLFireability-15
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-15
lola: result : false
lola: markings : 46
lola: fired transitions : 93
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 54 StigmergyCommit-PT-06a-CTLFireability-14
lola: time limit : 239 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-08: EXEF 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 2/239 1/32 StigmergyCommit-PT-06a-CTLFireability-14 227994 m, 45598 m/sec, 1763485 t fired, .

Time elapsed: 16 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-08: EXEF 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 7/239 4/32 StigmergyCommit-PT-06a-CTLFireability-14 712802 m, 96961 m/sec, 5183889 t fired, .

Time elapsed: 21 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-08: EXEF 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 12/239 5/32 StigmergyCommit-PT-06a-CTLFireability-14 1129351 m, 83309 m/sec, 8163110 t fired, .

Time elapsed: 26 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 55 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-14
lola: result : false
lola: markings : 1153502
lola: fired transitions : 8340294
lola: time used : 13.000000
lola: memory pages used : 5
lola: LAUNCH task # 45 (type EXCL) for 44 StigmergyCommit-PT-06a-CTLFireability-12
lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-12
lola: result : true
lola: markings : 1878
lola: fired transitions : 6319
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 StigmergyCommit-PT-06a-CTLFireability-11
lola: time limit : 274 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-08: EXEF 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 4/274 3/32 StigmergyCommit-PT-06a-CTLFireability-11 472493 m, 94498 m/sec, 2787989 t fired, .

Time elapsed: 31 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-08: EXEF 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
StigmergyCommit-PT-06a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 9/274 5/32 StigmergyCommit-PT-06a-CTLFireability-11 998896 m, 105280 m/sec, 6008760 t fired, .

Time elapsed: 36 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 42 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-11
lola: result : false
lola: markings : 1058841
lola: fired transitions : 6386654
lola: time used : 10.000000
lola: memory pages used : 5
lola: LAUNCH task # 39 (type EXCL) for 38 StigmergyCommit-PT-06a-CTLFireability-10
lola: time limit : 296 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-10
lola: result : true
lola: markings : 372557
lola: fired transitions : 2087075
lola: time used : 3.000000
lola: memory pages used : 2
lola: LAUNCH task # 36 (type EXCL) for 31 StigmergyCommit-PT-06a-CTLFireability-09
lola: time limit : 323 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-09
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 31 StigmergyCommit-PT-06a-CTLFireability-09
lola: time limit : 356 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-09
lola: result : true
lola: markings : 45
lola: fired transitions : 44
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 StigmergyCommit-PT-06a-CTLFireability-08
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-08
lola: result : true
lola: markings : 45
lola: fired transitions : 44
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 21 StigmergyCommit-PT-06a-CTLFireability-07
lola: time limit : 445 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-07
lola: result : true
lola: markings : 46
lola: fired transitions : 137
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 StigmergyCommit-PT-06a-CTLFireability-06
lola: time limit : 593 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 1/593 1/32 StigmergyCommit-PT-06a-CTLFireability-06 122769 m, 24553 m/sec, 743692 t fired, .

Time elapsed: 41 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 19 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-06
lola: result : true
lola: markings : 372577
lola: fired transitions : 2436582
lola: time used : 4.000000
lola: memory pages used : 2
lola: LAUNCH task # 16 (type EXCL) for 15 StigmergyCommit-PT-06a-CTLFireability-05
lola: time limit : 711 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-05
lola: result : true
lola: markings : 66
lola: fired transitions : 116
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 StigmergyCommit-PT-06a-CTLFireability-04
lola: time limit : 889 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 2/889 2/32 StigmergyCommit-PT-06a-CTLFireability-04 288926 m, 57785 m/sec, 1604661 t fired, .

Time elapsed: 46 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 13 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-04
lola: result : true
lola: markings : 839876
lola: fired transitions : 4907860
lola: time used : 7.000000
lola: memory pages used : 4
lola: LAUNCH task # 10 (type EXCL) for 9 StigmergyCommit-PT-06a-CTLFireability-03
lola: time limit : 1183 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 0/1183 1/32 StigmergyCommit-PT-06a-CTLFireability-03 33559 m, 6711 m/sec, 149549 t fired, .

Time elapsed: 51 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/1183 3/32 StigmergyCommit-PT-06a-CTLFireability-03 481791 m, 89646 m/sec, 3434895 t fired, .

Time elapsed: 56 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 10 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-03
lola: result : false
lola: markings : 481791
lola: fired transitions : 5199748
lola: time used : 8.000000
lola: memory pages used : 3
lola: LAUNCH task # 4 (type EXCL) for 3 StigmergyCommit-PT-06a-CTLFireability-01
lola: time limit : 1770 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 2/1770 2/32 StigmergyCommit-PT-06a-CTLFireability-01 274088 m, 54817 m/sec, 1512013 t fired, .

Time elapsed: 61 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 7/1770 2/32 StigmergyCommit-PT-06a-CTLFireability-01 372614 m, 19705 m/sec, 2523943 t fired, .

Time elapsed: 66 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 12/1770 2/32 StigmergyCommit-PT-06a-CTLFireability-01 372673 m, 11 m/sec, 3044366 t fired, .

Time elapsed: 71 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 17/1770 2/32 StigmergyCommit-PT-06a-CTLFireability-01 372808 m, 27 m/sec, 3626144 t fired, .

Time elapsed: 76 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 22/1770 2/32 StigmergyCommit-PT-06a-CTLFireability-01 373180 m, 74 m/sec, 4246459 t fired, .

Time elapsed: 81 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 27/1770 2/32 StigmergyCommit-PT-06a-CTLFireability-01 462802 m, 17924 m/sec, 4814459 t fired, .

Time elapsed: 86 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 32/1770 3/32 StigmergyCommit-PT-06a-CTLFireability-01 577709 m, 22981 m/sec, 5511190 t fired, .

Time elapsed: 91 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 37/1770 3/32 StigmergyCommit-PT-06a-CTLFireability-01 677666 m, 19991 m/sec, 6117760 t fired, .

Time elapsed: 96 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 42/1770 4/32 StigmergyCommit-PT-06a-CTLFireability-01 784238 m, 21314 m/sec, 6774270 t fired, .

Time elapsed: 101 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 47/1770 4/32 StigmergyCommit-PT-06a-CTLFireability-01 893020 m, 21756 m/sec, 7446412 t fired, .

Time elapsed: 106 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyCommit-PT-06a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
StigmergyCommit-PT-06a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 52/1770 5/32 StigmergyCommit-PT-06a-CTLFireability-01 996601 m, 20716 m/sec, 8081077 t fired, .

Time elapsed: 111 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 4 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-01
lola: result : false
lola: markings : 1058842
lola: fired transitions : 8473716
lola: time used : 55.000000
lola: memory pages used : 5
lola: LAUNCH task # 1 (type EXCL) for 0 StigmergyCommit-PT-06a-CTLFireability-00
lola: time limit : 3486 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for StigmergyCommit-PT-06a-CTLFireability-00
lola: result : true
lola: markings : 46
lola: fired transitions : 182
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyCommit-PT-06a-CTLFireability-00: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-01: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-02: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-03: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-04: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-05: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-06: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-07: DISJ true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-08: EXEF true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-09: DISJ true state space /EXEF
StigmergyCommit-PT-06a-CTLFireability-10: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-11: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-12: CTL true CTL model checker
StigmergyCommit-PT-06a-CTLFireability-13: CONJ true CONJ
StigmergyCommit-PT-06a-CTLFireability-14: CTL false CTL model checker
StigmergyCommit-PT-06a-CTLFireability-15: CTL false CTL model checker


Time elapsed: 114 secs. Pages in use: 5

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyCommit-PT-06a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is StigmergyCommit-PT-06a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r454-smll-167912646400458"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/StigmergyCommit-PT-06a.tgz
mv StigmergyCommit-PT-06a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;