fond

jQuery Multi Level CSS Menu Css3Menu.com

Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r454-smll-167912646000146
Last Updated
May 14, 2023

About the Execution of LoLA for SmallOperatingSystem-PT-MT8192DC4096

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3173.903 75307.00 70177.00 326.80 F?FF?TTTT?FFFTFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r454-smll-167912646000146.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is SmallOperatingSystem-PT-MT8192DC4096, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r454-smll-167912646000146
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 11K Feb 25 12:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 97K Feb 25 12:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Feb 25 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 12:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 94K Feb 25 12:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 12:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 87K Feb 25 12:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679218812784

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT8192DC4096
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT8192DC4096
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679218888091

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:122
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:207
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 4 (type EXCL) for 3 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 60 (type FNDP) for 29 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07
lola: time limit : 32000000 sec
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lola: LAUNCH task # 61 (type EQUN) for 29 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07
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lola: LAUNCH task # 63 (type SRCH) for 29 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07
lola: time limit : 32000000 sec
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lola: FINISHED task # 63 (type SRCH) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: CANCELED task # 60 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07 (obsolete)
lola: CANCELED task # 61 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 60 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07
lola: result : true
lola: tried executions : 1
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lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/CTLFireability-61.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 61 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/211 9/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01 2003839 m, 400767 m/sec, 3991943 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/211 18/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01 4195696 m, 438371 m/sec, 8376370 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/211 27/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01 6188365 m, 398533 m/sec, 12362356 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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lola: result : true
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lola: FINISHED task # 43 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10
lola: result : false
lola: markings : 4097
lola: fired transitions : 8193
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lola: result : true
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lola: result : true
lola: markings : 16386
lola: fired transitions : 32775
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: DISJ true search / frozen tokens
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 5/397 5/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04 967811 m, 193562 m/sec, 3854933 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: DISJ true search / frozen tokens
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 10/397 9/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04 2006654 m, 207768 m/sec, 8010386 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0

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21 CTL EXCL 15/397 13/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04 3051707 m, 209010 m/sec, 12190683 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 20/397 18/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04 4086021 m, 206862 m/sec, 16328025 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: DISJ true search / frozen tokens
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 25/397 22/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04 5072799 m, 197355 m/sec, 20275215 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: DISJ true search / frozen tokens
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 30/397 26/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04 6113674 m, 208175 m/sec, 24438800 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: DISJ true search / frozen tokens
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 35/397 31/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04 7150940 m, 207453 m/sec, 28587955 t fired, .

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lola: CANCELED task # 21 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04 (memory limit exceeded)
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: DISJ true search / frozen tokens
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 18 (type EXCL) for 13 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03
lola: time limit : 442 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03
lola: result : false
lola: markings : 20480
lola: fired transitions : 24577
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 13 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03
lola: time limit : 505 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03
lola: result : false
lola: markings : 16384
lola: fired transitions : 32768
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 6 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: time limit : 590 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 6 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: time limit : 708 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: result : false
lola: markings : 4096
lola: fired transitions : 12286
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00
lola: time limit : 885 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00
lola: result : false
lola: markings : 8193
lola: fired transitions : 16390
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 54 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14
lola: time limit : 1180 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09
lola: time limit : 1770 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: DISJ true search / frozen tokens
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG false state space / EG
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/1770 12/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09 2783846 m, 556769 m/sec, 8335375 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: DISJ true search / frozen tokens
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG false state space / EG
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/1770 24/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09 5581727 m, 559576 m/sec, 16729247 t fired, .

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lola: CANCELED task # 40 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: DISJ true search / frozen tokens
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG false state space / EG
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 52 (type EXCL) for 51 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13
lola: time limit : 3525 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: DISJ true search / frozen tokens
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: EG false state space / EG
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT8192DC4096"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is SmallOperatingSystem-PT-MT8192DC4096, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r454-smll-167912646000146"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT8192DC4096.tgz
mv SmallOperatingSystem-PT-MT8192DC4096 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;