fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r454-smll-167912646000114
Last Updated
May 14, 2023

About the Execution of LoLA for SmallOperatingSystem-PT-MT2048DC1024

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
4785.771 215481.00 200355.00 767.60 T????T?TT?TFFFT? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r454-smll-167912646000114.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is SmallOperatingSystem-PT-MT2048DC1024, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r454-smll-167912646000114
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 8.9K Feb 25 12:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 78K Feb 25 12:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 25 12:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 25 12:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 12:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 99K Feb 25 12:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 12:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Feb 25 12:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679203694771

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT2048DC1024
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT2048DC1024
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679203910252

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 29 (type EXCL) for 28 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 56 (type FNDP) for 0 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type EQUN) for 0 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 60 (type SRCH) for 0 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 60 (type SRCH) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 56 (type FNDP) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 58 (type EQUN) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 61 (type FNDP) for 50 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type EQUN) for 50 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SRCH) for 50 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type SRCH) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 61 (type FNDP) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14 (obsolete)
lola: CANCELED task # 62 (type EQUN) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14 (obsolete)
lola: FINISHED task # 61 (type FNDP) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/CTLFireability-58.sara.
sara: try reading problem file /home/mcc/execution/CTLFireability-62.sara.


lola: FINISHED task # 62 (type EQUN) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14
lola: result : true
lola: FINISHED task # 58 (type EQUN) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00
lola: result : true
lola: FINISHED task # 29 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08
lola: result : true
lola: markings : 530942
lola: fired transitions : 1077256
lola: time used : 1.000000
lola: memory pages used : 3
lola: LAUNCH task # 54 (type EXCL) for 53 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15
lola: time limit : 239 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 4/239 7/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15 1503403 m, 300680 m/sec, 4354134 t fired, .

Time elapsed: 5 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 9/239 14/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15 3260847 m, 351488 m/sec, 9041994 t fired, .

Time elapsed: 10 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 14/239 21/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15 4876529 m, 323136 m/sec, 14297527 t fired, .

Time elapsed: 15 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 19/239 27/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15 6344517 m, 293597 m/sec, 20348993 t fired, .

Time elapsed: 20 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 48 (type EXCL) for 47 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13
lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13
lola: result : false
lola: markings : 4098
lola: fired transitions : 10247
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12
lola: result : false
lola: markings : 8195
lola: fired transitions : 16401
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09
lola: time limit : 297 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/297 4/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09 908966 m, 181793 m/sec, 5462449 t fired, .

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/297 14/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09 3198615 m, 457929 m/sec, 12757970 t fired, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 15/297 25/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09 5844213 m, 529119 m/sec, 20689484 t fired, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 32 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 26 (type EXCL) for 25 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07
lola: time limit : 323 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07
lola: result : true
lola: markings : 1053696
lola: fired transitions : 2104663
lola: time used : 2.000000
lola: memory pages used : 5
lola: LAUNCH task # 23 (type EXCL) for 22 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06
lola: time limit : 355 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 3/355 4/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06 842459 m, 168491 m/sec, 2522780 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 8/355 9/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06 1937698 m, 219047 m/sec, 5808027 t fired, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 13/355 14/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06 3202559 m, 252972 m/sec, 9602517 t fired, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 18/355 20/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06 4677970 m, 295082 m/sec, 14527458 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 23/355 26/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06 6147062 m, 293818 m/sec, 20723402 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 28/355 32/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06 7564594 m, 283506 m/sec, 26771947 t fired, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 23 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 20 (type EXCL) for 19 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05
lola: time limit : 391 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05
lola: result : true
lola: markings : 5120
lola: fired transitions : 10241
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 0 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00
lola: time limit : 440 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00
lola: result : false
lola: markings : 1025
lola: fired transitions : 1024
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 8 (type EXCL) for 7 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01
lola: time limit : 502 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 AGEF EXCL 5/502 18/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01 4824428 m, 964885 m/sec, 7236464 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 8 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 42 (type EXCL) for 41 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11
lola: time limit : 585 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11
lola: result : false
lola: markings : 4098
lola: fired transitions : 9221
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 34 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10
lola: time limit : 702 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10
lola: result : true
lola: markings : 1062913
lola: fired transitions : 4219223
lola: time used : 5.000000
lola: memory pages used : 5
lola: LAUNCH task # 17 (type EXCL) for 16 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04
lola: time limit : 1168 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 0/1168 1/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 56779 m, 11355 m/sec, 163494 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/1168 5/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 1055742 m, 199792 m/sec, 5916623 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/1168 9/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 2105341 m, 209919 m/sec, 11944497 t fired, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/1168 9/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 2105341 m, 0 m/sec, 18044604 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 20/1168 14/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 3155964 m, 210124 m/sec, 24258221 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 25/1168 16/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 3598930 m, 88593 m/sec, 30862419 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 30/1168 19/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 4329630 m, 146140 m/sec, 36706188 t fired, .

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 35/1168 22/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 5017780 m, 137630 m/sec, 42211612 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 40/1168 25/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 5842219 m, 164887 m/sec, 48805336 t fired, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 45/1168 28/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 6652584 m, 162073 m/sec, 55286455 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 50/1168 32/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 7442914 m, 158066 m/sec, 61607278 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 17 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 11 (type EXCL) for 10 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02
lola: time limit : 1725 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/1725 5/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02 1014703 m, 202940 m/sec, 6085468 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/1725 9/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02 2030246 m, 203108 m/sec, 12175994 t fired, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 15/1725 13/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02 3035717 m, 201094 m/sec, 18206073 t fired, .

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 20/1725 17/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02 4028580 m, 198572 m/sec, 24160505 t fired, .

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 25/1725 22/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02 5036322 m, 201548 m/sec, 30204221 t fired, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 30/1725 26/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02 6070630 m, 206861 m/sec, 36407340 t fired, .

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 35/1725 30/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02 7068438 m, 199561 m/sec, 42391447 t fired, .

Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 11 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 14 (type EXCL) for 13 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03
lola: time limit : 3410 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/3410 5/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03 1186713 m, 237342 m/sec, 4747104 t fired, .

Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 10/3410 11/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03 2404139 m, 243485 m/sec, 9612942 t fired, .

Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 15/3410 18/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03 4229619 m, 365096 m/sec, 15834925 t fired, .

Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 20/3410 29/32 SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03 6867747 m, 527625 m/sec, 23744029 t fired, .

Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 14 (type EXCL) for SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-00: CONJ true CONJ
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-01: AGEF unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-02: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-03: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-06: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-09: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-10: DISJ true CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-14: EF true search / frozen tokens
SmallOperatingSystem-PT-MT2048DC1024-CTLFireability-15: CTL unknown AGGR


Time elapsed: 215 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT2048DC1024"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is SmallOperatingSystem-PT-MT2048DC1024, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r454-smll-167912646000114"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT2048DC1024.tgz
mv SmallOperatingSystem-PT-MT2048DC1024 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;