Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2023-input.r423-tajo-167905976800510.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.....................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SimpleLoadBal-PT-05, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-tajo-167905976800510
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 732K
-rw-r--r-- 1 mcc users 6.6K Feb 26 03:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 54K Feb 26 03:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 26 03:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 26 03:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.1K Feb 25 17:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 17:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 28K Feb 26 03:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 241K Feb 26 03:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 03:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 71K Feb 26 03:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 17:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 155K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-00
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-01
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-02
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-03
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-04
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-05
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-06
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-07
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-08
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-09
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-10
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-11
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-12
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-13
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-14
FORMULA_NAME SimpleLoadBal-PT-05-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1679250247823

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SimpleLoadBal-PT-05
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 18:24:09] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 18:24:09] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 18:24:09] [INFO ] Load time of PNML (sax parser for PT used): 51 ms
[2023-03-19 18:24:09] [INFO ] Transformed 59 places.
[2023-03-19 18:24:09] [INFO ] Transformed 180 transitions.
[2023-03-19 18:24:09] [INFO ] Found NUPN structural information;
[2023-03-19 18:24:09] [INFO ] Completing missing partition info from NUPN : creating a component with [P_client_idle_1, P_client_idle_2, P_client_idle_3, P_client_idle_4, P_client_idle_5, P_client_waiting_1, P_client_waiting_2, P_client_waiting_3, P_client_waiting_4, P_client_waiting_5, P_client_request_1, P_client_request_2, P_client_request_3, P_client_request_4, P_client_request_5, P_client_ack_1, P_client_ack_2, P_client_ack_3, P_client_ack_4, P_client_ack_5, P_server_idle_1, P_server_idle_2, P_server_waiting_1, P_server_waiting_2, P_server_processed_1, P_server_processed_2, P_server_notification_1, P_server_notification_2, P_server_notification_ack_1, P_server_notification_ack_2, P_server_request_1_1, P_server_request_1_2, P_server_request_2_1, P_server_request_2_2, P_server_request_3_1, P_server_request_3_2, P_server_request_4_1, P_server_request_4_2, P_server_request_5_1, P_server_request_5_2, P_lb_idle_1, P_lb_routing_1_1, P_lb_routing_1_2, P_lb_routing_1_3, P_lb_routing_1_4, P_lb_routing_1_5, P_lb_balancing_1, P_lb_load_1_0, P_lb_load_1_1, P_lb_load_1_2, P_lb_load_1_3, P_lb_load_1_4, P_lb_load_1_5, P_lb_load_2_0, P_lb_load_2_1, P_lb_load_2_2, P_lb_load_2_3, P_lb_load_2_4, P_lb_load_2_5]
[2023-03-19 18:24:09] [INFO ] Parsed PT model containing 59 places and 180 transitions and 1158 arcs in 123 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 21 ms.
Working with output stream class java.io.PrintStream
Initial state reduction rules removed 1 formulas.
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 406 ms. (steps per millisecond=24 ) properties (out of 8) seen :4
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-13 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-11 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-10 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-03 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 110 ms. (steps per millisecond=90 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 72 ms. (steps per millisecond=138 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 78 ms. (steps per millisecond=128 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-19 18:24:10] [INFO ] Flow matrix only has 140 transitions (discarded 40 similar events)
// Phase 1: matrix 140 rows 59 cols
[2023-03-19 18:24:10] [INFO ] Computed 19 place invariants in 10 ms
[2023-03-19 18:24:10] [INFO ] After 179ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:3
[2023-03-19 18:24:11] [INFO ] [Nat]Absence check using 16 positive place invariants in 18 ms returned sat
[2023-03-19 18:24:11] [INFO ] [Nat]Absence check using 16 positive and 3 generalized place invariants in 1 ms returned sat
[2023-03-19 18:24:11] [INFO ] After 58ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :1
[2023-03-19 18:24:11] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-19 18:24:11] [INFO ] After 29ms SMT Verify possible using 55 Read/Feed constraints in natural domain returned unsat :3 sat :1
[2023-03-19 18:24:11] [INFO ] After 70ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :1
Attempting to minimize the solution found.
Minimization took 52 ms.
[2023-03-19 18:24:11] [INFO ] After 290ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :1
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-14 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-09 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-00 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 4 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 3 ms.
Support contains 5 out of 59 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 59/59 places, 180/180 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 58 transition count 179
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 0 with 15 rules applied. Total rules applied 17 place count 48 transition count 174
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 0 with 10 rules applied. Total rules applied 27 place count 43 transition count 169
Applied a total of 27 rules in 56 ms. Remains 43 /59 variables (removed 16) and now considering 169/180 (removed 11) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 57 ms. Remains : 43/59 places, 169/180 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 1) seen :0
Probably explored full state space saw : 6834 states, properties seen :0
Probabilistic random walk after 29975 steps, saw 6834 distinct states, run finished after 73 ms. (steps per millisecond=410 ) properties seen :0
Explored full state space saw : 6834 states, properties seen :0
Exhaustive walk after 29975 steps, saw 6834 distinct states, run finished after 50 ms. (steps per millisecond=599 ) properties seen :0
FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-12 TRUE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
All properties solved without resorting to model-checking.
Total runtime 1794 ms.
starting LoLA
BK_INPUT SimpleLoadBal-PT-05
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SimpleLoadBal-PT-05-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679250257131

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 52 (type EXCL) for 9 SimpleLoadBal-PT-05-ReachabilityCardinality-03
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 9 SimpleLoadBal-PT-05-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 9 SimpleLoadBal-PT-05-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 9 SimpleLoadBal-PT-05-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 52 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-03
lola: result : true
lola: markings : 53
lola: fired transitions : 57
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 48 (type FNDP) for SimpleLoadBal-PT-05-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 49 (type EQUN) for SimpleLoadBal-PT-05-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 51 (type SRCH) for SimpleLoadBal-PT-05-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 63 (type EXCL) for 12 SimpleLoadBal-PT-05-ReachabilityCardinality-04
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 66 (type FNDP) for 21 SimpleLoadBal-PT-05-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type EQUN) for 21 SimpleLoadBal-PT-05-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type SRCH) for 21 SimpleLoadBal-PT-05-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 48 (type FNDP) for SimpleLoadBal-PT-05-ReachabilityCardinality-03
lola: result : true
lola: fired transitions : 1044
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-67.sara.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 63 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-04
lola: result : false
lola: markings : 5466
lola: fired transitions : 11628
lola: time used : 1.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 112 (type EXCL) for 3 SimpleLoadBal-PT-05-ReachabilityCardinality-01
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 112 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-01
lola: result : false
lola: markings : 2972
lola: fired transitions : 7081
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 93 (type EXCL) for 30 SimpleLoadBal-PT-05-ReachabilityCardinality-10
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 93 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-10
lola: result : true
lola: markings : 24
lola: fired transitions : 23
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 83 (type EXCL) for 6 SimpleLoadBal-PT-05-ReachabilityCardinality-02
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-49.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 83 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-02
lola: result : false
lola: markings : 34566
lola: fired transitions : 83174
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 149 (type EXCL) for 24 SimpleLoadBal-PT-05-ReachabilityCardinality-08
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 149 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-08
lola: result : false
lola: markings : 2972
lola: fired transitions : 7081
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 147 (type EXCL) for 39 SimpleLoadBal-PT-05-ReachabilityCardinality-13
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 147 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-13
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 70 (type EXCL) for 21 SimpleLoadBal-PT-05-ReachabilityCardinality-07
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 69 (type SRCH) for SimpleLoadBal-PT-05-ReachabilityCardinality-07
lola: result : false
lola: markings : 83953
lola: fired transitions : 251360
lola: time used : 2.000000
lola: memory pages used : 1
lola: CANCELED task # 66 (type FNDP) for SimpleLoadBal-PT-05-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 67 (type EQUN) for SimpleLoadBal-PT-05-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 70 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 107 (type EXCL) for 15 SimpleLoadBal-PT-05-ReachabilityCardinality-05
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 123 (type FNDP) for 42 SimpleLoadBal-PT-05-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 126 (type EQUN) for 42 SimpleLoadBal-PT-05-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 128 (type SRCH) for 42 SimpleLoadBal-PT-05-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 66 (type FNDP) for SimpleLoadBal-PT-05-ReachabilityCardinality-07
lola: result : unknown
lola: fired transitions : 112737
lola: tried executions : 2
lola: time used : 2.000000
lola: memory pages used : 0
lola: FINISHED task # 67 (type EQUN) for SimpleLoadBal-PT-05-ReachabilityCardinality-07
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-126.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 128 (type SRCH) for SimpleLoadBal-PT-05-ReachabilityCardinality-14
lola: result : false
lola: markings : 110447
lola: fired transitions : 368821
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 123 (type FNDP) for SimpleLoadBal-PT-05-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 126 (type EQUN) for SimpleLoadBal-PT-05-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 115 (type FNDP) for 36 SimpleLoadBal-PT-05-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 116 (type EQUN) for 36 SimpleLoadBal-PT-05-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type SRCH) for 36 SimpleLoadBal-PT-05-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 126 (type EQUN) for SimpleLoadBal-PT-05-ReachabilityCardinality-14
lola: result : unknown
lola: FINISHED task # 123 (type FNDP) for SimpleLoadBal-PT-05-ReachabilityCardinality-14
lola: result : unknown
lola: fired transitions : 113055
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 107 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-05
lola: result : false
lola: markings : 42175
lola: fired transitions : 93915
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 99 (type EXCL) for 33 SimpleLoadBal-PT-05-ReachabilityCardinality-11
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 99 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-11
lola: result : true
lola: markings : 488
lola: fired transitions : 606
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 144 (type EXCL) for 18 SimpleLoadBal-PT-05-ReachabilityCardinality-06
lola: time limit : 719 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-116.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 118 (type SRCH) for SimpleLoadBal-PT-05-ReachabilityCardinality-12
lola: result : false
lola: markings : 50725
lola: fired transitions : 156540
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 115 (type FNDP) for SimpleLoadBal-PT-05-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 116 (type EQUN) for SimpleLoadBal-PT-05-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 121 (type FNDP) for 45 SimpleLoadBal-PT-05-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 132 (type EQUN) for 45 SimpleLoadBal-PT-05-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 134 (type SRCH) for 45 SimpleLoadBal-PT-05-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 115 (type FNDP) for SimpleLoadBal-PT-05-ReachabilityCardinality-12
lola: result : unknown
lola: fired transitions : 60502
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 116 (type EQUN) for SimpleLoadBal-PT-05-ReachabilityCardinality-12
lola: result : unknown
lola: FINISHED task # 121 (type FNDP) for SimpleLoadBal-PT-05-ReachabilityCardinality-15
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 132 (type EQUN) for SimpleLoadBal-PT-05-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 134 (type SRCH) for SimpleLoadBal-PT-05-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 72 (type FNDP) for 27 SimpleLoadBal-PT-05-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type EQUN) for 27 SimpleLoadBal-PT-05-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type SRCH) for 27 SimpleLoadBal-PT-05-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-132.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-73.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 144 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-06
lola: result : false
lola: markings : 38617
lola: fired transitions : 74552
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 86 (type EXCL) for 0 SimpleLoadBal-PT-05-ReachabilityCardinality-00
lola: time limit : 1798 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SimpleLoadBal-PT-05-ReachabilityCardinality-01: AG true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-02: AG true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-03: EF true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-04: AG true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-05: EF false tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-06: EF false tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-07: AG true tandem / insertion
SimpleLoadBal-PT-05-ReachabilityCardinality-08: AG true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-10: AG false tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-11: EF true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-12: AG true tandem / insertion
SimpleLoadBal-PT-05-ReachabilityCardinality-13: EF true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-14: EF false tandem / insertion
SimpleLoadBal-PT-05-ReachabilityCardinality-15: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SimpleLoadBal-PT-05-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
SimpleLoadBal-PT-05-ReachabilityCardinality-09: EF 0 2 3 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 EF FNDP 1/1198 0/5 SimpleLoadBal-PT-05-ReachabilityCardinality-09 107399 t fired, 1 attempts, .
73 EF STEQ 1/1198 0/5 SimpleLoadBal-PT-05-ReachabilityCardinality-09 sara is running.
75 EF SRCH 1/1798 1/5 SimpleLoadBal-PT-05-ReachabilityCardinality-09 84556 m, 16911 m/sec, 206456 t fired, .
86 EF EXCL 1/1798 1/32 SimpleLoadBal-PT-05-ReachabilityCardinality-00 37831 m, 7566 m/sec, 81091 t fired, .

Time elapsed: 5 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 86 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-00
lola: result : false
lola: markings : 50759
lola: fired transitions : 120016
lola: time used : 2.000000
lola: memory pages used : 1
lola: LAUNCH task # 76 (type EXCL) for 27 SimpleLoadBal-PT-05-ReachabilityCardinality-09
lola: time limit : 3594 sec
lola: memory limit: 32 pages
lola: FINISHED task # 75 (type SRCH) for SimpleLoadBal-PT-05-ReachabilityCardinality-09
lola: result : false
lola: markings : 97314
lola: fired transitions : 305448
lola: time used : 2.000000
lola: memory pages used : 1
lola: CANCELED task # 72 (type FNDP) for SimpleLoadBal-PT-05-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 73 (type EQUN) for SimpleLoadBal-PT-05-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 76 (type EXCL) for SimpleLoadBal-PT-05-ReachabilityCardinality-09 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SimpleLoadBal-PT-05-ReachabilityCardinality-00: AG true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-01: AG true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-02: AG true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-03: EF true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-04: AG true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-05: EF false tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-06: EF false tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-07: AG true tandem / insertion
SimpleLoadBal-PT-05-ReachabilityCardinality-08: AG true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-09: EF false tandem / insertion
SimpleLoadBal-PT-05-ReachabilityCardinality-10: AG false tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-11: EF true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-12: AG true tandem / insertion
SimpleLoadBal-PT-05-ReachabilityCardinality-13: EF true tandem / relaxed
SimpleLoadBal-PT-05-ReachabilityCardinality-14: EF false tandem / insertion
SimpleLoadBal-PT-05-ReachabilityCardinality-15: EF true findpath


Time elapsed: 6 secs. Pages in use: 2

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SimpleLoadBal-PT-05"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SimpleLoadBal-PT-05, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-tajo-167905976800510"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SimpleLoadBal-PT-05.tgz
mv SimpleLoadBal-PT-05 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;