Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2023-input.r423-tajo-167905976700426.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.....................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SieveSingleMsgMbox-PT-d1m36, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-tajo-167905976700426
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 900K
-rw-r--r-- 1 mcc users 7.5K Feb 26 10:25 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Feb 26 10:25 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Feb 26 10:24 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 26 10:24 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 17:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 10:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 152K Feb 26 10:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 26 10:26 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 26 10:26 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 450K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-00
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-01
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-02
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-03
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-04
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-05
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-06
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-07
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-08
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-09
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-10
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-11
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-12
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-13
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-14
FORMULA_NAME SieveSingleMsgMbox-PT-d1m36-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679247300913

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SieveSingleMsgMbox-PT-d1m36
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 17:35:02] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 17:35:02] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 17:35:02] [INFO ] Load time of PNML (sax parser for PT used): 78 ms
[2023-03-19 17:35:02] [INFO ] Transformed 1295 places.
[2023-03-19 17:35:02] [INFO ] Transformed 749 transitions.
[2023-03-19 17:35:02] [INFO ] Parsed PT model containing 1295 places and 749 transitions and 2996 arcs in 144 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Deduced a syphon composed of 1036 places in 7 ms
Reduce places removed 1036 places and 0 transitions.
Support contains 60 out of 259 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 259/259 places, 749/749 transitions.
Reduce places removed 17 places and 0 transitions.
Ensure Unique test removed 240 transitions
Reduce isomorphic transitions removed 240 transitions.
Iterating post reduction 0 with 257 rules applied. Total rules applied 257 place count 242 transition count 509
Discarding 26 places :
Symmetric choice reduction at 1 with 26 rule applications. Total rules 283 place count 216 transition count 471
Iterating global reduction 1 with 26 rules applied. Total rules applied 309 place count 216 transition count 471
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 318 place count 216 transition count 462
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 327 place count 207 transition count 453
Iterating global reduction 2 with 9 rules applied. Total rules applied 336 place count 207 transition count 453
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 343 place count 200 transition count 446
Iterating global reduction 2 with 7 rules applied. Total rules applied 350 place count 200 transition count 446
Ensure Unique test removed 17 transitions
Reduce isomorphic transitions removed 17 transitions.
Iterating post reduction 2 with 17 rules applied. Total rules applied 367 place count 200 transition count 429
Applied a total of 367 rules in 57 ms. Remains 200 /259 variables (removed 59) and now considering 429/749 (removed 320) transitions.
// Phase 1: matrix 429 rows 200 cols
[2023-03-19 17:35:02] [INFO ] Computed 5 place invariants in 21 ms
[2023-03-19 17:35:03] [INFO ] Implicit Places using invariants in 262 ms returned []
[2023-03-19 17:35:03] [INFO ] Invariant cache hit.
[2023-03-19 17:35:03] [INFO ] State equation strengthened by 292 read => feed constraints.
[2023-03-19 17:35:03] [INFO ] Implicit Places using invariants and state equation in 679 ms returned []
Implicit Place search using SMT with State Equation took 965 ms to find 0 implicit places.
[2023-03-19 17:35:03] [INFO ] Invariant cache hit.
[2023-03-19 17:35:03] [INFO ] Dead Transitions using invariants and state equation in 164 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 200/259 places, 429/749 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1189 ms. Remains : 200/259 places, 429/749 transitions.
Support contains 60 out of 200 places after structural reductions.
[2023-03-19 17:35:04] [INFO ] Flatten gal took : 61 ms
[2023-03-19 17:35:04] [INFO ] Flatten gal took : 33 ms
[2023-03-19 17:35:04] [INFO ] Input system was already deterministic with 429 transitions.
Support contains 57 out of 200 places (down from 60) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2257 resets, run finished after 550 ms. (steps per millisecond=18 ) properties (out of 50) seen :3
Incomplete Best-First random walk after 1001 steps, including 47 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 49 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 36 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 50 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 50 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 48 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 104 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 38 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 45 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 47 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 44 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 47) seen :1
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 46 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 39 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 101 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 40 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 55 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 54 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 40 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 36 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 43 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 43 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 42 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 53 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 47 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 47 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 48 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 48 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 82 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 103 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 48 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1000 steps, including 45 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 48 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 38 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 48 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 46) seen :0
Interrupted probabilistic random walk after 197350 steps, run timeout after 3001 ms. (steps per millisecond=65 ) properties seen :{2=1, 4=1, 5=1, 6=1, 7=1, 8=1, 12=1, 17=1, 18=1, 19=1, 22=1, 23=1, 27=1, 30=1, 31=1, 33=1, 34=1, 35=1, 37=1, 42=1, 44=1}
Probabilistic random walk after 197350 steps, saw 92309 distinct states, run finished after 3003 ms. (steps per millisecond=65 ) properties seen :21
Running SMT prover for 25 properties.
[2023-03-19 17:35:08] [INFO ] Invariant cache hit.
[2023-03-19 17:35:08] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:35:08] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 5 ms returned sat
[2023-03-19 17:35:09] [INFO ] After 808ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:22
[2023-03-19 17:35:09] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:35:09] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 5 ms returned sat
[2023-03-19 17:35:10] [INFO ] After 1121ms SMT Verify possible using state equation in natural domain returned unsat :6 sat :19
[2023-03-19 17:35:10] [INFO ] State equation strengthened by 292 read => feed constraints.
[2023-03-19 17:35:12] [INFO ] After 1918ms SMT Verify possible using 292 Read/Feed constraints in natural domain returned unsat :6 sat :19
[2023-03-19 17:35:12] [INFO ] Deduced a trap composed of 73 places in 71 ms of which 6 ms to minimize.
[2023-03-19 17:35:12] [INFO ] Deduced a trap composed of 94 places in 74 ms of which 2 ms to minimize.
[2023-03-19 17:35:12] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 223 ms
[2023-03-19 17:35:13] [INFO ] Deduced a trap composed of 28 places in 37 ms of which 2 ms to minimize.
[2023-03-19 17:35:13] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 91 ms
[2023-03-19 17:35:15] [INFO ] After 4484ms SMT Verify possible using trap constraints in natural domain returned unsat :6 sat :19
Attempting to minimize the solution found.
Minimization took 1682 ms.
[2023-03-19 17:35:16] [INFO ] After 7478ms SMT Verify possible using all constraints in natural domain returned unsat :6 sat :19
Fused 25 Parikh solutions to 19 different solutions.
Parikh walk visited 1 properties in 1041 ms.
Support contains 23 out of 200 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 200/200 places, 429/429 transitions.
Graph (complete) has 740 edges and 200 vertex of which 199 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 3 place count 199 transition count 427
Discarding 21 places :
Symmetric choice reduction at 1 with 21 rule applications. Total rules 24 place count 178 transition count 301
Iterating global reduction 1 with 21 rules applied. Total rules applied 45 place count 178 transition count 301
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 48 place count 178 transition count 298
Discarding 19 places :
Symmetric choice reduction at 2 with 19 rule applications. Total rules 67 place count 159 transition count 276
Iterating global reduction 2 with 19 rules applied. Total rules applied 86 place count 159 transition count 276
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 2 with 18 rules applied. Total rules applied 104 place count 159 transition count 258
Discarding 8 places :
Symmetric choice reduction at 3 with 8 rule applications. Total rules 112 place count 151 transition count 248
Iterating global reduction 3 with 8 rules applied. Total rules applied 120 place count 151 transition count 248
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 3 with 9 rules applied. Total rules applied 129 place count 151 transition count 239
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 131 place count 149 transition count 237
Iterating global reduction 4 with 2 rules applied. Total rules applied 133 place count 149 transition count 237
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 135 place count 147 transition count 235
Iterating global reduction 4 with 2 rules applied. Total rules applied 137 place count 147 transition count 235
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 138 place count 146 transition count 234
Iterating global reduction 4 with 1 rules applied. Total rules applied 139 place count 146 transition count 234
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 140 place count 145 transition count 233
Iterating global reduction 4 with 1 rules applied. Total rules applied 141 place count 145 transition count 233
Applied a total of 141 rules in 62 ms. Remains 145 /200 variables (removed 55) and now considering 233/429 (removed 196) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 62 ms. Remains : 145/200 places, 233/429 transitions.
Incomplete random walk after 10000 steps, including 2262 resets, run finished after 247 ms. (steps per millisecond=40 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 48 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 52 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 109 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1000 steps, including 49 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 50 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 50 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 104 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 53 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 52 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 45 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 42 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1000 steps, including 48 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 108 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 41 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1000 steps, including 47 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 47 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 18) seen :0
Interrupted probabilistic random walk after 272674 steps, run timeout after 3001 ms. (steps per millisecond=90 ) properties seen :{}
Probabilistic random walk after 272674 steps, saw 118982 distinct states, run finished after 3003 ms. (steps per millisecond=90 ) properties seen :0
Running SMT prover for 18 properties.
// Phase 1: matrix 233 rows 145 cols
[2023-03-19 17:35:21] [INFO ] Computed 4 place invariants in 7 ms
[2023-03-19 17:35:21] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:35:21] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 17:35:21] [INFO ] After 584ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:18
[2023-03-19 17:35:22] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:35:22] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 5 ms returned sat
[2023-03-19 17:35:22] [INFO ] After 655ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :18
[2023-03-19 17:35:22] [INFO ] State equation strengthened by 133 read => feed constraints.
[2023-03-19 17:35:23] [INFO ] After 997ms SMT Verify possible using 133 Read/Feed constraints in natural domain returned unsat :0 sat :18
[2023-03-19 17:35:23] [INFO ] Deduced a trap composed of 20 places in 78 ms of which 1 ms to minimize.
[2023-03-19 17:35:24] [INFO ] Deduced a trap composed of 54 places in 48 ms of which 0 ms to minimize.
[2023-03-19 17:35:24] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 209 ms
[2023-03-19 17:35:25] [INFO ] After 2569ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :18
Attempting to minimize the solution found.
Minimization took 1463 ms.
[2023-03-19 17:35:26] [INFO ] After 4860ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :18
Parikh walk visited 1 properties in 544 ms.
Support contains 22 out of 145 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 145/145 places, 233/233 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 144 transition count 232
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 144 transition count 232
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 143 transition count 231
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 143 transition count 231
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 6 place count 143 transition count 229
Applied a total of 6 rules in 23 ms. Remains 143 /145 variables (removed 2) and now considering 229/233 (removed 4) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 23 ms. Remains : 143/145 places, 229/233 transitions.
Incomplete random walk after 10000 steps, including 2255 resets, run finished after 174 ms. (steps per millisecond=57 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 46 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 58 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 53 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 96 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 57 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 48 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 36 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 109 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 40 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 50 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 40 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 41 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 38 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 96 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 48 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Interrupted probabilistic random walk after 526304 steps, run timeout after 3001 ms. (steps per millisecond=175 ) properties seen :{}
Probabilistic random walk after 526304 steps, saw 227434 distinct states, run finished after 3001 ms. (steps per millisecond=175 ) properties seen :0
Running SMT prover for 17 properties.
// Phase 1: matrix 229 rows 143 cols
[2023-03-19 17:35:30] [INFO ] Computed 4 place invariants in 16 ms
[2023-03-19 17:35:30] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:35:30] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 17:35:31] [INFO ] After 590ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:17
[2023-03-19 17:35:31] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:35:31] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 17:35:31] [INFO ] After 458ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :17
[2023-03-19 17:35:31] [INFO ] State equation strengthened by 130 read => feed constraints.
[2023-03-19 17:35:32] [INFO ] After 769ms SMT Verify possible using 130 Read/Feed constraints in natural domain returned unsat :0 sat :17
[2023-03-19 17:35:32] [INFO ] Deduced a trap composed of 20 places in 65 ms of which 1 ms to minimize.
[2023-03-19 17:35:32] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 100 ms
[2023-03-19 17:35:33] [INFO ] After 1993ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :17
Attempting to minimize the solution found.
Minimization took 798 ms.
[2023-03-19 17:35:34] [INFO ] After 3394ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :17
Parikh walk visited 0 properties in 496 ms.
Support contains 22 out of 143 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 143/143 places, 229/229 transitions.
Applied a total of 0 rules in 9 ms. Remains 143 /143 variables (removed 0) and now considering 229/229 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 9 ms. Remains : 143/143 places, 229/229 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 143/143 places, 229/229 transitions.
Applied a total of 0 rules in 9 ms. Remains 143 /143 variables (removed 0) and now considering 229/229 (removed 0) transitions.
[2023-03-19 17:35:35] [INFO ] Invariant cache hit.
[2023-03-19 17:35:35] [INFO ] Implicit Places using invariants in 102 ms returned []
[2023-03-19 17:35:35] [INFO ] Invariant cache hit.
[2023-03-19 17:35:35] [INFO ] State equation strengthened by 130 read => feed constraints.
[2023-03-19 17:35:36] [INFO ] Implicit Places using invariants and state equation in 928 ms returned []
Implicit Place search using SMT with State Equation took 1034 ms to find 0 implicit places.
[2023-03-19 17:35:36] [INFO ] Redundant transitions in 7 ms returned []
[2023-03-19 17:35:36] [INFO ] Invariant cache hit.
[2023-03-19 17:35:36] [INFO ] Dead Transitions using invariants and state equation in 93 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1172 ms. Remains : 143/143 places, 229/229 transitions.
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 143 transition count 226
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 5 place count 141 transition count 226
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 13 Pre rules applied. Total rules applied 5 place count 141 transition count 213
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 2 with 26 rules applied. Total rules applied 31 place count 128 transition count 213
Performed 17 Post agglomeration using F-continuation condition.Transition count delta: 17
Deduced a syphon composed of 17 places in 0 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 2 with 34 rules applied. Total rules applied 65 place count 111 transition count 196
Free-agglomeration rule applied 2 times.
Iterating global reduction 2 with 2 rules applied. Total rules applied 67 place count 111 transition count 194
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 69 place count 109 transition count 194
Applied a total of 69 rules in 24 ms. Remains 109 /143 variables (removed 34) and now considering 194/229 (removed 35) transitions.
Running SMT prover for 17 properties.
// Phase 1: matrix 194 rows 109 cols
[2023-03-19 17:35:36] [INFO ] Computed 4 place invariants in 1 ms
[2023-03-19 17:35:36] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:35:36] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:35:36] [INFO ] After 415ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:17
[2023-03-19 17:35:37] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:35:37] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:35:37] [INFO ] After 355ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :17
[2023-03-19 17:35:37] [INFO ] Deduced a trap composed of 40 places in 38 ms of which 0 ms to minimize.
[2023-03-19 17:35:37] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 55 ms
[2023-03-19 17:35:37] [INFO ] Deduced a trap composed of 12 places in 26 ms of which 0 ms to minimize.
[2023-03-19 17:35:37] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 38 ms
[2023-03-19 17:35:37] [INFO ] After 864ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :17
Attempting to minimize the solution found.
Minimization took 415 ms.
[2023-03-19 17:35:38] [INFO ] After 1378ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :17
Successfully simplified 6 atomic propositions for a total of 16 simplifications.
FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 25 ms
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 20 ms
[2023-03-19 17:35:38] [INFO ] Input system was already deterministic with 429 transitions.
Support contains 36 out of 200 places (down from 39) after GAL structural reductions.
FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 51 stabilizing places and 86 stable transitions
Graph (complete) has 815 edges and 200 vertex of which 199 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.6 ms
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 35 places :
Symmetric choice reduction at 0 with 35 rule applications. Total rules 35 place count 165 transition count 243
Iterating global reduction 0 with 35 rules applied. Total rules applied 70 place count 165 transition count 243
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 72 place count 165 transition count 241
Discarding 31 places :
Symmetric choice reduction at 1 with 31 rule applications. Total rules 103 place count 134 transition count 207
Iterating global reduction 1 with 31 rules applied. Total rules applied 134 place count 134 transition count 207
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 150 place count 134 transition count 191
Discarding 19 places :
Symmetric choice reduction at 2 with 19 rule applications. Total rules 169 place count 115 transition count 170
Iterating global reduction 2 with 19 rules applied. Total rules applied 188 place count 115 transition count 170
Ensure Unique test removed 17 transitions
Reduce isomorphic transitions removed 17 transitions.
Iterating post reduction 2 with 17 rules applied. Total rules applied 205 place count 115 transition count 153
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 210 place count 110 transition count 147
Iterating global reduction 3 with 5 rules applied. Total rules applied 215 place count 110 transition count 147
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 220 place count 105 transition count 142
Iterating global reduction 3 with 5 rules applied. Total rules applied 225 place count 105 transition count 142
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 229 place count 101 transition count 137
Iterating global reduction 3 with 4 rules applied. Total rules applied 233 place count 101 transition count 137
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 237 place count 101 transition count 133
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 241 place count 97 transition count 129
Iterating global reduction 4 with 4 rules applied. Total rules applied 245 place count 97 transition count 129
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 247 place count 95 transition count 127
Iterating global reduction 4 with 2 rules applied. Total rules applied 249 place count 95 transition count 127
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 250 place count 94 transition count 125
Iterating global reduction 4 with 1 rules applied. Total rules applied 251 place count 94 transition count 125
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 252 place count 93 transition count 124
Iterating global reduction 4 with 1 rules applied. Total rules applied 253 place count 93 transition count 124
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 254 place count 92 transition count 123
Iterating global reduction 4 with 1 rules applied. Total rules applied 255 place count 92 transition count 123
Applied a total of 255 rules in 26 ms. Remains 92 /200 variables (removed 108) and now considering 123/429 (removed 306) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 92/200 places, 123/429 transitions.
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 6 ms
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 6 ms
[2023-03-19 17:35:38] [INFO ] Input system was already deterministic with 123 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 38 places :
Symmetric choice reduction at 0 with 38 rule applications. Total rules 38 place count 162 transition count 217
Iterating global reduction 0 with 38 rules applied. Total rules applied 76 place count 162 transition count 217
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 79 place count 162 transition count 214
Discarding 33 places :
Symmetric choice reduction at 1 with 33 rule applications. Total rules 112 place count 129 transition count 178
Iterating global reduction 1 with 33 rules applied. Total rules applied 145 place count 129 transition count 178
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 160 place count 129 transition count 163
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 180 place count 109 transition count 141
Iterating global reduction 2 with 20 rules applied. Total rules applied 200 place count 109 transition count 141
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 213 place count 109 transition count 128
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 219 place count 103 transition count 121
Iterating global reduction 3 with 6 rules applied. Total rules applied 225 place count 103 transition count 121
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 231 place count 97 transition count 115
Iterating global reduction 3 with 6 rules applied. Total rules applied 237 place count 97 transition count 115
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 241 place count 93 transition count 110
Iterating global reduction 3 with 4 rules applied. Total rules applied 245 place count 93 transition count 110
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 247 place count 93 transition count 108
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 251 place count 89 transition count 104
Iterating global reduction 4 with 4 rules applied. Total rules applied 255 place count 89 transition count 104
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 257 place count 87 transition count 102
Iterating global reduction 4 with 2 rules applied. Total rules applied 259 place count 87 transition count 102
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 260 place count 86 transition count 100
Iterating global reduction 4 with 1 rules applied. Total rules applied 261 place count 86 transition count 100
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 262 place count 85 transition count 99
Iterating global reduction 4 with 1 rules applied. Total rules applied 263 place count 85 transition count 99
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 264 place count 84 transition count 98
Iterating global reduction 4 with 1 rules applied. Total rules applied 265 place count 84 transition count 98
Applied a total of 265 rules in 41 ms. Remains 84 /200 variables (removed 116) and now considering 98/429 (removed 331) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 42 ms. Remains : 84/200 places, 98/429 transitions.
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:35:38] [INFO ] Input system was already deterministic with 98 transitions.
Incomplete random walk after 10000 steps, including 2236 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 468 resets, run finished after 10 ms. (steps per millisecond=1000 ) properties (out of 1) seen :0
Finished probabilistic random walk after 3856 steps, run visited all 1 properties in 19 ms. (steps per millisecond=202 )
Probabilistic random walk after 3856 steps, saw 1737 distinct states, run finished after 19 ms. (steps per millisecond=202 ) properties seen :1
FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-02 FALSE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 38 places :
Symmetric choice reduction at 0 with 38 rule applications. Total rules 38 place count 162 transition count 217
Iterating global reduction 0 with 38 rules applied. Total rules applied 76 place count 162 transition count 217
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 79 place count 162 transition count 214
Discarding 33 places :
Symmetric choice reduction at 1 with 33 rule applications. Total rules 112 place count 129 transition count 178
Iterating global reduction 1 with 33 rules applied. Total rules applied 145 place count 129 transition count 178
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 160 place count 129 transition count 163
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 180 place count 109 transition count 141
Iterating global reduction 2 with 20 rules applied. Total rules applied 200 place count 109 transition count 141
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 213 place count 109 transition count 128
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 219 place count 103 transition count 121
Iterating global reduction 3 with 6 rules applied. Total rules applied 225 place count 103 transition count 121
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 231 place count 97 transition count 115
Iterating global reduction 3 with 6 rules applied. Total rules applied 237 place count 97 transition count 115
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 241 place count 93 transition count 110
Iterating global reduction 3 with 4 rules applied. Total rules applied 245 place count 93 transition count 110
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 247 place count 93 transition count 108
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 251 place count 89 transition count 104
Iterating global reduction 4 with 4 rules applied. Total rules applied 255 place count 89 transition count 104
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 257 place count 87 transition count 102
Iterating global reduction 4 with 2 rules applied. Total rules applied 259 place count 87 transition count 102
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 260 place count 86 transition count 100
Iterating global reduction 4 with 1 rules applied. Total rules applied 261 place count 86 transition count 100
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 262 place count 85 transition count 99
Iterating global reduction 4 with 1 rules applied. Total rules applied 263 place count 85 transition count 99
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 264 place count 84 transition count 98
Iterating global reduction 4 with 1 rules applied. Total rules applied 265 place count 84 transition count 98
Applied a total of 265 rules in 37 ms. Remains 84 /200 variables (removed 116) and now considering 98/429 (removed 331) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 37 ms. Remains : 84/200 places, 98/429 transitions.
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:35:38] [INFO ] Input system was already deterministic with 98 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 36 places :
Symmetric choice reduction at 0 with 36 rule applications. Total rules 36 place count 164 transition count 210
Iterating global reduction 0 with 36 rules applied. Total rules applied 72 place count 164 transition count 210
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 75 place count 164 transition count 207
Discarding 32 places :
Symmetric choice reduction at 1 with 32 rule applications. Total rules 107 place count 132 transition count 172
Iterating global reduction 1 with 32 rules applied. Total rules applied 139 place count 132 transition count 172
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 1 with 14 rules applied. Total rules applied 153 place count 132 transition count 158
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 173 place count 112 transition count 136
Iterating global reduction 2 with 20 rules applied. Total rules applied 193 place count 112 transition count 136
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 2 with 11 rules applied. Total rules applied 204 place count 112 transition count 125
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 210 place count 106 transition count 119
Iterating global reduction 3 with 6 rules applied. Total rules applied 216 place count 106 transition count 119
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 222 place count 100 transition count 113
Iterating global reduction 3 with 6 rules applied. Total rules applied 228 place count 100 transition count 113
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 232 place count 96 transition count 108
Iterating global reduction 3 with 4 rules applied. Total rules applied 236 place count 96 transition count 108
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 238 place count 96 transition count 106
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 242 place count 92 transition count 102
Iterating global reduction 4 with 4 rules applied. Total rules applied 246 place count 92 transition count 102
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 247 place count 91 transition count 101
Iterating global reduction 4 with 1 rules applied. Total rules applied 248 place count 91 transition count 101
Applied a total of 248 rules in 20 ms. Remains 91 /200 variables (removed 109) and now considering 101/429 (removed 328) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 91/200 places, 101/429 transitions.
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:35:38] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 37 places :
Symmetric choice reduction at 0 with 37 rule applications. Total rules 37 place count 163 transition count 229
Iterating global reduction 0 with 37 rules applied. Total rules applied 74 place count 163 transition count 229
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 77 place count 163 transition count 226
Discarding 32 places :
Symmetric choice reduction at 1 with 32 rule applications. Total rules 109 place count 131 transition count 191
Iterating global reduction 1 with 32 rules applied. Total rules applied 141 place count 131 transition count 191
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 156 place count 131 transition count 176
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 174 place count 113 transition count 157
Iterating global reduction 2 with 18 rules applied. Total rules applied 192 place count 113 transition count 157
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 205 place count 113 transition count 144
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 210 place count 108 transition count 138
Iterating global reduction 3 with 5 rules applied. Total rules applied 215 place count 108 transition count 138
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 220 place count 103 transition count 133
Iterating global reduction 3 with 5 rules applied. Total rules applied 225 place count 103 transition count 133
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 228 place count 100 transition count 129
Iterating global reduction 3 with 3 rules applied. Total rules applied 231 place count 100 transition count 129
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 234 place count 97 transition count 126
Iterating global reduction 3 with 3 rules applied. Total rules applied 237 place count 97 transition count 126
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 239 place count 95 transition count 124
Iterating global reduction 3 with 2 rules applied. Total rules applied 241 place count 95 transition count 124
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 242 place count 94 transition count 122
Iterating global reduction 3 with 1 rules applied. Total rules applied 243 place count 94 transition count 122
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 244 place count 93 transition count 121
Iterating global reduction 3 with 1 rules applied. Total rules applied 245 place count 93 transition count 121
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 246 place count 92 transition count 120
Iterating global reduction 3 with 1 rules applied. Total rules applied 247 place count 92 transition count 120
Applied a total of 247 rules in 36 ms. Remains 92 /200 variables (removed 108) and now considering 120/429 (removed 309) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 36 ms. Remains : 92/200 places, 120/429 transitions.
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:35:38] [INFO ] Input system was already deterministic with 120 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 34 places :
Symmetric choice reduction at 0 with 34 rule applications. Total rules 34 place count 166 transition count 255
Iterating global reduction 0 with 34 rules applied. Total rules applied 68 place count 166 transition count 255
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 70 place count 166 transition count 253
Discarding 30 places :
Symmetric choice reduction at 1 with 30 rule applications. Total rules 100 place count 136 transition count 220
Iterating global reduction 1 with 30 rules applied. Total rules applied 130 place count 136 transition count 220
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 146 place count 136 transition count 204
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 164 place count 118 transition count 184
Iterating global reduction 2 with 18 rules applied. Total rules applied 182 place count 118 transition count 184
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 2 with 18 rules applied. Total rules applied 200 place count 118 transition count 166
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 204 place count 114 transition count 161
Iterating global reduction 3 with 4 rules applied. Total rules applied 208 place count 114 transition count 161
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 212 place count 110 transition count 157
Iterating global reduction 3 with 4 rules applied. Total rules applied 216 place count 110 transition count 157
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 219 place count 107 transition count 153
Iterating global reduction 3 with 3 rules applied. Total rules applied 222 place count 107 transition count 153
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 225 place count 104 transition count 150
Iterating global reduction 3 with 3 rules applied. Total rules applied 228 place count 104 transition count 150
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 230 place count 102 transition count 148
Iterating global reduction 3 with 2 rules applied. Total rules applied 232 place count 102 transition count 148
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 233 place count 101 transition count 146
Iterating global reduction 3 with 1 rules applied. Total rules applied 234 place count 101 transition count 146
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 235 place count 100 transition count 145
Iterating global reduction 3 with 1 rules applied. Total rules applied 236 place count 100 transition count 145
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 237 place count 99 transition count 144
Iterating global reduction 3 with 1 rules applied. Total rules applied 238 place count 99 transition count 144
Applied a total of 238 rules in 46 ms. Remains 99 /200 variables (removed 101) and now considering 144/429 (removed 285) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 47 ms. Remains : 99/200 places, 144/429 transitions.
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 6 ms
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 6 ms
[2023-03-19 17:35:38] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 38 places :
Symmetric choice reduction at 0 with 38 rule applications. Total rules 38 place count 162 transition count 206
Iterating global reduction 0 with 38 rules applied. Total rules applied 76 place count 162 transition count 206
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 79 place count 162 transition count 203
Discarding 33 places :
Symmetric choice reduction at 1 with 33 rule applications. Total rules 112 place count 129 transition count 167
Iterating global reduction 1 with 33 rules applied. Total rules applied 145 place count 129 transition count 167
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 1 with 14 rules applied. Total rules applied 159 place count 129 transition count 153
Discarding 21 places :
Symmetric choice reduction at 2 with 21 rule applications. Total rules 180 place count 108 transition count 130
Iterating global reduction 2 with 21 rules applied. Total rules applied 201 place count 108 transition count 130
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 213 place count 108 transition count 118
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 219 place count 102 transition count 112
Iterating global reduction 3 with 6 rules applied. Total rules applied 225 place count 102 transition count 112
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 231 place count 96 transition count 106
Iterating global reduction 3 with 6 rules applied. Total rules applied 237 place count 96 transition count 106
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 241 place count 92 transition count 101
Iterating global reduction 3 with 4 rules applied. Total rules applied 245 place count 92 transition count 101
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 247 place count 92 transition count 99
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 251 place count 88 transition count 95
Iterating global reduction 4 with 4 rules applied. Total rules applied 255 place count 88 transition count 95
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 256 place count 87 transition count 94
Iterating global reduction 4 with 1 rules applied. Total rules applied 257 place count 87 transition count 94
Applied a total of 257 rules in 18 ms. Remains 87 /200 variables (removed 113) and now considering 94/429 (removed 335) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 87/200 places, 94/429 transitions.
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:35:38] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 34 places :
Symmetric choice reduction at 0 with 34 rule applications. Total rules 34 place count 166 transition count 249
Iterating global reduction 0 with 34 rules applied. Total rules applied 68 place count 166 transition count 249
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 71 place count 166 transition count 246
Discarding 29 places :
Symmetric choice reduction at 1 with 29 rule applications. Total rules 100 place count 137 transition count 214
Iterating global reduction 1 with 29 rules applied. Total rules applied 129 place count 137 transition count 214
Ensure Unique test removed 20 transitions
Reduce isomorphic transitions removed 20 transitions.
Iterating post reduction 1 with 20 rules applied. Total rules applied 149 place count 137 transition count 194
Discarding 17 places :
Symmetric choice reduction at 2 with 17 rule applications. Total rules 166 place count 120 transition count 175
Iterating global reduction 2 with 17 rules applied. Total rules applied 183 place count 120 transition count 175
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 2 with 14 rules applied. Total rules applied 197 place count 120 transition count 161
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 202 place count 115 transition count 155
Iterating global reduction 3 with 5 rules applied. Total rules applied 207 place count 115 transition count 155
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 212 place count 110 transition count 150
Iterating global reduction 3 with 5 rules applied. Total rules applied 217 place count 110 transition count 150
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 220 place count 107 transition count 146
Iterating global reduction 3 with 3 rules applied. Total rules applied 223 place count 107 transition count 146
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 225 place count 105 transition count 144
Iterating global reduction 3 with 2 rules applied. Total rules applied 227 place count 105 transition count 144
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 228 place count 104 transition count 143
Iterating global reduction 3 with 1 rules applied. Total rules applied 229 place count 104 transition count 143
Applied a total of 229 rules in 17 ms. Remains 104 /200 variables (removed 96) and now considering 143/429 (removed 286) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 104/200 places, 143/429 transitions.
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:35:38] [INFO ] Input system was already deterministic with 143 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 30 place count 170 transition count 280
Iterating global reduction 0 with 30 rules applied. Total rules applied 60 place count 170 transition count 280
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 63 place count 170 transition count 277
Discarding 25 places :
Symmetric choice reduction at 1 with 25 rule applications. Total rules 88 place count 145 transition count 249
Iterating global reduction 1 with 25 rules applied. Total rules applied 113 place count 145 transition count 249
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 129 place count 145 transition count 233
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 141 place count 133 transition count 220
Iterating global reduction 2 with 12 rules applied. Total rules applied 153 place count 133 transition count 220
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 2 with 19 rules applied. Total rules applied 172 place count 133 transition count 201
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 174 place count 131 transition count 199
Iterating global reduction 3 with 2 rules applied. Total rules applied 176 place count 131 transition count 199
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 178 place count 129 transition count 197
Iterating global reduction 3 with 2 rules applied. Total rules applied 180 place count 129 transition count 197
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 181 place count 128 transition count 196
Iterating global reduction 3 with 1 rules applied. Total rules applied 182 place count 128 transition count 196
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 183 place count 127 transition count 195
Iterating global reduction 3 with 1 rules applied. Total rules applied 184 place count 127 transition count 195
Applied a total of 184 rules in 17 ms. Remains 127 /200 variables (removed 73) and now considering 195/429 (removed 234) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 127/200 places, 195/429 transitions.
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:35:38] [INFO ] Flatten gal took : 6 ms
[2023-03-19 17:35:39] [INFO ] Input system was already deterministic with 195 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 38 places :
Symmetric choice reduction at 0 with 38 rule applications. Total rules 38 place count 162 transition count 217
Iterating global reduction 0 with 38 rules applied. Total rules applied 76 place count 162 transition count 217
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 79 place count 162 transition count 214
Discarding 33 places :
Symmetric choice reduction at 1 with 33 rule applications. Total rules 112 place count 129 transition count 178
Iterating global reduction 1 with 33 rules applied. Total rules applied 145 place count 129 transition count 178
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 160 place count 129 transition count 163
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 180 place count 109 transition count 141
Iterating global reduction 2 with 20 rules applied. Total rules applied 200 place count 109 transition count 141
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 213 place count 109 transition count 128
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 219 place count 103 transition count 121
Iterating global reduction 3 with 6 rules applied. Total rules applied 225 place count 103 transition count 121
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 231 place count 97 transition count 115
Iterating global reduction 3 with 6 rules applied. Total rules applied 237 place count 97 transition count 115
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 241 place count 93 transition count 110
Iterating global reduction 3 with 4 rules applied. Total rules applied 245 place count 93 transition count 110
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 247 place count 93 transition count 108
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 251 place count 89 transition count 104
Iterating global reduction 4 with 4 rules applied. Total rules applied 255 place count 89 transition count 104
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 257 place count 87 transition count 102
Iterating global reduction 4 with 2 rules applied. Total rules applied 259 place count 87 transition count 102
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 260 place count 86 transition count 100
Iterating global reduction 4 with 1 rules applied. Total rules applied 261 place count 86 transition count 100
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 262 place count 85 transition count 99
Iterating global reduction 4 with 1 rules applied. Total rules applied 263 place count 85 transition count 99
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 264 place count 84 transition count 98
Iterating global reduction 4 with 1 rules applied. Total rules applied 265 place count 84 transition count 98
Applied a total of 265 rules in 28 ms. Remains 84 /200 variables (removed 116) and now considering 98/429 (removed 331) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 84/200 places, 98/429 transitions.
[2023-03-19 17:35:39] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:35:39] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:35:39] [INFO ] Input system was already deterministic with 98 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 39 places :
Symmetric choice reduction at 0 with 39 rule applications. Total rules 39 place count 161 transition count 205
Iterating global reduction 0 with 39 rules applied. Total rules applied 78 place count 161 transition count 205
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 81 place count 161 transition count 202
Discarding 34 places :
Symmetric choice reduction at 1 with 34 rule applications. Total rules 115 place count 127 transition count 165
Iterating global reduction 1 with 34 rules applied. Total rules applied 149 place count 127 transition count 165
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 164 place count 127 transition count 150
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 184 place count 107 transition count 128
Iterating global reduction 2 with 20 rules applied. Total rules applied 204 place count 107 transition count 128
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 2 with 11 rules applied. Total rules applied 215 place count 107 transition count 117
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 221 place count 101 transition count 110
Iterating global reduction 3 with 6 rules applied. Total rules applied 227 place count 101 transition count 110
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 233 place count 95 transition count 104
Iterating global reduction 3 with 6 rules applied. Total rules applied 239 place count 95 transition count 104
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 243 place count 91 transition count 99
Iterating global reduction 3 with 4 rules applied. Total rules applied 247 place count 91 transition count 99
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 248 place count 91 transition count 98
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 252 place count 87 transition count 94
Iterating global reduction 4 with 4 rules applied. Total rules applied 256 place count 87 transition count 94
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 257 place count 86 transition count 93
Iterating global reduction 4 with 1 rules applied. Total rules applied 258 place count 86 transition count 93
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 259 place count 85 transition count 91
Iterating global reduction 4 with 1 rules applied. Total rules applied 260 place count 85 transition count 91
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 261 place count 84 transition count 90
Iterating global reduction 4 with 1 rules applied. Total rules applied 262 place count 84 transition count 90
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 263 place count 83 transition count 89
Iterating global reduction 4 with 1 rules applied. Total rules applied 264 place count 83 transition count 89
Applied a total of 264 rules in 27 ms. Remains 83 /200 variables (removed 117) and now considering 89/429 (removed 340) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 83/200 places, 89/429 transitions.
[2023-03-19 17:35:39] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:35:39] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:35:39] [INFO ] Input system was already deterministic with 89 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 39 places :
Symmetric choice reduction at 0 with 39 rule applications. Total rules 39 place count 161 transition count 205
Iterating global reduction 0 with 39 rules applied. Total rules applied 78 place count 161 transition count 205
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 81 place count 161 transition count 202
Discarding 33 places :
Symmetric choice reduction at 1 with 33 rule applications. Total rules 114 place count 128 transition count 166
Iterating global reduction 1 with 33 rules applied. Total rules applied 147 place count 128 transition count 166
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 1 with 14 rules applied. Total rules applied 161 place count 128 transition count 152
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 181 place count 108 transition count 130
Iterating global reduction 2 with 20 rules applied. Total rules applied 201 place count 108 transition count 130
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 2 with 11 rules applied. Total rules applied 212 place count 108 transition count 119
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 218 place count 102 transition count 112
Iterating global reduction 3 with 6 rules applied. Total rules applied 224 place count 102 transition count 112
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 230 place count 96 transition count 106
Iterating global reduction 3 with 6 rules applied. Total rules applied 236 place count 96 transition count 106
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 240 place count 92 transition count 101
Iterating global reduction 3 with 4 rules applied. Total rules applied 244 place count 92 transition count 101
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 245 place count 92 transition count 100
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 249 place count 88 transition count 96
Iterating global reduction 4 with 4 rules applied. Total rules applied 253 place count 88 transition count 96
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 255 place count 86 transition count 94
Iterating global reduction 4 with 2 rules applied. Total rules applied 257 place count 86 transition count 94
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 258 place count 85 transition count 92
Iterating global reduction 4 with 1 rules applied. Total rules applied 259 place count 85 transition count 92
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 260 place count 84 transition count 91
Iterating global reduction 4 with 1 rules applied. Total rules applied 261 place count 84 transition count 91
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 262 place count 83 transition count 90
Iterating global reduction 4 with 1 rules applied. Total rules applied 263 place count 83 transition count 90
Applied a total of 263 rules in 23 ms. Remains 83 /200 variables (removed 117) and now considering 90/429 (removed 339) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 83/200 places, 90/429 transitions.
[2023-03-19 17:35:39] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:35:39] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:35:39] [INFO ] Input system was already deterministic with 90 transitions.
Incomplete random walk after 10000 steps, including 2246 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 1068 resets, run finished after 9 ms. (steps per millisecond=1111 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2539445 steps, run timeout after 3001 ms. (steps per millisecond=846 ) properties seen :{}
Probabilistic random walk after 2539445 steps, saw 1064505 distinct states, run finished after 3001 ms. (steps per millisecond=846 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 90 rows 83 cols
[2023-03-19 17:35:42] [INFO ] Computed 5 place invariants in 3 ms
[2023-03-19 17:35:42] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:35:42] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 2 ms returned sat
[2023-03-19 17:35:42] [INFO ] After 92ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:35:42] [INFO ] [Nat]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-03-19 17:35:42] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 1 ms returned sat
[2023-03-19 17:35:42] [INFO ] After 24ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:35:42] [INFO ] State equation strengthened by 36 read => feed constraints.
[2023-03-19 17:35:42] [INFO ] After 22ms SMT Verify possible using 36 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:35:42] [INFO ] After 36ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 8 ms.
[2023-03-19 17:35:42] [INFO ] After 104ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 19 ms.
Support contains 2 out of 83 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 90/90 transitions.
Graph (complete) has 230 edges and 83 vertex of which 82 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.0 ms
Discarding 1 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 3 place count 82 transition count 88
Applied a total of 3 rules in 2 ms. Remains 82 /83 variables (removed 1) and now considering 88/90 (removed 2) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2 ms. Remains : 82/83 places, 88/90 transitions.
Incomplete random walk after 1000000 steps, including 224380 resets, run finished after 1261 ms. (steps per millisecond=793 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000000 steps, including 103181 resets, run finished after 739 ms. (steps per millisecond=1353 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 5910722 steps, run timeout after 6001 ms. (steps per millisecond=984 ) properties seen :{}
Probabilistic random walk after 5910722 steps, saw 2465820 distinct states, run finished after 6001 ms. (steps per millisecond=984 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 88 rows 82 cols
[2023-03-19 17:35:50] [INFO ] Computed 4 place invariants in 2 ms
[2023-03-19 17:35:50] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:35:50] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 17:35:50] [INFO ] After 96ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:35:50] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:35:50] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 17:35:50] [INFO ] After 43ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:35:50] [INFO ] State equation strengthened by 34 read => feed constraints.
[2023-03-19 17:35:50] [INFO ] After 18ms SMT Verify possible using 34 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:35:50] [INFO ] After 28ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 9 ms.
[2023-03-19 17:35:50] [INFO ] After 148ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 21 ms.
Support contains 2 out of 82 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 82/82 places, 88/88 transitions.
Applied a total of 0 rules in 2 ms. Remains 82 /82 variables (removed 0) and now considering 88/88 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3 ms. Remains : 82/82 places, 88/88 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 82/82 places, 88/88 transitions.
Applied a total of 0 rules in 2 ms. Remains 82 /82 variables (removed 0) and now considering 88/88 (removed 0) transitions.
[2023-03-19 17:35:50] [INFO ] Invariant cache hit.
[2023-03-19 17:35:50] [INFO ] Implicit Places using invariants in 52 ms returned []
[2023-03-19 17:35:50] [INFO ] Invariant cache hit.
[2023-03-19 17:35:50] [INFO ] State equation strengthened by 34 read => feed constraints.
[2023-03-19 17:35:50] [INFO ] Implicit Places using invariants and state equation in 148 ms returned []
Implicit Place search using SMT with State Equation took 202 ms to find 0 implicit places.
[2023-03-19 17:35:50] [INFO ] Redundant transitions in 1 ms returned []
[2023-03-19 17:35:50] [INFO ] Invariant cache hit.
[2023-03-19 17:35:50] [INFO ] Dead Transitions using invariants and state equation in 70 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 283 ms. Remains : 82/82 places, 88/88 transitions.
Incomplete random walk after 100000 steps, including 22374 resets, run finished after 1181 ms. (steps per millisecond=84 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-19 17:35:52] [INFO ] Invariant cache hit.
[2023-03-19 17:35:52] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:35:52] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:35:52] [INFO ] After 22ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2
[2023-03-19 17:35:52] [INFO ] State equation strengthened by 34 read => feed constraints.
[2023-03-19 17:35:52] [INFO ] After 8ms SMT Verify possible using 34 Read/Feed constraints in real domain returned unsat :0 sat :2
[2023-03-19 17:35:52] [INFO ] After 25ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-19 17:35:52] [INFO ] After 90ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-19 17:35:52] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:35:52] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:35:52] [INFO ] After 21ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-19 17:35:52] [INFO ] After 8ms SMT Verify possible using 34 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-19 17:35:52] [INFO ] After 20ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 3 ms.
[2023-03-19 17:35:52] [INFO ] After 85ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Incomplete random walk after 1000000 steps, including 224245 resets, run finished after 1295 ms. (steps per millisecond=772 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000001 steps, including 103297 resets, run finished after 725 ms. (steps per millisecond=1379 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 5714213 steps, run timeout after 6001 ms. (steps per millisecond=952 ) properties seen :{}
Probabilistic random walk after 5714213 steps, saw 2384466 distinct states, run finished after 6001 ms. (steps per millisecond=952 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 17:36:00] [INFO ] Invariant cache hit.
[2023-03-19 17:36:00] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:00] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:00] [INFO ] After 86ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:00] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:00] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:00] [INFO ] After 41ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:00] [INFO ] State equation strengthened by 34 read => feed constraints.
[2023-03-19 17:36:00] [INFO ] After 17ms SMT Verify possible using 34 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:00] [INFO ] After 28ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 9 ms.
[2023-03-19 17:36:00] [INFO ] After 145ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 18 ms.
Support contains 2 out of 82 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 82/82 places, 88/88 transitions.
Applied a total of 0 rules in 3 ms. Remains 82 /82 variables (removed 0) and now considering 88/88 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3 ms. Remains : 82/82 places, 88/88 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 82/82 places, 88/88 transitions.
Applied a total of 0 rules in 2 ms. Remains 82 /82 variables (removed 0) and now considering 88/88 (removed 0) transitions.
[2023-03-19 17:36:00] [INFO ] Invariant cache hit.
[2023-03-19 17:36:00] [INFO ] Implicit Places using invariants in 67 ms returned []
[2023-03-19 17:36:00] [INFO ] Invariant cache hit.
[2023-03-19 17:36:00] [INFO ] State equation strengthened by 34 read => feed constraints.
[2023-03-19 17:36:00] [INFO ] Implicit Places using invariants and state equation in 107 ms returned []
Implicit Place search using SMT with State Equation took 202 ms to find 0 implicit places.
[2023-03-19 17:36:00] [INFO ] Redundant transitions in 1 ms returned []
[2023-03-19 17:36:00] [INFO ] Invariant cache hit.
[2023-03-19 17:36:00] [INFO ] Dead Transitions using invariants and state equation in 45 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 277 ms. Remains : 82/82 places, 88/88 transitions.
Incomplete random walk after 100000 steps, including 22349 resets, run finished after 1030 ms. (steps per millisecond=97 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-19 17:36:01] [INFO ] Invariant cache hit.
[2023-03-19 17:36:01] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:01] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:01] [INFO ] After 27ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2
[2023-03-19 17:36:01] [INFO ] State equation strengthened by 34 read => feed constraints.
[2023-03-19 17:36:01] [INFO ] After 10ms SMT Verify possible using 34 Read/Feed constraints in real domain returned unsat :0 sat :2
[2023-03-19 17:36:01] [INFO ] After 27ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-19 17:36:01] [INFO ] After 97ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-19 17:36:02] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:02] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:02] [INFO ] After 39ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-19 17:36:02] [INFO ] After 13ms SMT Verify possible using 34 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-19 17:36:02] [INFO ] After 34ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 4 ms.
[2023-03-19 17:36:02] [INFO ] After 126ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Incomplete random walk after 10000 steps, including 2251 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 1067 resets, run finished after 15 ms. (steps per millisecond=666 ) properties (out of 1) seen :0
Finished probabilistic random walk after 3795 steps, run visited all 1 properties in 10 ms. (steps per millisecond=379 )
Probabilistic random walk after 3795 steps, saw 1698 distinct states, run finished after 10 ms. (steps per millisecond=379 ) properties seen :1
Incomplete random walk after 10000 steps, including 2239 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 1061 resets, run finished after 15 ms. (steps per millisecond=666 ) properties (out of 1) seen :0
Finished probabilistic random walk after 3699 steps, run visited all 1 properties in 9 ms. (steps per millisecond=411 )
Probabilistic random walk after 3699 steps, saw 1634 distinct states, run finished after 10 ms. (steps per millisecond=369 ) properties seen :1
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 82 transition count 81
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 12 place count 77 transition count 81
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 13 Pre rules applied. Total rules applied 12 place count 77 transition count 68
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 2 with 26 rules applied. Total rules applied 38 place count 64 transition count 68
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 2 with 12 rules applied. Total rules applied 50 place count 58 transition count 62
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -5
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 52 place count 57 transition count 67
Applied a total of 52 rules in 11 ms. Remains 57 /82 variables (removed 25) and now considering 67/88 (removed 21) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 67 rows 57 cols
[2023-03-19 17:36:02] [INFO ] Computed 6 place invariants in 2 ms
[2023-03-19 17:36:02] [INFO ] [Real]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:02] [INFO ] [Real]Absence check using 4 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:02] [INFO ] After 64ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:02] [INFO ] [Nat]Absence check using 4 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:02] [INFO ] [Nat]Absence check using 4 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:02] [INFO ] After 21ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:02] [INFO ] After 27ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-19 17:36:02] [INFO ] After 89ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 38 places :
Symmetric choice reduction at 0 with 38 rule applications. Total rules 38 place count 162 transition count 217
Iterating global reduction 0 with 38 rules applied. Total rules applied 76 place count 162 transition count 217
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 79 place count 162 transition count 214
Discarding 33 places :
Symmetric choice reduction at 1 with 33 rule applications. Total rules 112 place count 129 transition count 178
Iterating global reduction 1 with 33 rules applied. Total rules applied 145 place count 129 transition count 178
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 160 place count 129 transition count 163
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 180 place count 109 transition count 141
Iterating global reduction 2 with 20 rules applied. Total rules applied 200 place count 109 transition count 141
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 213 place count 109 transition count 128
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 219 place count 103 transition count 121
Iterating global reduction 3 with 6 rules applied. Total rules applied 225 place count 103 transition count 121
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 231 place count 97 transition count 115
Iterating global reduction 3 with 6 rules applied. Total rules applied 237 place count 97 transition count 115
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 241 place count 93 transition count 110
Iterating global reduction 3 with 4 rules applied. Total rules applied 245 place count 93 transition count 110
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 247 place count 93 transition count 108
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 251 place count 89 transition count 104
Iterating global reduction 4 with 4 rules applied. Total rules applied 255 place count 89 transition count 104
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 257 place count 87 transition count 102
Iterating global reduction 4 with 2 rules applied. Total rules applied 259 place count 87 transition count 102
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 260 place count 86 transition count 100
Iterating global reduction 4 with 1 rules applied. Total rules applied 261 place count 86 transition count 100
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 262 place count 85 transition count 99
Iterating global reduction 4 with 1 rules applied. Total rules applied 263 place count 85 transition count 99
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 264 place count 84 transition count 98
Iterating global reduction 4 with 1 rules applied. Total rules applied 265 place count 84 transition count 98
Applied a total of 265 rules in 54 ms. Remains 84 /200 variables (removed 116) and now considering 98/429 (removed 331) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 56 ms. Remains : 84/200 places, 98/429 transitions.
[2023-03-19 17:36:02] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:36:02] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:36:02] [INFO ] Input system was already deterministic with 98 transitions.
Incomplete random walk after 10000 steps, including 2288 resets, run finished after 15 ms. (steps per millisecond=666 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 477 resets, run finished after 7 ms. (steps per millisecond=1428 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2526072 steps, run timeout after 3001 ms. (steps per millisecond=841 ) properties seen :{}
Probabilistic random walk after 2526072 steps, saw 1059030 distinct states, run finished after 3006 ms. (steps per millisecond=840 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 98 rows 84 cols
[2023-03-19 17:36:05] [INFO ] Computed 5 place invariants in 3 ms
[2023-03-19 17:36:05] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:05] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 2 ms returned sat
[2023-03-19 17:36:05] [INFO ] After 98ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:05] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:05] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 3 ms returned sat
[2023-03-19 17:36:05] [INFO ] After 50ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:05] [INFO ] State equation strengthened by 44 read => feed constraints.
[2023-03-19 17:36:05] [INFO ] After 22ms SMT Verify possible using 44 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:05] [INFO ] After 38ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 12 ms.
[2023-03-19 17:36:05] [INFO ] After 157ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 40 ms.
Support contains 2 out of 84 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 84/84 places, 98/98 transitions.
Graph (complete) has 238 edges and 84 vertex of which 83 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.0 ms
Discarding 1 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 3 place count 83 transition count 96
Applied a total of 3 rules in 3 ms. Remains 83 /84 variables (removed 1) and now considering 96/98 (removed 2) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3 ms. Remains : 83/84 places, 96/98 transitions.
Incomplete random walk after 1000000 steps, including 224005 resets, run finished after 1193 ms. (steps per millisecond=838 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000000 steps, including 47868 resets, run finished after 562 ms. (steps per millisecond=1779 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 3152183 steps, run timeout after 3001 ms. (steps per millisecond=1050 ) properties seen :{}
Probabilistic random walk after 3152183 steps, saw 1320936 distinct states, run finished after 3001 ms. (steps per millisecond=1050 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 96 rows 83 cols
[2023-03-19 17:36:10] [INFO ] Computed 4 place invariants in 2 ms
[2023-03-19 17:36:10] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:10] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:10] [INFO ] After 54ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:10] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:10] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 17:36:10] [INFO ] After 54ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:10] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:10] [INFO ] After 23ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:10] [INFO ] After 39ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 14 ms.
[2023-03-19 17:36:10] [INFO ] After 155ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 41 ms.
Support contains 2 out of 83 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2 ms. Remains : 83/83 places, 96/96 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
[2023-03-19 17:36:10] [INFO ] Invariant cache hit.
[2023-03-19 17:36:10] [INFO ] Implicit Places using invariants in 106 ms returned []
[2023-03-19 17:36:10] [INFO ] Invariant cache hit.
[2023-03-19 17:36:11] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:11] [INFO ] Implicit Places using invariants and state equation in 251 ms returned []
Implicit Place search using SMT with State Equation took 361 ms to find 0 implicit places.
[2023-03-19 17:36:11] [INFO ] Redundant transitions in 1 ms returned []
[2023-03-19 17:36:11] [INFO ] Invariant cache hit.
[2023-03-19 17:36:11] [INFO ] Dead Transitions using invariants and state equation in 102 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 477 ms. Remains : 83/83 places, 96/96 transitions.
Incomplete random walk after 100000 steps, including 22504 resets, run finished after 168 ms. (steps per millisecond=595 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-19 17:36:11] [INFO ] Invariant cache hit.
[2023-03-19 17:36:11] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:11] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 17:36:11] [INFO ] After 43ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 17:36:11] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:11] [INFO ] After 17ms SMT Verify possible using 42 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-19 17:36:11] [INFO ] After 31ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:11] [INFO ] After 131ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:11] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:11] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:11] [INFO ] After 31ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:11] [INFO ] After 27ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:11] [INFO ] After 50ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-19 17:36:11] [INFO ] After 122ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Incomplete random walk after 1000000 steps, including 224230 resets, run finished after 1302 ms. (steps per millisecond=768 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000000 steps, including 47747 resets, run finished after 460 ms. (steps per millisecond=2173 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 3031674 steps, run timeout after 3001 ms. (steps per millisecond=1010 ) properties seen :{}
Probabilistic random walk after 3031674 steps, saw 1269598 distinct states, run finished after 3001 ms. (steps per millisecond=1010 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 17:36:16] [INFO ] Invariant cache hit.
[2023-03-19 17:36:16] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:16] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:16] [INFO ] After 86ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:16] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:16] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:16] [INFO ] After 45ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:16] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:16] [INFO ] After 13ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:16] [INFO ] After 24ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 11 ms.
[2023-03-19 17:36:16] [INFO ] After 127ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 37 ms.
Support contains 2 out of 83 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2 ms. Remains : 83/83 places, 96/96 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
[2023-03-19 17:36:16] [INFO ] Invariant cache hit.
[2023-03-19 17:36:16] [INFO ] Implicit Places using invariants in 90 ms returned []
[2023-03-19 17:36:16] [INFO ] Invariant cache hit.
[2023-03-19 17:36:16] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:17] [INFO ] Implicit Places using invariants and state equation in 145 ms returned []
Implicit Place search using SMT with State Equation took 251 ms to find 0 implicit places.
[2023-03-19 17:36:17] [INFO ] Redundant transitions in 0 ms returned []
[2023-03-19 17:36:17] [INFO ] Invariant cache hit.
[2023-03-19 17:36:17] [INFO ] Dead Transitions using invariants and state equation in 57 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 338 ms. Remains : 83/83 places, 96/96 transitions.
Incomplete random walk after 100000 steps, including 22354 resets, run finished after 168 ms. (steps per millisecond=595 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-19 17:36:17] [INFO ] Invariant cache hit.
[2023-03-19 17:36:17] [INFO ] [Real]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-03-19 17:36:17] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:17] [INFO ] After 27ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 17:36:17] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:17] [INFO ] After 23ms SMT Verify possible using 42 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-19 17:36:17] [INFO ] After 29ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:17] [INFO ] After 101ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:17] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:17] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:17] [INFO ] After 33ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:17] [INFO ] After 25ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:17] [INFO ] After 36ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 2 ms.
[2023-03-19 17:36:17] [INFO ] After 112ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=1 )
Incomplete random walk after 10000 steps, including 2224 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 1096 resets, run finished after 10 ms. (steps per millisecond=1000 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2608238 steps, run timeout after 3001 ms. (steps per millisecond=869 ) properties seen :{}
Probabilistic random walk after 2608238 steps, saw 1091860 distinct states, run finished after 3001 ms. (steps per millisecond=869 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 17:36:20] [INFO ] Invariant cache hit.
[2023-03-19 17:36:20] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:20] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 17:36:20] [INFO ] After 38ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 17:36:20] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:20] [INFO ] After 19ms SMT Verify possible using 42 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:20] [INFO ] After 105ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:20] [INFO ] [Nat]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-03-19 17:36:20] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:20] [INFO ] After 21ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:20] [INFO ] After 14ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:20] [INFO ] After 21ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 4 ms.
[2023-03-19 17:36:20] [INFO ] After 77ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 83 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 1 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1 ms. Remains : 83/83 places, 96/96 transitions.
Incomplete random walk after 10000 steps, including 2255 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 992 resets, run finished after 8 ms. (steps per millisecond=1250 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2601740 steps, run timeout after 3001 ms. (steps per millisecond=866 ) properties seen :{}
Probabilistic random walk after 2601740 steps, saw 1089282 distinct states, run finished after 3002 ms. (steps per millisecond=866 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 17:36:23] [INFO ] Invariant cache hit.
[2023-03-19 17:36:23] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:23] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:23] [INFO ] After 38ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 17:36:23] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:23] [INFO ] After 18ms SMT Verify possible using 42 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:23] [INFO ] After 104ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:23] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:23] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:23] [INFO ] After 31ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:23] [INFO ] After 16ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:23] [INFO ] After 22ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-19 17:36:23] [INFO ] After 88ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 83 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3 ms. Remains : 83/83 places, 96/96 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
[2023-03-19 17:36:23] [INFO ] Invariant cache hit.
[2023-03-19 17:36:23] [INFO ] Implicit Places using invariants in 53 ms returned []
[2023-03-19 17:36:24] [INFO ] Invariant cache hit.
[2023-03-19 17:36:24] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:24] [INFO ] Implicit Places using invariants and state equation in 152 ms returned []
Implicit Place search using SMT with State Equation took 207 ms to find 0 implicit places.
[2023-03-19 17:36:24] [INFO ] Redundant transitions in 1 ms returned []
[2023-03-19 17:36:24] [INFO ] Invariant cache hit.
[2023-03-19 17:36:24] [INFO ] Dead Transitions using invariants and state equation in 56 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 271 ms. Remains : 83/83 places, 96/96 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 83 transition count 89
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 12 place count 78 transition count 89
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 13 Pre rules applied. Total rules applied 12 place count 78 transition count 76
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 2 with 26 rules applied. Total rules applied 38 place count 65 transition count 76
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 2 with 14 rules applied. Total rules applied 52 place count 58 transition count 69
Applied a total of 52 rules in 4 ms. Remains 58 /83 variables (removed 25) and now considering 69/96 (removed 27) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 69 rows 58 cols
[2023-03-19 17:36:24] [INFO ] Computed 5 place invariants in 3 ms
[2023-03-19 17:36:24] [INFO ] [Real]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-03-19 17:36:24] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:24] [INFO ] After 22ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 17:36:24] [INFO ] Deduced a trap composed of 32 places in 29 ms of which 1 ms to minimize.
[2023-03-19 17:36:24] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 35 ms
[2023-03-19 17:36:24] [INFO ] After 62ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:24] [INFO ] After 105ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:24] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:24] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:24] [INFO ] After 21ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:24] [INFO ] Deduced a trap composed of 32 places in 24 ms of which 0 ms to minimize.
[2023-03-19 17:36:24] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 30 ms
[2023-03-19 17:36:24] [INFO ] After 53ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 3 ms.
[2023-03-19 17:36:24] [INFO ] After 88ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 6 rules applied. Total rules applied 6 place count 83 transition count 90
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 11 place count 78 transition count 90
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 13 Pre rules applied. Total rules applied 11 place count 78 transition count 77
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 2 with 26 rules applied. Total rules applied 37 place count 65 transition count 77
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 2 with 14 rules applied. Total rules applied 51 place count 58 transition count 70
Applied a total of 51 rules in 6 ms. Remains 58 /83 variables (removed 25) and now considering 70/96 (removed 26) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 70 rows 58 cols
[2023-03-19 17:36:24] [INFO ] Computed 4 place invariants in 1 ms
[2023-03-19 17:36:24] [INFO ] [Real]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:24] [INFO ] [Real]Absence check using 3 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-19 17:36:24] [INFO ] After 69ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:24] [INFO ] [Nat]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:24] [INFO ] [Nat]Absence check using 3 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:24] [INFO ] After 26ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:24] [INFO ] After 35ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 7 ms.
[2023-03-19 17:36:24] [INFO ] After 74ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 429/429 transitions.
Discarding 31 places :
Symmetric choice reduction at 0 with 31 rule applications. Total rules 31 place count 169 transition count 250
Iterating global reduction 0 with 31 rules applied. Total rules applied 62 place count 169 transition count 250
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 63 place count 169 transition count 249
Discarding 27 places :
Symmetric choice reduction at 1 with 27 rule applications. Total rules 90 place count 142 transition count 219
Iterating global reduction 1 with 27 rules applied. Total rules applied 117 place count 142 transition count 219
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 1 with 13 rules applied. Total rules applied 130 place count 142 transition count 206
Discarding 17 places :
Symmetric choice reduction at 2 with 17 rule applications. Total rules 147 place count 125 transition count 186
Iterating global reduction 2 with 17 rules applied. Total rules applied 164 place count 125 transition count 186
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 2 with 15 rules applied. Total rules applied 179 place count 125 transition count 171
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 183 place count 121 transition count 165
Iterating global reduction 3 with 4 rules applied. Total rules applied 187 place count 121 transition count 165
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 191 place count 117 transition count 161
Iterating global reduction 3 with 4 rules applied. Total rules applied 195 place count 117 transition count 161
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 197 place count 115 transition count 159
Iterating global reduction 3 with 2 rules applied. Total rules applied 199 place count 115 transition count 159
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 200 place count 114 transition count 158
Iterating global reduction 3 with 1 rules applied. Total rules applied 201 place count 114 transition count 158
Applied a total of 201 rules in 11 ms. Remains 114 /200 variables (removed 86) and now considering 158/429 (removed 271) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 114/200 places, 158/429 transitions.
[2023-03-19 17:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-19 17:36:24] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:36:24] [INFO ] Input system was already deterministic with 158 transitions.
[2023-03-19 17:36:24] [INFO ] Flatten gal took : 14 ms
[2023-03-19 17:36:24] [INFO ] Flatten gal took : 14 ms
[2023-03-19 17:36:24] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 17:36:24] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 200 places, 429 transitions and 1698 arcs took 4 ms.
Total runtime 82233 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SieveSingleMsgMbox-PT-d1m36
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m36-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393356 kB
MemFree: 13166604 kB
After kill :
MemTotal: 16393356 kB
MemFree: 16230860 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 16 (type EXCL) for 15 SieveSingleMsgMbox-PT-d1m36-CTLFireability-07
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-07
lola: result : false
lola: markings : 1439
lola: fired transitions : 1764
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 19 (type EXCL) for 18 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 41 (type FNDP) for 33 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 42 (type EQUN) for 33 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 46 (type SRCH) for 33 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 46 (type SRCH) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-13
lola: result : unknown
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type FNDP) for 30 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/376/CTLFireability-42.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/299 3/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 539184 m, 107836 m/sec, 724571 t fired, .
39 EF FNDP 5/1799 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 424539 t fired, 31264 attempts, .
41 EF FNDP 5/1799 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 849415 t fired, 119198 attempts, .
42 EF STEQ 5/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 6 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/299 6/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 1083391 m, 108841 m/sec, 1488394 t fired, .
39 EF FNDP 10/1794 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 1093301 t fired, 80551 attempts, .
41 EF FNDP 10/1794 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 1696933 t fired, 237582 attempts, .
42 EF STEQ 10/3594 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 11 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/299 8/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 1676531 m, 118628 m/sec, 2292466 t fired, .
39 EF FNDP 15/1789 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 2027805 t fired, 149404 attempts, .
41 EF FNDP 15/1789 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 2318557 t fired, 324559 attempts, .
42 EF STEQ 15/3589 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 16 secs. Pages in use: 8
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/299 11/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 2247121 m, 114118 m/sec, 3105867 t fired, .
39 EF FNDP 20/1784 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 2991448 t fired, 220433 attempts, .
41 EF FNDP 20/1784 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 2953039 t fired, 413557 attempts, .
42 EF STEQ 20/3584 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 21 secs. Pages in use: 11
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/299 14/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 2823828 m, 115341 m/sec, 3908171 t fired, .
39 EF FNDP 25/1779 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 3958243 t fired, 291730 attempts, .
41 EF FNDP 25/1779 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 3423190 t fired, 479234 attempts, .
42 EF STEQ 25/3579 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 26 secs. Pages in use: 14
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/299 18/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 3621341 m, 159502 m/sec, 4986832 t fired, .
39 EF FNDP 30/1774 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 4888919 t fired, 360336 attempts, .
41 EF FNDP 30/1774 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 3916861 t fired, 548388 attempts, .
42 EF STEQ 30/3574 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 31 secs. Pages in use: 18
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/299 21/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 4268781 m, 129488 m/sec, 5884177 t fired, .
39 EF FNDP 35/1769 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 5843944 t fired, 430708 attempts, .
41 EF FNDP 35/1769 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 4384286 t fired, 613769 attempts, .
42 EF STEQ 35/3569 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 36 secs. Pages in use: 21
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 40/299 24/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 4892046 m, 124653 m/sec, 6742762 t fired, .
39 EF FNDP 40/1764 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 6754594 t fired, 497735 attempts, .
41 EF FNDP 40/1764 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 4826895 t fired, 675749 attempts, .
42 EF STEQ 40/3564 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 41 secs. Pages in use: 24
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 45/299 26/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 5425105 m, 106611 m/sec, 7542604 t fired, .
39 EF FNDP 45/1759 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 7669991 t fired, 565210 attempts, .
41 EF FNDP 45/1759 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 5258243 t fired, 736199 attempts, .
42 EF STEQ 45/3559 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 46 secs. Pages in use: 26
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 50/299 29/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 5996237 m, 114226 m/sec, 8303652 t fired, .
39 EF FNDP 50/1754 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 8591089 t fired, 633161 attempts, .
41 EF FNDP 50/1754 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 5712390 t fired, 799899 attempts, .
42 EF STEQ 50/3554 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 51 secs. Pages in use: 29
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 55/299 31/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 6539744 m, 108701 m/sec, 9070964 t fired, .
39 EF FNDP 55/1749 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 9505569 t fired, 700569 attempts, .
41 EF FNDP 55/1749 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 6158245 t fired, 862479 attempts, .
42 EF STEQ 55/3549 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 56 secs. Pages in use: 31
# running tasks: 4 of 4 Visible: 13
lola: CANCELED task # 19 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 60/1744 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 10403722 t fired, 766771 attempts, .
41 EF FNDP 60/1744 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 6829247 t fired, 956456 attempts, .
42 EF STEQ 60/3544 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 61 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
lola: LAUNCH task # 37 (type EXCL) for 36 SieveSingleMsgMbox-PT-d1m36-CTLFireability-14
lola: time limit : 321 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-14
lola: result : false
lola: markings : 8
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 SieveSingleMsgMbox-PT-d1m36-CTLFireability-09
lola: time limit : 353 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-09
lola: result : false
lola: markings : 8
lola: fired transitions : 34
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 SieveSingleMsgMbox-PT-d1m36-CTLFireability-06
lola: time limit : 393 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-06
lola: result : false
lola: markings : 874
lola: fired transitions : 1064
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04
lola: time limit : 442 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/442 3/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 597605 m, 119521 m/sec, 803677 t fired, .
39 EF FNDP 65/1739 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 10883583 t fired, 802182 attempts, .
41 EF FNDP 65/1739 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 7311952 t fired, 1024167 attempts, .
42 EF STEQ 65/3539 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 66 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/442 6/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 1232876 m, 127054 m/sec, 1684043 t fired, .
39 EF FNDP 70/1734 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 11383395 t fired, 839054 attempts, .
41 EF FNDP 70/1734 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 7812964 t fired, 1094124 attempts, .
42 EF STEQ 70/3534 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 71 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/442 8/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 1664560 m, 86336 m/sec, 2273643 t fired, .
39 EF FNDP 75/1729 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 12188234 t fired, 898401 attempts, .
41 EF FNDP 75/1729 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 8285976 t fired, 1160317 attempts, .
42 EF STEQ 75/3529 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 76 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/442 11/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 2203621 m, 107812 m/sec, 3047525 t fired, .
39 EF FNDP 80/1724 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 13098868 t fired, 965545 attempts, .
41 EF FNDP 80/1724 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 8770835 t fired, 1228124 attempts, .
42 EF STEQ 80/3524 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 81 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/442 14/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 2830027 m, 125281 m/sec, 3918368 t fired, .
39 EF FNDP 85/1719 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 13575821 t fired, 1000733 attempts, .
41 EF FNDP 85/1719 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 9250913 t fired, 1295149 attempts, .
42 EF STEQ 85/3519 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 86 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/442 17/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 3477894 m, 129573 m/sec, 4784248 t fired, .
39 EF FNDP 90/1714 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 14070875 t fired, 1037297 attempts, .
41 EF FNDP 90/1714 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 9746377 t fired, 1364286 attempts, .
42 EF STEQ 90/3514 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 91 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/442 19/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 3971096 m, 98640 m/sec, 5453662 t fired, .
39 EF FNDP 95/1709 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 14557952 t fired, 1073169 attempts, .
41 EF FNDP 95/1709 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 10494677 t fired, 1469105 attempts, .
42 EF STEQ 95/3509 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 96 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/442 22/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 4610799 m, 127940 m/sec, 6335682 t fired, .
39 EF FNDP 100/1704 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 15481970 t fired, 1141340 attempts, .
41 EF FNDP 100/1704 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 11451069 t fired, 1602919 attempts, .
42 EF STEQ 100/3504 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 101 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/442 25/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 5275272 m, 132894 m/sec, 7325969 t fired, .
39 EF FNDP 105/1699 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 16427584 t fired, 1211063 attempts, .
41 EF FNDP 105/1699 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 12407594 t fired, 1736749 attempts, .
42 EF STEQ 105/3499 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 106 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/442 28/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 5917345 m, 128414 m/sec, 8195572 t fired, .
39 EF FNDP 110/1694 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 17319164 t fired, 1276737 attempts, .
41 EF FNDP 110/1694 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 13298975 t fired, 1861877 attempts, .
42 EF STEQ 110/3494 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 111 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 55/442 31/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 6556928 m, 127916 m/sec, 9091964 t fired, .
39 EF FNDP 115/1689 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 18240403 t fired, 1344655 attempts, .
41 EF FNDP 115/1689 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 14194144 t fired, 1987281 attempts, .
42 EF STEQ 115/3489 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 116 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
lola: CANCELED task # 7 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 1 2 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 120/1684 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 19137894 t fired, 1410808 attempts, .
41 EF FNDP 120/1684 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 15104610 t fired, 2114621 attempts, .
42 EF STEQ 120/3484 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
lola: LAUNCH task # 1 (type EXCL) for 0 SieveSingleMsgMbox-PT-d1m36-CTLFireability-01
lola: time limit : 497 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-01
lola: result : true
lola: markings : 876
lola: fired transitions : 1820
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 33 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13
lola: time limit : 579 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 3 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 125/1679 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 20013732 t fired, 1475393 attempts, .
41 EF FNDP 125/1679 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 16058424 t fired, 2248348 attempts, .
42 EF STEQ 125/3479 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
45 EF EXCL 5/579 4/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 775949 m, 155189 m/sec, 922125 t fired, .

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 3 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 130/1674 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 20961035 t fired, 1545296 attempts, .
41 EF FNDP 130/1674 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 16997847 t fired, 2379798 attempts, .
42 EF STEQ 130/3474 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
45 EF EXCL 10/579 9/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 1810785 m, 206967 m/sec, 2166987 t fired, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 3 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 135/1669 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 21909699 t fired, 1615273 attempts, .
41 EF FNDP 135/1669 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 17939515 t fired, 2512013 attempts, .
42 EF STEQ 135/3469 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
45 EF EXCL 15/579 14/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 2835720 m, 204987 m/sec, 3403703 t fired, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 3 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 140/1664 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 22856247 t fired, 1685010 attempts, .
41 EF FNDP 140/1664 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 18881526 t fired, 2644135 attempts, .
42 EF STEQ 140/3464 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
45 EF EXCL 20/579 19/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 3855409 m, 203937 m/sec, 4632945 t fired, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 3 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 145/1659 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 23808193 t fired, 1755167 attempts, .
41 EF FNDP 145/1659 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 19822012 t fired, 2776021 attempts, .
42 EF STEQ 145/3459 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
45 EF EXCL 25/579 24/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 4874973 m, 203912 m/sec, 5871393 t fired, .

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 3 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 150/1654 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 24759408 t fired, 1825333 attempts, .
41 EF FNDP 150/1654 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 20761867 t fired, 2907687 attempts, .
42 EF STEQ 150/3454 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
45 EF EXCL 30/579 29/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 5896513 m, 204308 m/sec, 7102732 t fired, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
lola: CANCELED task # 45 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 3 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 155/1649 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 25714081 t fired, 1895691 attempts, .
41 EF FNDP 155/1649 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 21705952 t fired, 3039783 attempts, .
42 EF STEQ 155/3449 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
lola: LAUNCH task # 44 (type EXCL) for 30 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12
lola: time limit : 688 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 2 2 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 160/1644 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 26662982 t fired, 1965682 attempts, .
41 EF FNDP 160/1644 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 22650669 t fired, 3172356 attempts, .
42 EF STEQ 160/3444 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
44 EF EXCL 5/688 5/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 1015430 m, 203086 m/sec, 1227050 t fired, .

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 2 2 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 165/1639 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 27580932 t fired, 2033434 attempts, .
41 EF FNDP 165/1639 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 23568935 t fired, 3300602 attempts, .
42 EF STEQ 165/3439 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
44 EF EXCL 10/688 10/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 2047266 m, 206367 m/sec, 2487648 t fired, .

Time elapsed: 166 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 2 2 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 170/1634 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 28484897 t fired, 2100196 attempts, .
41 EF FNDP 170/1634 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 24460766 t fired, 3425332 attempts, .
42 EF STEQ 170/3434 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
44 EF EXCL 15/688 15/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 2964126 m, 183372 m/sec, 3606792 t fired, .

Time elapsed: 171 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 2 2 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 175/1629 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 29388490 t fired, 2166861 attempts, .
41 EF FNDP 175/1629 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 25346509 t fired, 3549429 attempts, .
42 EF STEQ 175/3429 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
44 EF EXCL 20/688 20/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 3939448 m, 195064 m/sec, 4802872 t fired, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 2 2 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 180/1624 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 30322727 t fired, 2235752 attempts, .
41 EF FNDP 180/1624 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 26289396 t fired, 3681493 attempts, .
42 EF STEQ 180/3424 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
44 EF EXCL 25/688 24/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 4967663 m, 205643 m/sec, 6052020 t fired, .

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 2 2 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 185/1619 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 31255844 t fired, 2304657 attempts, .
41 EF FNDP 185/1619 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 27234544 t fired, 3814224 attempts, .
42 EF STEQ 185/3419 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
44 EF EXCL 30/688 29/32 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 6005237 m, 207514 m/sec, 7322116 t fired, .

Time elapsed: 186 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
lola: CANCELED task # 44 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 2 1 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 190/1614 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 32116053 t fired, 2367928 attempts, .
41 EF FNDP 190/1614 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 28085827 t fired, 3933728 attempts, .
42 EF STEQ 190/3414 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.

Time elapsed: 191 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
lola: LAUNCH task # 40 (type EXCL) for 24 SieveSingleMsgMbox-PT-d1m36-CTLFireability-10
lola: time limit : 852 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-10
lola: result : true
lola: markings : 8
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 SieveSingleMsgMbox-PT-d1m36-CTLFireability-03
lola: time limit : 1136 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-03
lola: result : false
lola: markings : 8
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 SieveSingleMsgMbox-PT-d1m36-CTLFireability-11
lola: time limit : 1704 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-11
lola: result : false
lola: markings : 6
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 SieveSingleMsgMbox-PT-d1m36-CTLFireability-05
lola: time limit : 3409 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-05
lola: result : true
lola: markings : 8
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EQUN) for 30 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/376/CTLFireability-43.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 195/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 33017957 t fired, 2434470 attempts, .
41 EF FNDP 195/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 28701124 t fired, 4019698 attempts, .
42 EF STEQ 195/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 5/1704 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 200/3404 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 33964617 t fired, 2504280 attempts, .
41 EF FNDP 200/3404 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 29176608 t fired, 4086533 attempts, .
42 EF STEQ 200/3404 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 10/1699 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 205/3399 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 34850266 t fired, 2569658 attempts, .
41 EF FNDP 205/3399 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 29615857 t fired, 4148006 attempts, .
42 EF STEQ 205/3399 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 15/1694 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 210/3394 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 35758813 t fired, 2636693 attempts, .
41 EF FNDP 210/3394 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 30070152 t fired, 4211612 attempts, .
42 EF STEQ 210/3394 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 20/1689 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 215/3389 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 36719588 t fired, 2707528 attempts, .
41 EF FNDP 215/3389 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 30533519 t fired, 4276527 attempts, .
42 EF STEQ 215/3389 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 25/1684 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 220/3384 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 37692851 t fired, 2779302 attempts, .
41 EF FNDP 220/3384 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 31012657 t fired, 4343736 attempts, .
42 EF STEQ 220/3384 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 30/1679 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 225/3379 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 38655062 t fired, 2850252 attempts, .
41 EF FNDP 225/3379 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 31494892 t fired, 4411211 attempts, .
42 EF STEQ 225/3379 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 35/1674 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 230/3374 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 39624038 t fired, 2921747 attempts, .
41 EF FNDP 230/3374 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 31973356 t fired, 4478238 attempts, .
42 EF STEQ 230/3374 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 40/1669 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 235/3369 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 40590842 t fired, 2992977 attempts, .
41 EF FNDP 235/3369 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 32448626 t fired, 4544870 attempts, .
42 EF STEQ 235/3369 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 45/1664 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 240/3364 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 41576743 t fired, 3065711 attempts, .
41 EF FNDP 240/3364 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 32929600 t fired, 4612134 attempts, .
42 EF STEQ 240/3364 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 50/1659 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 245/3359 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 42556760 t fired, 3137997 attempts, .
41 EF FNDP 245/3359 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 33409751 t fired, 4679352 attempts, .
42 EF STEQ 245/3359 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 55/1654 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 250/3354 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 43536926 t fired, 3210292 attempts, .
41 EF FNDP 250/3354 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 33887684 t fired, 4746202 attempts, .
42 EF STEQ 250/3354 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 60/1649 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 255/3349 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 44514974 t fired, 3282463 attempts, .
41 EF FNDP 255/3349 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 34366283 t fired, 4813227 attempts, .
42 EF STEQ 255/3349 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 65/1644 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 260/3344 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 45469884 t fired, 3352937 attempts, .
41 EF FNDP 260/3344 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 34846924 t fired, 4880763 attempts, .
42 EF STEQ 260/3344 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 70/1639 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 265/3339 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 46457107 t fired, 3425721 attempts, .
41 EF FNDP 265/3339 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 35327493 t fired, 4948084 attempts, .
42 EF STEQ 265/3339 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 75/1634 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 270/3334 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 47431790 t fired, 3497611 attempts, .
41 EF FNDP 270/3334 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 35806623 t fired, 5015218 attempts, .
42 EF STEQ 270/3334 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 80/1629 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 275/3329 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 48411400 t fired, 3569882 attempts, .
41 EF FNDP 275/3329 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 36283824 t fired, 5082244 attempts, .
42 EF STEQ 275/3329 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 85/1624 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 280/3324 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 49377700 t fired, 3641103 attempts, .
41 EF FNDP 280/3324 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 36766677 t fired, 5149738 attempts, .
42 EF STEQ 280/3324 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 90/1619 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 285/3319 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 50341267 t fired, 3712219 attempts, .
41 EF FNDP 285/3319 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 37244170 t fired, 5216587 attempts, .
42 EF STEQ 285/3319 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 95/1614 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 286 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 290/3314 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 51321980 t fired, 3784493 attempts, .
41 EF FNDP 290/3314 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 37724394 t fired, 5283852 attempts, .
42 EF STEQ 290/3314 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 100/1609 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 291 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 295/3309 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 52302669 t fired, 3856832 attempts, .
41 EF FNDP 295/3309 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 38205806 t fired, 5351307 attempts, .
42 EF STEQ 295/3309 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 105/1604 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 296 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 300/3304 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 53233285 t fired, 3925481 attempts, .
41 EF FNDP 300/3304 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 38726841 t fired, 5424363 attempts, .
42 EF STEQ 300/3304 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 110/1599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 301 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 305/3299 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 54162826 t fired, 3994111 attempts, .
41 EF FNDP 305/3299 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 39679833 t fired, 5557781 attempts, .
42 EF STEQ 305/3299 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 115/1594 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 306 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 310/3294 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 55115045 t fired, 4064276 attempts, .
41 EF FNDP 310/3294 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 40624587 t fired, 5690538 attempts, .
42 EF STEQ 310/3294 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 120/1589 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 311 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 315/3289 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 56067459 t fired, 4134455 attempts, .
41 EF FNDP 315/3289 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 41571589 t fired, 5823099 attempts, .
42 EF STEQ 315/3289 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 125/1584 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 316 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 320/3284 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 57017631 t fired, 4204499 attempts, .
41 EF FNDP 320/3284 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 42514157 t fired, 5955053 attempts, .
42 EF STEQ 320/3284 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 130/1579 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 321 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 325/3279 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 57968820 t fired, 4274627 attempts, .
41 EF FNDP 325/3279 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 43458224 t fired, 6087661 attempts, .
42 EF STEQ 325/3279 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 135/1574 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 326 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 330/3274 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 58920251 t fired, 4344856 attempts, .
41 EF FNDP 330/3274 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 44403954 t fired, 6220229 attempts, .
42 EF STEQ 330/3274 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 140/1569 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 331 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 335/3269 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 59872680 t fired, 4415122 attempts, .
41 EF FNDP 335/3269 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 45353717 t fired, 6353297 attempts, .
42 EF STEQ 335/3269 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 145/1564 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 336 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 340/3264 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 60823444 t fired, 4485200 attempts, .
41 EF FNDP 340/3264 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 46297651 t fired, 6485231 attempts, .
42 EF STEQ 340/3264 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 150/1559 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 341 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 345/3259 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 61774231 t fired, 4555261 attempts, .
41 EF FNDP 345/3259 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 47241270 t fired, 6617154 attempts, .
42 EF STEQ 345/3259 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 155/1554 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 346 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 350/3254 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 62726135 t fired, 4625432 attempts, .
41 EF FNDP 350/3254 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 48187431 t fired, 6749445 attempts, .
42 EF STEQ 350/3254 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 160/1549 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 351 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 355/3249 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 63676736 t fired, 4695538 attempts, .
41 EF FNDP 355/3249 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 49130088 t fired, 6881482 attempts, .
42 EF STEQ 355/3249 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 165/1544 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 356 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 360/3244 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 64627670 t fired, 4765675 attempts, .
41 EF FNDP 360/3244 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 50073270 t fired, 7013561 attempts, .
42 EF STEQ 360/3244 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 170/1539 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 361 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 365/3239 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 65580887 t fired, 4835927 attempts, .
41 EF FNDP 365/3239 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 51020749 t fired, 7146349 attempts, .
42 EF STEQ 365/3239 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 175/1534 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 366 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 370/3234 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 66462048 t fired, 4900881 attempts, .
41 EF FNDP 370/3234 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 51913712 t fired, 7271472 attempts, .
42 EF STEQ 370/3234 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 180/1529 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 371 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 375/3229 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 67380105 t fired, 4968588 attempts, .
41 EF FNDP 375/3229 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 52817604 t fired, 7398169 attempts, .
42 EF STEQ 375/3229 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 185/1524 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 376 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 380/3224 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 68303355 t fired, 5036712 attempts, .
41 EF FNDP 380/3224 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 53710983 t fired, 7523539 attempts, .
42 EF STEQ 380/3224 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 190/1519 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 381 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 385/3219 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 69253028 t fired, 5106739 attempts, .
41 EF FNDP 385/3219 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 54629211 t fired, 7652253 attempts, .
42 EF STEQ 385/3219 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 195/1514 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 386 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 390/3214 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 70159561 t fired, 5173520 attempts, .
41 EF FNDP 390/3214 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 55528352 t fired, 7777912 attempts, .
42 EF STEQ 390/3214 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 200/1509 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 391 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 395/3209 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 71051676 t fired, 5239300 attempts, .
41 EF FNDP 395/3209 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 56425310 t fired, 7903459 attempts, .
42 EF STEQ 395/3209 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 205/1504 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 396 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 400/3204 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 71946098 t fired, 5305283 attempts, .
41 EF FNDP 400/3204 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 57306200 t fired, 8027045 attempts, .
42 EF STEQ 400/3204 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 210/1499 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 401 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 405/3199 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 72898429 t fired, 5375498 attempts, .
41 EF FNDP 405/3199 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 58216794 t fired, 8154555 attempts, .
42 EF STEQ 405/3199 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 215/1494 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 406 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 410/3194 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 73851487 t fired, 5445710 attempts, .
41 EF FNDP 410/3194 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 59156832 t fired, 8286015 attempts, .
42 EF STEQ 410/3194 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 220/1489 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 411 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 415/3189 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 74804069 t fired, 5515926 attempts, .
41 EF FNDP 415/3189 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 60102575 t fired, 8418684 attempts, .
42 EF STEQ 415/3189 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 225/1484 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 416 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 420/3184 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 75757450 t fired, 5586255 attempts, .
41 EF FNDP 420/3184 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 61047585 t fired, 8551279 attempts, .
42 EF STEQ 420/3184 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 230/1479 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 421 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 425/3179 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 76710590 t fired, 5656506 attempts, .
41 EF FNDP 425/3179 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 61993766 t fired, 8683879 attempts, .
42 EF STEQ 425/3179 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 235/1474 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 426 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 430/3174 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 77660702 t fired, 5726518 attempts, .
41 EF FNDP 430/3174 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 62938268 t fired, 8816373 attempts, .
42 EF STEQ 430/3174 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 240/1469 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 431 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 435/3169 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 78604871 t fired, 5796069 attempts, .
41 EF FNDP 435/3169 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 63877301 t fired, 8947715 attempts, .
42 EF STEQ 435/3169 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 245/1464 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 436 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 440/3164 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 79506391 t fired, 5862472 attempts, .
41 EF FNDP 440/3164 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 64704511 t fired, 9063610 attempts, .
42 EF STEQ 440/3164 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 250/1459 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 441 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 445/3159 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 80400608 t fired, 5928382 attempts, .
41 EF FNDP 445/3159 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 65567106 t fired, 9184120 attempts, .
42 EF STEQ 445/3159 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 255/1454 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 446 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 450/3154 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 81341172 t fired, 5997727 attempts, .
41 EF FNDP 450/3154 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 66434424 t fired, 9305495 attempts, .
42 EF STEQ 450/3154 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 260/1449 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 451 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 455/3149 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 82265764 t fired, 6065900 attempts, .
41 EF FNDP 455/3149 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 67290307 t fired, 9425392 attempts, .
42 EF STEQ 455/3149 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 265/1444 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 456 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 460/3144 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 83211303 t fired, 6135675 attempts, .
41 EF FNDP 460/3144 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 68230271 t fired, 9557021 attempts, .
42 EF STEQ 460/3144 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 270/1439 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 461 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 465/3139 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 84143035 t fired, 6204455 attempts, .
41 EF FNDP 465/3139 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 69095260 t fired, 9678512 attempts, .
42 EF STEQ 465/3139 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 275/1434 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 466 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 470/3134 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 85098349 t fired, 6274829 attempts, .
41 EF FNDP 470/3134 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 69972746 t fired, 9801543 attempts, .
42 EF STEQ 470/3134 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 280/1429 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 471 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 475/3129 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 86049951 t fired, 6345039 attempts, .
41 EF FNDP 475/3129 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 70908402 t fired, 9932590 attempts, .
42 EF STEQ 475/3129 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 285/1424 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 476 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 480/3124 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 87002384 t fired, 6415222 attempts, .
41 EF FNDP 480/3124 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 71850253 t fired, 10064283 attempts, .
42 EF STEQ 480/3124 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 290/1419 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 481 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 485/3119 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 87870941 t fired, 6479246 attempts, .
41 EF FNDP 485/3119 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 72729820 t fired, 10187382 attempts, .
42 EF STEQ 485/3119 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 295/1414 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 486 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 490/3114 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 88769407 t fired, 6545508 attempts, .
41 EF FNDP 490/3114 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 73620730 t fired, 10312236 attempts, .
42 EF STEQ 490/3114 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 300/1409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 491 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 495/3109 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 89722244 t fired, 6615685 attempts, .
41 EF FNDP 495/3109 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 74506341 t fired, 10436068 attempts, .
42 EF STEQ 495/3109 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 305/1404 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 496 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 500/3104 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 90674918 t fired, 6685927 attempts, .
41 EF FNDP 500/3104 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 75414590 t fired, 10563490 attempts, .
42 EF STEQ 500/3104 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 310/1399 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 501 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 505/3099 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 91573654 t fired, 6752146 attempts, .
41 EF FNDP 505/3099 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 76308444 t fired, 10688353 attempts, .
42 EF STEQ 505/3099 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 315/1394 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 506 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 510/3094 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 92501611 t fired, 6820593 attempts, .
41 EF FNDP 510/3094 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 77209364 t fired, 10814248 attempts, .
42 EF STEQ 510/3094 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 320/1389 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 511 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 515/3089 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 93413489 t fired, 6887808 attempts, .
41 EF FNDP 515/3089 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 78148930 t fired, 10945210 attempts, .
42 EF STEQ 515/3089 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 325/1384 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 516 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 520/3084 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 94363673 t fired, 6957924 attempts, .
41 EF FNDP 520/3084 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 79087324 t fired, 11077065 attempts, .
42 EF STEQ 520/3084 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 330/1379 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 521 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 525/3079 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 95238884 t fired, 7022449 attempts, .
41 EF FNDP 525/3079 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 79986481 t fired, 11202745 attempts, .
42 EF STEQ 525/3079 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 335/1374 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 526 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 530/3074 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 96153205 t fired, 7089796 attempts, .
41 EF FNDP 530/3074 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 80854318 t fired, 11324290 attempts, .
42 EF STEQ 530/3074 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 340/1369 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 531 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 535/3069 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 97059453 t fired, 7156723 attempts, .
41 EF FNDP 535/3069 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 81693364 t fired, 11441736 attempts, .
42 EF STEQ 535/3069 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 345/1364 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 536 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 540/3064 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 97994711 t fired, 7225608 attempts, .
41 EF FNDP 540/3064 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 82423729 t fired, 11544244 attempts, .
42 EF STEQ 540/3064 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 350/1359 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 541 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 545/3059 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 98730317 t fired, 7279895 attempts, .
41 EF FNDP 545/3059 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 82889206 t fired, 11609492 attempts, .
42 EF STEQ 545/3059 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 355/1354 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 546 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 550/3054 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 99630362 t fired, 7346363 attempts, .
41 EF FNDP 550/3054 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 83723648 t fired, 11726292 attempts, .
42 EF STEQ 550/3054 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 360/1349 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 551 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 555/3049 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 100582004 t fired, 7416503 attempts, .
41 EF FNDP 555/3049 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 84660545 t fired, 11857522 attempts, .
42 EF STEQ 555/3049 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 365/1344 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 556 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 560/3044 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 101551548 t fired, 7487981 attempts, .
41 EF FNDP 560/3044 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 85640163 t fired, 11994624 attempts, .
42 EF STEQ 560/3044 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 370/1339 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 561 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 565/3039 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 102502766 t fired, 7558138 attempts, .
41 EF FNDP 565/3039 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 86593310 t fired, 12127987 attempts, .
42 EF STEQ 565/3039 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 375/1334 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 566 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 570/3034 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 103404157 t fired, 7624590 attempts, .
41 EF FNDP 570/3034 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 87493734 t fired, 12254066 attempts, .
42 EF STEQ 570/3034 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 380/1329 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 571 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 575/3029 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 104317966 t fired, 7691895 attempts, .
41 EF FNDP 575/3029 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 88414734 t fired, 12383122 attempts, .
42 EF STEQ 575/3029 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 385/1324 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 576 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 580/3024 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 105219482 t fired, 7758340 attempts, .
41 EF FNDP 580/3024 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 89188999 t fired, 12491411 attempts, .
42 EF STEQ 580/3024 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 390/1319 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 581 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 585/3019 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 105767401 t fired, 7798719 attempts, .
41 EF FNDP 585/3019 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 90013564 t fired, 12606984 attempts, .
42 EF STEQ 585/3019 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 395/1314 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 586 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 590/3014 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 106242239 t fired, 7833704 attempts, .
41 EF FNDP 590/3014 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 90921309 t fired, 12734307 attempts, .
42 EF STEQ 590/3014 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 400/1309 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 591 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 595/3009 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 106842381 t fired, 7877909 attempts, .
41 EF FNDP 595/3009 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 91701521 t fired, 12843817 attempts, .
42 EF STEQ 595/3009 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 405/1304 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 596 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 600/3004 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 107411225 t fired, 7919863 attempts, .
41 EF FNDP 600/3004 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 92418133 t fired, 12943964 attempts, .
42 EF STEQ 600/3004 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 410/1299 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 601 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 605/2999 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 108005365 t fired, 7963603 attempts, .
41 EF FNDP 605/2999 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 93256147 t fired, 13061193 attempts, .
42 EF STEQ 605/2999 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 415/1294 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 606 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 610/2994 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 108463941 t fired, 7997459 attempts, .
41 EF FNDP 610/2994 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 93948295 t fired, 13158305 attempts, .
42 EF STEQ 610/2994 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 420/1289 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 611 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 615/2989 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 109350253 t fired, 8062767 attempts, .
41 EF FNDP 615/2989 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 94517387 t fired, 13238112 attempts, .
42 EF STEQ 615/2989 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 425/1284 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 616 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 620/2984 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 110029329 t fired, 8112821 attempts, .
41 EF FNDP 620/2984 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 95011738 t fired, 13306924 attempts, .
42 EF STEQ 620/2984 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 430/1279 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 621 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 625/2979 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 110830983 t fired, 8171953 attempts, .
41 EF FNDP 625/2979 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 95495257 t fired, 13374936 attempts, .
42 EF STEQ 625/2979 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 435/1274 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 626 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 630/2974 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 111448173 t fired, 8217468 attempts, .
41 EF FNDP 630/2974 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 96034097 t fired, 13450341 attempts, .
42 EF STEQ 630/2974 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 440/1269 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 631 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 635/2969 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 112088736 t fired, 8264719 attempts, .
41 EF FNDP 635/2969 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 96941396 t fired, 13577535 attempts, .
42 EF STEQ 635/2969 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 445/1264 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 636 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 640/2964 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 112652306 t fired, 8306291 attempts, .
41 EF FNDP 640/2964 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 97746488 t fired, 13690379 attempts, .
42 EF STEQ 640/2964 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 450/1259 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 641 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 645/2959 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 113165920 t fired, 8344141 attempts, .
41 EF FNDP 645/2959 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 98389669 t fired, 13780726 attempts, .
42 EF STEQ 645/2959 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 455/1254 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 646 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 650/2954 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 113965710 t fired, 8403120 attempts, .
41 EF FNDP 650/2954 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 98917835 t fired, 13854526 attempts, .
42 EF STEQ 650/2954 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 460/1249 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 651 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 655/2949 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 114679204 t fired, 8455757 attempts, .
41 EF FNDP 655/2949 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 99660248 t fired, 13958640 attempts, .
42 EF STEQ 655/2949 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 465/1244 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 656 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 660/2944 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 115578239 t fired, 8522078 attempts, .
41 EF FNDP 660/2944 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 100528007 t fired, 14079886 attempts, .
42 EF STEQ 660/2944 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 470/1239 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 661 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 665/2939 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 116433065 t fired, 8585083 attempts, .
41 EF FNDP 665/2939 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 101351287 t fired, 14195463 attempts, .
42 EF STEQ 665/2939 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 475/1234 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 666 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 670/2934 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 117305902 t fired, 8649399 attempts, .
41 EF FNDP 670/2934 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 102208658 t fired, 14315678 attempts, .
42 EF STEQ 670/2934 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 480/1229 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 671 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 675/2929 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 118112645 t fired, 8708906 attempts, .
41 EF FNDP 675/2929 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 102962974 t fired, 14421191 attempts, .
42 EF STEQ 675/2929 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 485/1224 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 676 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 680/2924 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 118653554 t fired, 8748844 attempts, .
41 EF FNDP 680/2924 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 103851804 t fired, 14545895 attempts, .
42 EF STEQ 680/2924 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 490/1219 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 681 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 685/2919 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 119239790 t fired, 8792125 attempts, .
41 EF FNDP 685/2919 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 104693627 t fired, 14663807 attempts, .
42 EF STEQ 685/2919 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 495/1214 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 686 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 690/2914 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 119935362 t fired, 8843379 attempts, .
41 EF FNDP 690/2914 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 105516779 t fired, 14779115 attempts, .
42 EF STEQ 690/2914 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 500/1209 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 691 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 695/2909 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 120881795 t fired, 8913199 attempts, .
41 EF FNDP 695/2909 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 106469607 t fired, 14912575 attempts, .
42 EF STEQ 695/2909 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 505/1204 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 696 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 700/2904 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 121731169 t fired, 8975879 attempts, .
41 EF FNDP 700/2904 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 107360699 t fired, 15037262 attempts, .
42 EF STEQ 700/2904 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 510/1199 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 701 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 705/2899 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 122583806 t fired, 9038718 attempts, .
41 EF FNDP 705/2899 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 108255583 t fired, 15162680 attempts, .
42 EF STEQ 705/2899 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 515/1194 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 706 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 710/2894 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 123519933 t fired, 9107719 attempts, .
41 EF FNDP 710/2894 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 109181622 t fired, 15292357 attempts, .
42 EF STEQ 710/2894 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 520/1189 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 711 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 715/2889 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 124320706 t fired, 9166755 attempts, .
41 EF FNDP 715/2889 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 109727510 t fired, 15369053 attempts, .
42 EF STEQ 715/2889 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 525/1184 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 716 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 720/2884 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 124990585 t fired, 9216171 attempts, .
41 EF FNDP 720/2884 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 110560980 t fired, 15485800 attempts, .
42 EF STEQ 720/2884 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 530/1179 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 721 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 725/2879 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 125917702 t fired, 9284526 attempts, .
41 EF FNDP 725/2879 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 111503783 t fired, 15617754 attempts, .
42 EF STEQ 725/2879 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 535/1174 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 726 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 730/2874 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 126845799 t fired, 9352981 attempts, .
41 EF FNDP 730/2874 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 112437778 t fired, 15748696 attempts, .
42 EF STEQ 730/2874 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 540/1169 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 731 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 735/2869 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 127744278 t fired, 9419235 attempts, .
41 EF FNDP 735/2869 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 113325143 t fired, 15872959 attempts, .
42 EF STEQ 735/2869 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 545/1164 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 736 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 740/2864 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 128643885 t fired, 9485600 attempts, .
41 EF FNDP 740/2864 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 114182886 t fired, 15992949 attempts, .
42 EF STEQ 740/2864 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 550/1159 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 741 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 745/2859 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 129537942 t fired, 9551468 attempts, .
41 EF FNDP 745/2859 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 115049409 t fired, 16113931 attempts, .
42 EF STEQ 745/2859 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 555/1154 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 746 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 750/2854 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 130423576 t fired, 9616679 attempts, .
41 EF FNDP 750/2854 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 115981311 t fired, 16244634 attempts, .
42 EF STEQ 750/2854 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 560/1149 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 751 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 755/2849 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 131336648 t fired, 9683959 attempts, .
41 EF FNDP 755/2849 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 116917389 t fired, 16375588 attempts, .
42 EF STEQ 755/2849 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 565/1144 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 756 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 760/2844 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 132266583 t fired, 9752540 attempts, .
41 EF FNDP 760/2844 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 117868725 t fired, 16508771 attempts, .
42 EF STEQ 760/2844 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 570/1139 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 761 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 765/2839 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 132991701 t fired, 9805944 attempts, .
41 EF FNDP 765/2839 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 118530780 t fired, 16601580 attempts, .
42 EF STEQ 765/2839 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 575/1134 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 766 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 770/2834 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 133610187 t fired, 9851537 attempts, .
41 EF FNDP 770/2834 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 119300455 t fired, 16709375 attempts, .
42 EF STEQ 770/2834 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 580/1129 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 771 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 775/2829 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 134184385 t fired, 9893870 attempts, .
41 EF FNDP 775/2829 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 119851215 t fired, 16786369 attempts, .
42 EF STEQ 775/2829 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 585/1124 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 776 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 780/2824 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 134798254 t fired, 9939183 attempts, .
41 EF FNDP 780/2824 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 120459580 t fired, 16871397 attempts, .
42 EF STEQ 780/2824 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 590/1119 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 781 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 785/2819 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 135478248 t fired, 9989282 attempts, .
41 EF FNDP 785/2819 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 120998450 t fired, 16946776 attempts, .
42 EF STEQ 785/2819 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 595/1114 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 786 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 790/2814 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 136140625 t fired, 10038128 attempts, .
41 EF FNDP 790/2814 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 121580496 t fired, 17028049 attempts, .
42 EF STEQ 790/2814 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 600/1109 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 791 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 795/2809 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 136656358 t fired, 10076091 attempts, .
41 EF FNDP 795/2809 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 122073617 t fired, 17096851 attempts, .
42 EF STEQ 795/2809 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 605/1104 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 796 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 800/2804 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 137115608 t fired, 10109965 attempts, .
41 EF FNDP 800/2804 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 122756246 t fired, 17192294 attempts, .
42 EF STEQ 800/2804 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 610/1099 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 801 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 805/2799 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 137699958 t fired, 10153099 attempts, .
41 EF FNDP 805/2799 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 123454602 t fired, 17290407 attempts, .
42 EF STEQ 805/2799 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 615/1094 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 806 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 810/2794 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 138198718 t fired, 10189801 attempts, .
41 EF FNDP 810/2794 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 124058018 t fired, 17375100 attempts, .
42 EF STEQ 810/2794 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 620/1089 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 811 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 815/2789 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 138811042 t fired, 10235009 attempts, .
41 EF FNDP 815/2789 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 124675896 t fired, 17461694 attempts, .
42 EF STEQ 815/2789 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 625/1084 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 816 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 820/2784 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 138946840 t fired, 10244998 attempts, .
41 EF FNDP 820/2784 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 124896379 t fired, 17492391 attempts, .
42 EF STEQ 820/2784 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 630/1079 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 821 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 1 2 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 2 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 826/2779 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 139041761 t fired, 10251988 attempts, .
41 EF FNDP 826/2779 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 124980072 t fired, 17504171 attempts, .
42 EF STEQ 826/2779 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 sara is running.
43 EF STEQ 636/1074 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 827 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 13
lola: FINISHED task # 42 (type EQUN) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-13
lola: result : unknown
lola: LAUNCH task # 47 (type SRCH) for 30 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 47 (type SRCH) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-12
lola: result : unknown
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 831/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 139869236 t fired, 10312972 attempts, .
41 EF FNDP 831/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 125846992 t fired, 17625594 attempts, .
43 EF STEQ 641/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 832 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 836/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 140699241 t fired, 10374132 attempts, .
41 EF FNDP 836/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 126712058 t fired, 17746439 attempts, .
43 EF STEQ 646/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 837 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 841/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 141580703 t fired, 10439096 attempts, .
41 EF FNDP 841/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 127556776 t fired, 17864865 attempts, .
43 EF STEQ 651/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 842 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 846/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 142426280 t fired, 10501434 attempts, .
41 EF FNDP 846/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 128335641 t fired, 17974172 attempts, .
43 EF STEQ 656/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 847 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 851/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 143283290 t fired, 10564605 attempts, .
41 EF FNDP 851/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 129214005 t fired, 18097157 attempts, .
43 EF STEQ 661/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 852 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 856/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 144136147 t fired, 10627500 attempts, .
41 EF FNDP 856/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 130098493 t fired, 18220868 attempts, .
43 EF STEQ 666/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 857 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 861/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 144994477 t fired, 10690726 attempts, .
41 EF FNDP 861/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 131019714 t fired, 18349809 attempts, .
43 EF STEQ 671/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 862 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 866/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 145851421 t fired, 10753874 attempts, .
41 EF FNDP 866/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 131913646 t fired, 18474751 attempts, .
43 EF STEQ 676/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 867 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 871/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 146701025 t fired, 10816585 attempts, .
41 EF FNDP 871/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 132787449 t fired, 18597342 attempts, .
43 EF STEQ 681/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 872 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 876/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 147536266 t fired, 10878124 attempts, .
41 EF FNDP 876/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 133641546 t fired, 18716929 attempts, .
43 EF STEQ 686/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 877 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 881/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 148366652 t fired, 10939321 attempts, .
41 EF FNDP 881/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 134519776 t fired, 18840110 attempts, .
43 EF STEQ 691/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 882 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 886/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 149193759 t fired, 11000244 attempts, .
41 EF FNDP 886/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 135383294 t fired, 18961048 attempts, .
43 EF STEQ 696/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 887 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 891/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 150026355 t fired, 11061543 attempts, .
41 EF FNDP 891/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 136313350 t fired, 19091509 attempts, .
43 EF STEQ 701/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 892 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 896/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 150854094 t fired, 11122638 attempts, .
41 EF FNDP 896/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 137274922 t fired, 19226197 attempts, .
43 EF STEQ 706/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 897 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 901/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 151716281 t fired, 11186246 attempts, .
41 EF FNDP 901/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 138170746 t fired, 19351872 attempts, .
43 EF STEQ 711/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 902 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 906/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 152603659 t fired, 11251701 attempts, .
41 EF FNDP 906/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 139038874 t fired, 19473523 attempts, .
43 EF STEQ 716/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 907 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 911/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 153418925 t fired, 11311807 attempts, .
41 EF FNDP 911/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 139879320 t fired, 19591209 attempts, .
43 EF STEQ 721/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 912 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 916/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 154289791 t fired, 11376021 attempts, .
41 EF FNDP 916/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 140720962 t fired, 19709214 attempts, .
43 EF STEQ 726/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 917 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 921/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 155128065 t fired, 11437773 attempts, .
41 EF FNDP 921/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 141596656 t fired, 19831835 attempts, .
43 EF STEQ 731/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 922 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 926/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 156038080 t fired, 11504816 attempts, .
41 EF FNDP 926/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 142494895 t fired, 19957543 attempts, .
43 EF STEQ 736/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 927 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 931/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 156917958 t fired, 11569666 attempts, .
41 EF FNDP 931/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 143428475 t fired, 20088488 attempts, .
43 EF STEQ 741/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 932 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 936/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 157757373 t fired, 11631528 attempts, .
41 EF FNDP 936/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 144254741 t fired, 20204323 attempts, .
43 EF STEQ 746/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 937 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 941/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 158600152 t fired, 11693664 attempts, .
41 EF FNDP 941/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 145186575 t fired, 20335231 attempts, .
43 EF STEQ 751/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 942 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 946/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 159441880 t fired, 11755726 attempts, .
41 EF FNDP 946/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 146083070 t fired, 20461119 attempts, .
43 EF STEQ 756/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 947 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 951/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 160290329 t fired, 11818301 attempts, .
41 EF FNDP 951/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 146992891 t fired, 20588760 attempts, .
43 EF STEQ 761/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 952 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 956/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 161174132 t fired, 11883467 attempts, .
41 EF FNDP 956/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 147911061 t fired, 20717184 attempts, .
43 EF STEQ 766/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 957 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 961/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 162051041 t fired, 11948174 attempts, .
41 EF FNDP 961/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 148846734 t fired, 20848473 attempts, .
43 EF STEQ 771/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 962 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 966/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 162889719 t fired, 12010062 attempts, .
41 EF FNDP 966/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 149721040 t fired, 20970865 attempts, .
43 EF STEQ 776/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 967 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 971/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 163736866 t fired, 12072566 attempts, .
41 EF FNDP 971/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 150635490 t fired, 21098947 attempts, .
43 EF STEQ 781/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 972 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 976/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 164644971 t fired, 12139524 attempts, .
41 EF FNDP 976/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 151514358 t fired, 21222030 attempts, .
43 EF STEQ 786/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 977 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 981/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 165558041 t fired, 12206869 attempts, .
41 EF FNDP 981/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 152454941 t fired, 21353933 attempts, .
43 EF STEQ 791/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 982 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 986/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 166472177 t fired, 12274248 attempts, .
41 EF FNDP 986/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 153413540 t fired, 21488372 attempts, .
43 EF STEQ 796/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 987 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 991/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 167061775 t fired, 12317713 attempts, .
41 EF FNDP 991/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 154015828 t fired, 21572947 attempts, .
43 EF STEQ 801/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 992 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 996/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 167530200 t fired, 12352236 attempts, .
41 EF FNDP 996/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 154489383 t fired, 21639306 attempts, .
43 EF STEQ 806/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 997 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1001/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 168009011 t fired, 12387582 attempts, .
41 EF FNDP 1001/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 154968629 t fired, 21706179 attempts, .
43 EF STEQ 811/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1002 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1006/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 168522484 t fired, 12425420 attempts, .
41 EF FNDP 1006/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 155488438 t fired, 21778871 attempts, .
43 EF STEQ 816/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1007 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1011/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 169046166 t fired, 12464097 attempts, .
41 EF FNDP 1011/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 156012610 t fired, 21852357 attempts, .
43 EF STEQ 821/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1012 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1016/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 169566092 t fired, 12502471 attempts, .
41 EF FNDP 1016/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 156539464 t fired, 21925995 attempts, .
43 EF STEQ 826/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1017 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1021/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 170089209 t fired, 12541037 attempts, .
41 EF FNDP 1021/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 157063422 t fired, 21999231 attempts, .
43 EF STEQ 831/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1022 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1026/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 170609583 t fired, 12579356 attempts, .
41 EF FNDP 1026/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 157591602 t fired, 22073421 attempts, .
43 EF STEQ 836/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1027 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1031/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 171133921 t fired, 12617972 attempts, .
41 EF FNDP 1031/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 158140216 t fired, 22150525 attempts, .
43 EF STEQ 841/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1032 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1036/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 171653290 t fired, 12656349 attempts, .
41 EF FNDP 1036/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 158665388 t fired, 22224245 attempts, .
43 EF STEQ 846/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1037 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1041/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 172168574 t fired, 12694356 attempts, .
41 EF FNDP 1041/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 159186045 t fired, 22297292 attempts, .
43 EF STEQ 851/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1042 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1046/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 172690472 t fired, 12732936 attempts, .
41 EF FNDP 1046/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 159715353 t fired, 22371274 attempts, .
43 EF STEQ 856/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1047 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1051/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 173214203 t fired, 12771590 attempts, .
41 EF FNDP 1051/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 160237687 t fired, 22444169 attempts, .
43 EF STEQ 861/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1052 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1056/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 173881299 t fired, 12820755 attempts, .
41 EF FNDP 1056/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 160905994 t fired, 22537846 attempts, .
43 EF STEQ 866/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1057 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1061/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 174812383 t fired, 12889377 attempts, .
41 EF FNDP 1061/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 161815120 t fired, 22665210 attempts, .
43 EF STEQ 871/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1062 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1066/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 175397273 t fired, 12932558 attempts, .
41 EF FNDP 1066/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 162399477 t fired, 22747180 attempts, .
43 EF STEQ 876/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1067 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1071/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 175920542 t fired, 12971172 attempts, .
41 EF FNDP 1071/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 162929733 t fired, 22821544 attempts, .
43 EF STEQ 881/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1072 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1076/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 176443870 t fired, 13009721 attempts, .
41 EF FNDP 1076/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 163459040 t fired, 22895364 attempts, .
43 EF STEQ 886/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1077 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1081/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 177028512 t fired, 13052861 attempts, .
41 EF FNDP 1081/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 164074663 t fired, 22981385 attempts, .
43 EF STEQ 891/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1082 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1086/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 177961796 t fired, 13121641 attempts, .
41 EF FNDP 1086/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 164957890 t fired, 23105026 attempts, .
43 EF STEQ 896/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1087 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1091/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 178900438 t fired, 13190887 attempts, .
41 EF FNDP 1091/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 165861333 t fired, 23231887 attempts, .
43 EF STEQ 901/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1092 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1096/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 179841132 t fired, 13260220 attempts, .
41 EF FNDP 1096/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 166784709 t fired, 23361210 attempts, .
43 EF STEQ 906/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1097 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1101/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 180779166 t fired, 13329436 attempts, .
41 EF FNDP 1101/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 167699561 t fired, 23489287 attempts, .
43 EF STEQ 911/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1102 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1106/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 181689473 t fired, 13396506 attempts, .
41 EF FNDP 1106/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 168593941 t fired, 23614443 attempts, .
43 EF STEQ 916/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1107 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1111/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 182214031 t fired, 13435163 attempts, .
41 EF FNDP 1111/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 169123851 t fired, 23688499 attempts, .
43 EF STEQ 921/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1112 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1116/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 182738107 t fired, 13473789 attempts, .
41 EF FNDP 1116/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 169654266 t fired, 23762992 attempts, .
43 EF STEQ 926/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1117 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1121/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 183302570 t fired, 13515426 attempts, .
41 EF FNDP 1121/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 170235526 t fired, 23844504 attempts, .
43 EF STEQ 931/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1122 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1126/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 183826792 t fired, 13554110 attempts, .
41 EF FNDP 1126/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 170766150 t fired, 23918671 attempts, .
43 EF STEQ 936/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1127 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1131/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 184352413 t fired, 13592917 attempts, .
41 EF FNDP 1131/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 171294461 t fired, 23992388 attempts, .
43 EF STEQ 941/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1132 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1136/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 184875731 t fired, 13631544 attempts, .
41 EF FNDP 1136/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 171825932 t fired, 24067122 attempts, .
43 EF STEQ 946/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1137 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1141/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 185410966 t fired, 13671000 attempts, .
41 EF FNDP 1141/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 172405032 t fired, 24148191 attempts, .
43 EF STEQ 951/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1142 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1146/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 186115792 t fired, 13722920 attempts, .
41 EF FNDP 1146/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 173084100 t fired, 24243296 attempts, .
43 EF STEQ 956/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1147 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1151/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 186637583 t fired, 13761430 attempts, .
41 EF FNDP 1151/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 173615391 t fired, 24317857 attempts, .
43 EF STEQ 961/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1152 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1156/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 187162969 t fired, 13800114 attempts, .
41 EF FNDP 1156/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 174139878 t fired, 24391295 attempts, .
43 EF STEQ 966/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1157 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1161/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 187685448 t fired, 13838605 attempts, .
41 EF FNDP 1161/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 174671830 t fired, 24465730 attempts, .
43 EF STEQ 971/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1162 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1166/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 188208246 t fired, 13877159 attempts, .
41 EF FNDP 1166/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 175202337 t fired, 24540236 attempts, .
43 EF STEQ 976/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1167 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1171/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 188732521 t fired, 13915826 attempts, .
41 EF FNDP 1171/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 175731920 t fired, 24614484 attempts, .
43 EF STEQ 981/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1172 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1176/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 189256534 t fired, 13954425 attempts, .
41 EF FNDP 1176/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 176261781 t fired, 24688938 attempts, .
43 EF STEQ 986/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1177 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1181/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 189779397 t fired, 13993059 attempts, .
41 EF FNDP 1181/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 176791457 t fired, 24763061 attempts, .
43 EF STEQ 991/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1182 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1186/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 190302281 t fired, 14031592 attempts, .
41 EF FNDP 1186/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 177320068 t fired, 24837159 attempts, .
43 EF STEQ 996/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1187 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1191/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 190857922 t fired, 14072538 attempts, .
41 EF FNDP 1191/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 177932478 t fired, 24923128 attempts, .
43 EF STEQ 1001/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1192 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1196/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 191378498 t fired, 14110945 attempts, .
41 EF FNDP 1196/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 178462185 t fired, 24997136 attempts, .
43 EF STEQ 1006/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1197 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1201/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 191902283 t fired, 14149568 attempts, .
41 EF FNDP 1201/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 178990941 t fired, 25071139 attempts, .
43 EF STEQ 1011/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1202 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1206/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 192431141 t fired, 14188543 attempts, .
41 EF FNDP 1206/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 179524337 t fired, 25145883 attempts, .
43 EF STEQ 1016/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1207 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1211/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 192955094 t fired, 14227197 attempts, .
41 EF FNDP 1211/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 180053626 t fired, 25219944 attempts, .
43 EF STEQ 1021/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1212 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1216/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 193478496 t fired, 14265844 attempts, .
41 EF FNDP 1216/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 180609947 t fired, 25297704 attempts, .
43 EF STEQ 1026/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1217 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1221/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 194002941 t fired, 14304549 attempts, .
41 EF FNDP 1221/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 181141089 t fired, 25372113 attempts, .
43 EF STEQ 1031/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1222 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1226/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 194527032 t fired, 14343258 attempts, .
41 EF FNDP 1226/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 181655709 t fired, 25444033 attempts, .
43 EF STEQ 1036/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1227 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1231/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 195355635 t fired, 14404313 attempts, .
41 EF FNDP 1231/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 182534707 t fired, 25567190 attempts, .
43 EF STEQ 1041/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1232 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1236/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 196292507 t fired, 14473353 attempts, .
41 EF FNDP 1236/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 183471620 t fired, 25698438 attempts, .
43 EF STEQ 1046/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1237 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1241/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 196818275 t fired, 14512056 attempts, .
41 EF FNDP 1241/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 183999656 t fired, 25772447 attempts, .
43 EF STEQ 1051/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1242 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1246/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 197577345 t fired, 14568047 attempts, .
41 EF FNDP 1246/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 184817126 t fired, 25887000 attempts, .
43 EF STEQ 1056/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1247 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1251/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 198523381 t fired, 14637772 attempts, .
41 EF FNDP 1251/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 185755032 t fired, 26018726 attempts, .
43 EF STEQ 1061/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1252 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1256/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 199463978 t fired, 14707050 attempts, .
41 EF FNDP 1256/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 186693133 t fired, 26150340 attempts, .
43 EF STEQ 1066/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1257 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1261/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 200409644 t fired, 14776728 attempts, .
41 EF FNDP 1261/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 187627854 t fired, 26281143 attempts, .
43 EF STEQ 1071/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1262 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1266/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 201351644 t fired, 14846260 attempts, .
41 EF FNDP 1266/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 188566938 t fired, 26413026 attempts, .
43 EF STEQ 1076/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1267 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1271/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 202296705 t fired, 14915945 attempts, .
41 EF FNDP 1271/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 189504820 t fired, 26544350 attempts, .
43 EF STEQ 1081/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1272 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1276/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 203235529 t fired, 14985247 attempts, .
41 EF FNDP 1276/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 190440458 t fired, 26675501 attempts, .
43 EF STEQ 1086/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1277 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1281/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 204176672 t fired, 15054635 attempts, .
41 EF FNDP 1281/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 191377345 t fired, 26806879 attempts, .
43 EF STEQ 1091/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1282 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1286/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 205111327 t fired, 15123620 attempts, .
41 EF FNDP 1286/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 192312640 t fired, 26937889 attempts, .
43 EF STEQ 1096/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1287 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1291/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 206051299 t fired, 15192927 attempts, .
41 EF FNDP 1291/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 193241236 t fired, 27068095 attempts, .
43 EF STEQ 1101/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1292 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1296/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 206995151 t fired, 15262566 attempts, .
41 EF FNDP 1296/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 194171341 t fired, 27198510 attempts, .
43 EF STEQ 1106/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1297 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1301/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 207938711 t fired, 15332176 attempts, .
41 EF FNDP 1301/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 195102099 t fired, 27328962 attempts, .
43 EF STEQ 1111/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1302 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1306/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 208883604 t fired, 15401896 attempts, .
41 EF FNDP 1306/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 196034415 t fired, 27459599 attempts, .
43 EF STEQ 1116/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1307 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1311/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 209828379 t fired, 15471571 attempts, .
41 EF FNDP 1311/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 196967217 t fired, 27590331 attempts, .
43 EF STEQ 1121/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1312 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1316/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 210773550 t fired, 15541205 attempts, .
41 EF FNDP 1316/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 197898180 t fired, 27720551 attempts, .
43 EF STEQ 1126/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1317 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1321/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 211440662 t fired, 15590425 attempts, .
41 EF FNDP 1321/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 198604189 t fired, 27819358 attempts, .
43 EF STEQ 1131/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1322 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1326/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 212009068 t fired, 15632360 attempts, .
41 EF FNDP 1326/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 199181063 t fired, 27900086 attempts, .
43 EF STEQ 1136/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1327 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1331/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 212530883 t fired, 15670828 attempts, .
41 EF FNDP 1331/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 199710014 t fired, 27974059 attempts, .
43 EF STEQ 1141/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1333 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1337/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 213317415 t fired, 15728846 attempts, .
41 EF FNDP 1337/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 200500943 t fired, 28085045 attempts, .
43 EF STEQ 1147/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1338 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1342/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 214161223 t fired, 15791055 attempts, .
41 EF FNDP 1342/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 201379848 t fired, 28207932 attempts, .
43 EF STEQ 1152/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1343 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1347/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 215033917 t fired, 15855416 attempts, .
41 EF FNDP 1347/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 202272069 t fired, 28333203 attempts, .
43 EF STEQ 1157/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1348 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1352/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 215609914 t fired, 15897837 attempts, .
41 EF FNDP 1352/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 202870280 t fired, 28417127 attempts, .
43 EF STEQ 1162/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1353 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1357/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 216115431 t fired, 15935072 attempts, .
41 EF FNDP 1357/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 203381772 t fired, 28488792 attempts, .
43 EF STEQ 1167/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1358 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1362/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 216694112 t fired, 15977778 attempts, .
41 EF FNDP 1362/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 203968136 t fired, 28570948 attempts, .
43 EF STEQ 1172/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1363 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1367/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 217184126 t fired, 16013967 attempts, .
41 EF FNDP 1367/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 204461554 t fired, 28640389 attempts, .
43 EF STEQ 1177/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1368 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1372/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 217660301 t fired, 16049101 attempts, .
41 EF FNDP 1372/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 204944654 t fired, 28708067 attempts, .
43 EF STEQ 1182/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1373 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1377/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 218147569 t fired, 16085075 attempts, .
41 EF FNDP 1377/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 205438835 t fired, 28777435 attempts, .
43 EF STEQ 1187/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1378 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1382/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 218661832 t fired, 16122993 attempts, .
41 EF FNDP 1382/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 205957924 t fired, 28850195 attempts, .
43 EF STEQ 1192/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1383 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1387/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 219181129 t fired, 16161333 attempts, .
41 EF FNDP 1387/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 206482382 t fired, 28923596 attempts, .
43 EF STEQ 1197/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1388 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1392/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 219703016 t fired, 16199898 attempts, .
41 EF FNDP 1392/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 207013378 t fired, 28997926 attempts, .
43 EF STEQ 1202/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1393 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1397/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 220227488 t fired, 16238536 attempts, .
41 EF FNDP 1397/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 207542343 t fired, 29072041 attempts, .
43 EF STEQ 1207/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1398 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1402/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 220751415 t fired, 16277221 attempts, .
41 EF FNDP 1402/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 208070979 t fired, 29145978 attempts, .
43 EF STEQ 1212/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1403 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1407/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 221273792 t fired, 16315709 attempts, .
41 EF FNDP 1407/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 208601665 t fired, 29220658 attempts, .
43 EF STEQ 1217/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1408 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1412/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 221797437 t fired, 16354318 attempts, .
41 EF FNDP 1412/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 209129675 t fired, 29294602 attempts, .
43 EF STEQ 1222/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1413 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1417/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 222414843 t fired, 16399860 attempts, .
41 EF FNDP 1417/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 209803355 t fired, 29388895 attempts, .
43 EF STEQ 1227/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1418 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1422/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 222820282 t fired, 16429746 attempts, .
41 EF FNDP 1422/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 210135614 t fired, 29435322 attempts, .
43 EF STEQ 1232/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1423 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1427/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 223444135 t fired, 16475761 attempts, .
41 EF FNDP 1427/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 210550416 t fired, 29493500 attempts, .
43 EF STEQ 1237/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1428 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1432/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 224007233 t fired, 16517291 attempts, .
41 EF FNDP 1432/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 211267695 t fired, 29594241 attempts, .
43 EF STEQ 1242/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1433 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1437/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 224379328 t fired, 16544709 attempts, .
41 EF FNDP 1437/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 211593874 t fired, 29640045 attempts, .
43 EF STEQ 1247/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1438 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1442/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 224794252 t fired, 16575279 attempts, .
41 EF FNDP 1442/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 211948936 t fired, 29689876 attempts, .
43 EF STEQ 1252/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1443 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1447/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 225414455 t fired, 16621023 attempts, .
41 EF FNDP 1447/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 212464462 t fired, 29762218 attempts, .
43 EF STEQ 1257/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1448 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1452/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 225803752 t fired, 16649775 attempts, .
41 EF FNDP 1452/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 212767149 t fired, 29804783 attempts, .
43 EF STEQ 1262/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1453 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1457/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 226287707 t fired, 16685487 attempts, .
41 EF FNDP 1457/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 213117291 t fired, 29853716 attempts, .
43 EF STEQ 1267/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1458 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1462/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 226693115 t fired, 16715390 attempts, .
41 EF FNDP 1462/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 213466643 t fired, 29902740 attempts, .
43 EF STEQ 1272/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1463 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1467/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 227110885 t fired, 16746186 attempts, .
41 EF FNDP 1467/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 213824146 t fired, 29952775 attempts, .
43 EF STEQ 1277/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1468 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1472/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 227681382 t fired, 16788271 attempts, .
41 EF FNDP 1472/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 214449086 t fired, 30040357 attempts, .
43 EF STEQ 1282/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1473 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1477/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 228254217 t fired, 16830426 attempts, .
41 EF FNDP 1477/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 214846721 t fired, 30096228 attempts, .
43 EF STEQ 1287/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1478 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1482/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 228691550 t fired, 16862648 attempts, .
41 EF FNDP 1482/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 215180557 t fired, 30142728 attempts, .
43 EF STEQ 1292/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1483 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1487/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 229077123 t fired, 16891066 attempts, .
41 EF FNDP 1487/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 215453803 t fired, 30180873 attempts, .
43 EF STEQ 1297/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1488 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1492/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 229553670 t fired, 16926299 attempts, .
41 EF FNDP 1492/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 215871106 t fired, 30239253 attempts, .
43 EF STEQ 1302/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1493 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1497/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 229967948 t fired, 16956809 attempts, .
41 EF FNDP 1497/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 216172093 t fired, 30281364 attempts, .
43 EF STEQ 1307/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1498 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1502/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 230470087 t fired, 16993872 attempts, .
41 EF FNDP 1502/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 216650518 t fired, 30348284 attempts, .
43 EF STEQ 1312/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1503 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1507/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 230974012 t fired, 17031044 attempts, .
41 EF FNDP 1507/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 217149560 t fired, 30418317 attempts, .
43 EF STEQ 1317/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1508 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1512/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 231512264 t fired, 17070727 attempts, .
41 EF FNDP 1512/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 217632306 t fired, 30485909 attempts, .
43 EF STEQ 1322/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1513 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1517/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 232100798 t fired, 17114167 attempts, .
41 EF FNDP 1517/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 218043633 t fired, 30543588 attempts, .
43 EF STEQ 1327/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1518 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1522/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 233029287 t fired, 17182650 attempts, .
41 EF FNDP 1522/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 218570588 t fired, 30617642 attempts, .
43 EF STEQ 1332/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1523 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1527/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 233715557 t fired, 17233185 attempts, .
41 EF FNDP 1527/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 219373338 t fired, 30729792 attempts, .
43 EF STEQ 1337/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1528 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1532/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 234265564 t fired, 17273779 attempts, .
41 EF FNDP 1532/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 219875895 t fired, 30800233 attempts, .
43 EF STEQ 1342/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1533 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1537/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 234886287 t fired, 17319634 attempts, .
41 EF FNDP 1537/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 220347946 t fired, 30866258 attempts, .
43 EF STEQ 1347/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1538 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1542/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 235723578 t fired, 17381343 attempts, .
41 EF FNDP 1542/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 220984309 t fired, 30955537 attempts, .
43 EF STEQ 1352/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1543 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1547/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 236310279 t fired, 17424535 attempts, .
41 EF FNDP 1547/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 221454946 t fired, 31021533 attempts, .
43 EF STEQ 1357/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1548 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1552/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 237034487 t fired, 17477973 attempts, .
41 EF FNDP 1552/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 222026432 t fired, 31101647 attempts, .
43 EF STEQ 1362/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1553 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1557/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 237948328 t fired, 17545376 attempts, .
41 EF FNDP 1557/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 222947096 t fired, 31230647 attempts, .
43 EF STEQ 1367/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1558 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1562/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 238827776 t fired, 17610206 attempts, .
41 EF FNDP 1562/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 223840042 t fired, 31355811 attempts, .
43 EF STEQ 1372/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1563 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1567/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 239458173 t fired, 17656675 attempts, .
41 EF FNDP 1567/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 224552101 t fired, 31455571 attempts, .
43 EF STEQ 1377/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1568 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1572/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 239958662 t fired, 17693543 attempts, .
41 EF FNDP 1572/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 225164022 t fired, 31541574 attempts, .
43 EF STEQ 1382/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1573 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1577/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 240709186 t fired, 17748889 attempts, .
41 EF FNDP 1577/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 225926070 t fired, 31648257 attempts, .
43 EF STEQ 1387/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1578 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1582/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 241479362 t fired, 17805751 attempts, .
41 EF FNDP 1582/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 226682715 t fired, 31754394 attempts, .
43 EF STEQ 1392/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1583 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1587/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 241991869 t fired, 17843462 attempts, .
41 EF FNDP 1587/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 227166691 t fired, 31822241 attempts, .
43 EF STEQ 1397/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1588 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1592/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 242502107 t fired, 17881135 attempts, .
41 EF FNDP 1592/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 227675152 t fired, 31893393 attempts, .
43 EF STEQ 1402/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1593 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1597/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 243114440 t fired, 17926281 attempts, .
41 EF FNDP 1597/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 228150519 t fired, 31960209 attempts, .
43 EF STEQ 1407/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1598 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1602/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 243650239 t fired, 17965868 attempts, .
41 EF FNDP 1602/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 228636115 t fired, 32028228 attempts, .
43 EF STEQ 1412/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1603 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1607/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 244133736 t fired, 18001507 attempts, .
41 EF FNDP 1607/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 229095484 t fired, 32092689 attempts, .
43 EF STEQ 1417/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1608 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1612/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 244638280 t fired, 18038720 attempts, .
41 EF FNDP 1612/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 229693028 t fired, 32176663 attempts, .
43 EF STEQ 1422/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1613 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1617/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 245352590 t fired, 18091451 attempts, .
41 EF FNDP 1617/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 230350906 t fired, 32268806 attempts, .
43 EF STEQ 1427/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1618 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1622/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 246296828 t fired, 18161053 attempts, .
41 EF FNDP 1622/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 231269237 t fired, 32397409 attempts, .
43 EF STEQ 1432/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1623 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1627/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 247240111 t fired, 18230650 attempts, .
41 EF FNDP 1627/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 232199582 t fired, 32527512 attempts, .
43 EF STEQ 1437/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1628 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1632/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 248041781 t fired, 18289789 attempts, .
41 EF FNDP 1632/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 232952915 t fired, 32633378 attempts, .
43 EF STEQ 1442/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1633 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1637/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 248653144 t fired, 18334842 attempts, .
41 EF FNDP 1637/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 233432542 t fired, 32700391 attempts, .
43 EF STEQ 1447/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1638 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1642/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 249285261 t fired, 18381470 attempts, .
41 EF FNDP 1642/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 234067112 t fired, 32789173 attempts, .
43 EF STEQ 1452/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1643 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1647/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 250151230 t fired, 18445265 attempts, .
41 EF FNDP 1647/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 234562886 t fired, 32858641 attempts, .
43 EF STEQ 1457/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1648 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1652/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 250961535 t fired, 18504972 attempts, .
41 EF FNDP 1652/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 235022626 t fired, 32923178 attempts, .
43 EF STEQ 1462/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1653 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1657/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 251783637 t fired, 18565599 attempts, .
41 EF FNDP 1657/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 235813414 t fired, 33034066 attempts, .
43 EF STEQ 1467/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1658 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1662/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 252721343 t fired, 18634670 attempts, .
41 EF FNDP 1662/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 236729504 t fired, 33162516 attempts, .
43 EF STEQ 1472/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1663 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1667/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 253644011 t fired, 18702716 attempts, .
41 EF FNDP 1667/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 237630488 t fired, 33288682 attempts, .
43 EF STEQ 1477/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1668 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1672/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 254580924 t fired, 18771832 attempts, .
41 EF FNDP 1672/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 238556525 t fired, 33418416 attempts, .
43 EF STEQ 1482/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1673 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1677/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 255440785 t fired, 18835285 attempts, .
41 EF FNDP 1677/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 239501120 t fired, 33550462 attempts, .
43 EF STEQ 1487/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1678 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1682/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 256372221 t fired, 18903934 attempts, .
41 EF FNDP 1682/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 240453871 t fired, 33683678 attempts, .
43 EF STEQ 1492/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1683 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1687/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 257309313 t fired, 18972990 attempts, .
41 EF FNDP 1687/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 241211353 t fired, 33789857 attempts, .
43 EF STEQ 1497/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1688 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1692/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 257845435 t fired, 19012499 attempts, .
41 EF FNDP 1692/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 242048992 t fired, 33906811 attempts, .
43 EF STEQ 1502/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1693 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1697/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 258406555 t fired, 19053905 attempts, .
41 EF FNDP 1697/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 242638234 t fired, 33989313 attempts, .
43 EF STEQ 1507/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1698 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1702/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 259031837 t fired, 19100028 attempts, .
41 EF FNDP 1702/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 243196482 t fired, 34067813 attempts, .
43 EF STEQ 1512/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1703 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1707/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 259855043 t fired, 19160751 attempts, .
41 EF FNDP 1707/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 243917568 t fired, 34168655 attempts, .
43 EF STEQ 1517/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1708 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1712/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 260638713 t fired, 19218540 attempts, .
41 EF FNDP 1712/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 244555116 t fired, 34258091 attempts, .
43 EF STEQ 1522/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1713 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1717/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 261208065 t fired, 19260512 attempts, .
41 EF FNDP 1717/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 245205706 t fired, 34348950 attempts, .
43 EF STEQ 1527/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1718 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1722/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 261784281 t fired, 19303032 attempts, .
41 EF FNDP 1722/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 245897983 t fired, 34445660 attempts, .
43 EF STEQ 1532/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1723 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1727/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 262704371 t fired, 19370870 attempts, .
41 EF FNDP 1727/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 246814649 t fired, 34574284 attempts, .
43 EF STEQ 1537/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1728 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1732/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 263553163 t fired, 19433460 attempts, .
41 EF FNDP 1732/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 247637031 t fired, 34689423 attempts, .
43 EF STEQ 1542/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1733 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1737/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 264160428 t fired, 19478244 attempts, .
41 EF FNDP 1737/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 248247019 t fired, 34774704 attempts, .
43 EF STEQ 1547/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1738 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1742/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 264933472 t fired, 19535217 attempts, .
41 EF FNDP 1742/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 249143264 t fired, 34900446 attempts, .
43 EF STEQ 1552/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1743 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1747/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 265756820 t fired, 19596001 attempts, .
41 EF FNDP 1747/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 249696942 t fired, 34977935 attempts, .
43 EF STEQ 1557/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1748 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1752/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 266414375 t fired, 19644475 attempts, .
41 EF FNDP 1752/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 250384206 t fired, 35074001 attempts, .
43 EF STEQ 1562/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1753 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1757/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 267049544 t fired, 19691296 attempts, .
41 EF FNDP 1757/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 251091974 t fired, 35173205 attempts, .
43 EF STEQ 1567/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1758 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1762/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 267827687 t fired, 19748636 attempts, .
41 EF FNDP 1762/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 251754384 t fired, 35265997 attempts, .
43 EF STEQ 1572/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1763 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1767/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 268385066 t fired, 19789695 attempts, .
41 EF FNDP 1767/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 252591269 t fired, 35383147 attempts, .
43 EF STEQ 1577/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1768 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1772/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 268971676 t fired, 19833021 attempts, .
41 EF FNDP 1772/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 253402161 t fired, 35496821 attempts, .
43 EF STEQ 1582/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1773 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1777/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 269676938 t fired, 19885110 attempts, .
41 EF FNDP 1777/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 253995863 t fired, 35580041 attempts, .
43 EF STEQ 1587/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1778 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1782/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 270238064 t fired, 19926478 attempts, .
41 EF FNDP 1782/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 254538959 t fired, 35655879 attempts, .
43 EF STEQ 1592/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1783 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1787/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 270943914 t fired, 19978554 attempts, .
41 EF FNDP 1787/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 254992226 t fired, 35719420 attempts, .
43 EF STEQ 1597/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1788 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1792/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 271519788 t fired, 20021047 attempts, .
41 EF FNDP 1792/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 255506216 t fired, 35791591 attempts, .
43 EF STEQ 1602/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1793 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1797/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 272427343 t fired, 20087980 attempts, .
41 EF FNDP 1797/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 256011182 t fired, 35862444 attempts, .
43 EF STEQ 1607/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1798 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1802/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 272923177 t fired, 20124538 attempts, .
41 EF FNDP 1802/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 256579391 t fired, 35941990 attempts, .
43 EF STEQ 1612/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1803 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1807/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 273446844 t fired, 20163138 attempts, .
41 EF FNDP 1807/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 257131625 t fired, 36019492 attempts, .
43 EF STEQ 1617/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1808 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1812/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 274213618 t fired, 20219788 attempts, .
41 EF FNDP 1812/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 257991751 t fired, 36140203 attempts, .
43 EF STEQ 1622/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1813 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1817/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 275062802 t fired, 20282473 attempts, .
41 EF FNDP 1817/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 258681880 t fired, 36236856 attempts, .
43 EF STEQ 1627/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1818 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1822/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 276049797 t fired, 20355288 attempts, .
41 EF FNDP 1822/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 259388526 t fired, 36336045 attempts, .
43 EF STEQ 1632/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1823 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1827/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 277034386 t fired, 20427871 attempts, .
41 EF FNDP 1827/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 260362282 t fired, 36472145 attempts, .
43 EF STEQ 1637/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1828 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1832/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 277878805 t fired, 20490174 attempts, .
41 EF FNDP 1832/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 260850603 t fired, 36540431 attempts, .
43 EF STEQ 1642/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1833 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1837/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 278447379 t fired, 20532119 attempts, .
41 EF FNDP 1837/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 261352250 t fired, 36610903 attempts, .
43 EF STEQ 1647/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1838 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1842/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 279103412 t fired, 20580494 attempts, .
41 EF FNDP 1842/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 261878800 t fired, 36684710 attempts, .
43 EF STEQ 1652/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1843 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1847/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 279738202 t fired, 20627355 attempts, .
41 EF FNDP 1847/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 262583840 t fired, 36783131 attempts, .
43 EF STEQ 1657/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1848 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1852/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 280679193 t fired, 20696736 attempts, .
41 EF FNDP 1852/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 263516784 t fired, 36913845 attempts, .
43 EF STEQ 1662/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1853 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1857/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 281458563 t fired, 20754219 attempts, .
41 EF FNDP 1857/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 264348742 t fired, 37030552 attempts, .
43 EF STEQ 1667/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1858 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1862/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 282114173 t fired, 20802556 attempts, .
41 EF FNDP 1862/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 264896074 t fired, 37107191 attempts, .
43 EF STEQ 1672/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1863 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1867/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 283065680 t fired, 20872687 attempts, .
41 EF FNDP 1867/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 265676824 t fired, 37216342 attempts, .
43 EF STEQ 1677/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1868 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1872/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 283721371 t fired, 20920918 attempts, .
41 EF FNDP 1872/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 266175998 t fired, 37286281 attempts, .
43 EF STEQ 1682/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1873 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1877/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 284234895 t fired, 20958761 attempts, .
41 EF FNDP 1877/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 266709064 t fired, 37360776 attempts, .
43 EF STEQ 1687/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1878 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1882/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 284868214 t fired, 21005495 attempts, .
41 EF FNDP 1882/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 267675734 t fired, 37495899 attempts, .
43 EF STEQ 1692/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1883 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1887/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 285400994 t fired, 21044782 attempts, .
41 EF FNDP 1887/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 268296860 t fired, 37582909 attempts, .
43 EF STEQ 1697/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1888 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1892/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 286054271 t fired, 21092978 attempts, .
41 EF FNDP 1892/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 268905464 t fired, 37668051 attempts, .
43 EF STEQ 1702/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1893 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1897/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 287074535 t fired, 21168220 attempts, .
41 EF FNDP 1897/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 269557830 t fired, 37759224 attempts, .
43 EF STEQ 1707/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1898 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1902/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 287980923 t fired, 21235102 attempts, .
41 EF FNDP 1902/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 270066444 t fired, 37830271 attempts, .
43 EF STEQ 1712/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1903 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1907/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 288812205 t fired, 21296391 attempts, .
41 EF FNDP 1907/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 271003102 t fired, 37961535 attempts, .
43 EF STEQ 1717/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1908 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1912/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 289703327 t fired, 21362112 attempts, .
41 EF FNDP 1912/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 271711354 t fired, 38060429 attempts, .
43 EF STEQ 1722/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1913 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1917/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 290586120 t fired, 21427287 attempts, .
41 EF FNDP 1917/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 272370506 t fired, 38152850 attempts, .
43 EF STEQ 1727/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1918 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1922/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 291586860 t fired, 21501096 attempts, .
41 EF FNDP 1922/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 273367605 t fired, 38292899 attempts, .
43 EF STEQ 1732/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1923 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1927/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 292280539 t fired, 21552298 attempts, .
41 EF FNDP 1927/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 274253237 t fired, 38417201 attempts, .
43 EF STEQ 1737/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1928 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1932/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 292959898 t fired, 21602356 attempts, .
41 EF FNDP 1932/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 274993305 t fired, 38520911 attempts, .
43 EF STEQ 1742/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1933 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1937/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 293700883 t fired, 21657019 attempts, .
41 EF FNDP 1937/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 275926748 t fired, 38651761 attempts, .
43 EF STEQ 1747/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1938 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1942/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 294618533 t fired, 21724740 attempts, .
41 EF FNDP 1942/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 276886330 t fired, 38786206 attempts, .
43 EF STEQ 1752/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1943 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1947/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 295518284 t fired, 21791104 attempts, .
41 EF FNDP 1947/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 277806631 t fired, 38914823 attempts, .
43 EF STEQ 1757/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1948 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1952/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 296434472 t fired, 21858663 attempts, .
41 EF FNDP 1952/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 278632417 t fired, 39030558 attempts, .
43 EF STEQ 1762/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1953 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1957/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 297409410 t fired, 21930555 attempts, .
41 EF FNDP 1957/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 279500991 t fired, 39152096 attempts, .
43 EF STEQ 1767/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1958 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1962/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 298195674 t fired, 21988485 attempts, .
41 EF FNDP 1962/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 280287822 t fired, 39262409 attempts, .
43 EF STEQ 1772/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1963 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1967/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 298730164 t fired, 22027918 attempts, .
41 EF FNDP 1967/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 280715129 t fired, 39322140 attempts, .
43 EF STEQ 1777/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1968 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1972/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 299418738 t fired, 22078676 attempts, .
41 EF FNDP 1972/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 281541605 t fired, 39437738 attempts, .
43 EF STEQ 1782/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1973 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1977/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 300375459 t fired, 22149285 attempts, .
41 EF FNDP 1977/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 282058343 t fired, 39510111 attempts, .
43 EF STEQ 1787/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1978 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1982/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 301224823 t fired, 22211919 attempts, .
41 EF FNDP 1982/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 282666492 t fired, 39595242 attempts, .
43 EF STEQ 1792/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1983 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1987/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 302232840 t fired, 22286142 attempts, .
41 EF FNDP 1987/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 283168530 t fired, 39665411 attempts, .
43 EF STEQ 1797/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1988 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1992/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 302966365 t fired, 22340212 attempts, .
41 EF FNDP 1992/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 283643199 t fired, 39731937 attempts, .
43 EF STEQ 1802/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1993 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 1997/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 303666374 t fired, 22391862 attempts, .
41 EF FNDP 1997/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 284120772 t fired, 39798905 attempts, .
43 EF STEQ 1807/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 1998 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2002/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 304337922 t fired, 22441366 attempts, .
41 EF FNDP 2002/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 284755960 t fired, 39887824 attempts, .
43 EF STEQ 1812/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2003 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2007/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 305338891 t fired, 22515234 attempts, .
41 EF FNDP 2007/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 285317841 t fired, 39966520 attempts, .
43 EF STEQ 1817/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2008 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2012/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 306168609 t fired, 22576371 attempts, .
41 EF FNDP 2012/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 285793607 t fired, 40033220 attempts, .
43 EF STEQ 1822/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2013 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2017/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 306870065 t fired, 22628152 attempts, .
41 EF FNDP 2017/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 286278998 t fired, 40101286 attempts, .
43 EF STEQ 1827/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2018 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2022/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 307736397 t fired, 22691976 attempts, .
41 EF FNDP 2022/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 287176070 t fired, 40226780 attempts, .
43 EF STEQ 1832/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2023 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2027/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 308597370 t fired, 22755506 attempts, .
41 EF FNDP 2027/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 288129907 t fired, 40360262 attempts, .
43 EF STEQ 1837/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2028 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2032/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 309456960 t fired, 22818832 attempts, .
41 EF FNDP 2032/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 289000718 t fired, 40482238 attempts, .
43 EF STEQ 1842/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2033 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2037/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 310253168 t fired, 22877506 attempts, .
41 EF FNDP 2037/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 289830571 t fired, 40598508 attempts, .
43 EF STEQ 1847/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2038 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2042/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 311063089 t fired, 22937156 attempts, .
41 EF FNDP 2042/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 290594893 t fired, 40705562 attempts, .
43 EF STEQ 1852/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2043 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2047/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 311938022 t fired, 23001649 attempts, .
41 EF FNDP 2047/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 291230639 t fired, 40794527 attempts, .
43 EF STEQ 1857/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2048 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2052/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 312530165 t fired, 23045341 attempts, .
41 EF FNDP 2052/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 291801732 t fired, 40874629 attempts, .
43 EF STEQ 1862/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2053 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2057/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 313042095 t fired, 23083088 attempts, .
41 EF FNDP 2057/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 292316436 t fired, 40946607 attempts, .
43 EF STEQ 1867/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2058 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2062/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 313859380 t fired, 23143335 attempts, .
41 EF FNDP 2062/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 293214655 t fired, 41072568 attempts, .
43 EF STEQ 1872/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2063 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2067/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 314784467 t fired, 23211499 attempts, .
41 EF FNDP 2067/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 294157917 t fired, 41205033 attempts, .
43 EF STEQ 1877/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2068 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2072/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 315698588 t fired, 23278920 attempts, .
41 EF FNDP 2072/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 295102795 t fired, 41337452 attempts, .
43 EF STEQ 1882/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2073 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2077/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 316219704 t fired, 23317339 attempts, .
41 EF FNDP 2077/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 295677000 t fired, 41417866 attempts, .
43 EF STEQ 1887/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2078 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2082/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 316692547 t fired, 23352186 attempts, .
41 EF FNDP 2082/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 296218416 t fired, 41493523 attempts, .
43 EF STEQ 1892/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2083 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2087/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 317191745 t fired, 23388975 attempts, .
41 EF FNDP 2087/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 296775799 t fired, 41571788 attempts, .
43 EF STEQ 1897/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2088 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2092/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 318172535 t fired, 23461333 attempts, .
41 EF FNDP 2092/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 297773557 t fired, 41711190 attempts, .
43 EF STEQ 1902/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2093 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2097/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 319131332 t fired, 23531998 attempts, .
41 EF FNDP 2097/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 298695908 t fired, 41840554 attempts, .
43 EF STEQ 1907/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2098 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2102/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 320074032 t fired, 23601533 attempts, .
41 EF FNDP 2102/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 299184733 t fired, 41908996 attempts, .
43 EF STEQ 1912/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2103 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2107/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 321042433 t fired, 23672981 attempts, .
41 EF FNDP 2107/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 299661266 t fired, 41975472 attempts, .
43 EF STEQ 1917/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2108 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2112/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 322012875 t fired, 23744567 attempts, .
41 EF FNDP 2112/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 300141076 t fired, 42042504 attempts, .
43 EF STEQ 1922/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2113 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2117/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 322976257 t fired, 23815643 attempts, .
41 EF FNDP 2117/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 300619669 t fired, 42109409 attempts, .
43 EF STEQ 1927/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2118 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2122/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 323933341 t fired, 23886179 attempts, .
41 EF FNDP 2122/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 301101389 t fired, 42176860 attempts, .
43 EF STEQ 1932/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2123 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2127/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 324895729 t fired, 23957129 attempts, .
41 EF FNDP 2127/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 301579019 t fired, 42244024 attempts, .
43 EF STEQ 1937/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2128 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2132/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 325839309 t fired, 24026694 attempts, .
41 EF FNDP 2132/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 302055738 t fired, 42310909 attempts, .
43 EF STEQ 1942/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2133 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2137/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 326808492 t fired, 24098166 attempts, .
41 EF FNDP 2137/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 302533797 t fired, 42377675 attempts, .
43 EF STEQ 1947/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2138 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2142/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 327522236 t fired, 24150804 attempts, .
41 EF FNDP 2142/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 303056191 t fired, 42450876 attempts, .
43 EF STEQ 1952/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2143 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2147/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 328383275 t fired, 24214263 attempts, .
41 EF FNDP 2147/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 303968235 t fired, 42578414 attempts, .
43 EF STEQ 1957/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2148 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2152/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 329265973 t fired, 24279350 attempts, .
41 EF FNDP 2152/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 304896798 t fired, 42708453 attempts, .
43 EF STEQ 1962/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2153 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2157/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 330120382 t fired, 24342322 attempts, .
41 EF FNDP 2157/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 305803911 t fired, 42835490 attempts, .
43 EF STEQ 1967/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2158 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2162/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 330915875 t fired, 24401071 attempts, .
41 EF FNDP 2162/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 306443634 t fired, 42925136 attempts, .
43 EF STEQ 1972/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2163 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2167/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 331730306 t fired, 24461172 attempts, .
41 EF FNDP 2167/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 307249465 t fired, 43038211 attempts, .
43 EF STEQ 1977/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2168 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2172/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 332674356 t fired, 24530796 attempts, .
41 EF FNDP 2172/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 308183809 t fired, 43169614 attempts, .
43 EF STEQ 1982/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2173 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2177/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 333380705 t fired, 24582806 attempts, .
41 EF FNDP 2177/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 308885758 t fired, 43267716 attempts, .
43 EF STEQ 1987/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2178 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2182/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 334325209 t fired, 24652394 attempts, .
41 EF FNDP 2182/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 309817936 t fired, 43398152 attempts, .
43 EF STEQ 1992/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2183 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2187/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 335269733 t fired, 24721986 attempts, .
41 EF FNDP 2187/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 310753172 t fired, 43529356 attempts, .
43 EF STEQ 1997/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2188 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2192/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 336089712 t fired, 24782502 attempts, .
41 EF FNDP 2192/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 311446077 t fired, 43626398 attempts, .
43 EF STEQ 2002/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2193 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2197/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 336911313 t fired, 24843052 attempts, .
41 EF FNDP 2197/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 311944109 t fired, 43696164 attempts, .
43 EF STEQ 2007/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2198 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2202/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 337600648 t fired, 24893938 attempts, .
41 EF FNDP 2202/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 312523626 t fired, 43777287 attempts, .
43 EF STEQ 2012/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2203 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2208/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 338170671 t fired, 24935982 attempts, .
41 EF FNDP 2208/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 313117583 t fired, 43860688 attempts, .
43 EF STEQ 2018/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2209 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2213/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 338709294 t fired, 24975651 attempts, .
41 EF FNDP 2213/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 313665519 t fired, 43937407 attempts, .
43 EF STEQ 2023/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2214 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2218/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 339316147 t fired, 25020386 attempts, .
41 EF FNDP 2218/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 314463760 t fired, 44049158 attempts, .
43 EF STEQ 2028/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2219 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2223/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 340189467 t fired, 25084790 attempts, .
41 EF FNDP 2223/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 315310004 t fired, 44167688 attempts, .
43 EF STEQ 2033/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2224 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2228/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 340972025 t fired, 25142520 attempts, .
41 EF FNDP 2228/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 316285183 t fired, 44303924 attempts, .
43 EF STEQ 2038/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2229 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2233/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 341728094 t fired, 25198253 attempts, .
41 EF FNDP 2233/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 317119695 t fired, 44420658 attempts, .
43 EF STEQ 2043/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2234 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2238/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 342458301 t fired, 25252072 attempts, .
41 EF FNDP 2238/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 318008007 t fired, 44544895 attempts, .
43 EF STEQ 2048/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2239 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2243/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 343335735 t fired, 25316757 attempts, .
41 EF FNDP 2243/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 318880058 t fired, 44667152 attempts, .
43 EF STEQ 2053/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2244 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2248/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 343757569 t fired, 25347844 attempts, .
41 EF FNDP 2248/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 319415470 t fired, 44741928 attempts, .
43 EF STEQ 2058/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2249 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2253/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 344456984 t fired, 25399413 attempts, .
41 EF FNDP 2253/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 320179857 t fired, 44848970 attempts, .
43 EF STEQ 2063/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2254 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2258/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 345083876 t fired, 25445618 attempts, .
41 EF FNDP 2258/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 321121899 t fired, 44980824 attempts, .
43 EF STEQ 2068/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2259 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2263/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 346026637 t fired, 25515104 attempts, .
41 EF FNDP 2263/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 322073196 t fired, 45114268 attempts, .
43 EF STEQ 2073/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2264 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2268/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 346773475 t fired, 25570216 attempts, .
41 EF FNDP 2268/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 322792264 t fired, 45214653 attempts, .
43 EF STEQ 2078/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2269 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2273/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 347598369 t fired, 25631022 attempts, .
41 EF FNDP 2273/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 323569629 t fired, 45323644 attempts, .
43 EF STEQ 2083/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2274 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2278/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 348427414 t fired, 25692111 attempts, .
41 EF FNDP 2278/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 324424418 t fired, 45443786 attempts, .
43 EF STEQ 2088/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2279 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2283/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 349367556 t fired, 25761493 attempts, .
41 EF FNDP 2283/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 324996005 t fired, 45523519 attempts, .
43 EF STEQ 2093/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2284 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2288/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 350187321 t fired, 25821949 attempts, .
41 EF FNDP 2288/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 325840782 t fired, 45641796 attempts, .
43 EF STEQ 2098/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2289 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2293/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 351047016 t fired, 25885319 attempts, .
41 EF FNDP 2293/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 326701639 t fired, 45762089 attempts, .
43 EF STEQ 2103/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2294 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 2 0 2 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2299/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 351198101 t fired, 25896470 attempts, .
41 EF FNDP 2299/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 326917042 t fired, 45792251 attempts, .
43 EF STEQ 2109/3409 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 sara is running.

Time elapsed: 2300 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 13
lola: FINISHED task # 43 (type EQUN) for SieveSingleMsgMbox-PT-d1m36-CTLFireability-12
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2304/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 352102598 t fired, 25963105 attempts, .
41 EF FNDP 2304/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 327872138 t fired, 45926438 attempts, .

Time elapsed: 2305 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2309/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 353028577 t fired, 26031404 attempts, .
41 EF FNDP 2309/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 328827228 t fired, 46060309 attempts, .

Time elapsed: 2310 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2314/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 353996164 t fired, 26102645 attempts, .
41 EF FNDP 2314/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 329689130 t fired, 46181050 attempts, .

Time elapsed: 2315 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2319/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 354921637 t fired, 26170824 attempts, .
41 EF FNDP 2319/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 330648137 t fired, 46315160 attempts, .

Time elapsed: 2320 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2324/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 355848961 t fired, 26239138 attempts, .
41 EF FNDP 2324/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 331609867 t fired, 46449540 attempts, .

Time elapsed: 2325 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2329/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 356775019 t fired, 26307358 attempts, .
41 EF FNDP 2329/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 332570265 t fired, 46583653 attempts, .

Time elapsed: 2330 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2334/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 357735531 t fired, 26378203 attempts, .
41 EF FNDP 2334/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 333491928 t fired, 46712914 attempts, .

Time elapsed: 2335 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2339/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 358727640 t fired, 26451265 attempts, .
41 EF FNDP 2339/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 334500371 t fired, 46854077 attempts, .

Time elapsed: 2340 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2344/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 359630152 t fired, 26517819 attempts, .
41 EF FNDP 2344/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 335415012 t fired, 46982381 attempts, .

Time elapsed: 2345 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2349/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 360545187 t fired, 26585270 attempts, .
41 EF FNDP 2349/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 336338736 t fired, 47111953 attempts, .

Time elapsed: 2350 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-12: EF 0 0 1 0 3 0 1 0
SieveSingleMsgMbox-PT-d1m36-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 EF FNDP 2354/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-12 361504354 t fired, 26655985 attempts, .
41 EF FNDP 2354/3599 0/5 SieveSingleMsgMbox-PT-d1m36-CTLFireability-13 337303224 t fired, 47247172 attempts, .

Time elapsed: 2355 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m36-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-06: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-07: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-10: F false state space / EG
SieveSingleMsgMbox-PT-d1m36-CTLFireability-11: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m36-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m36-CTLFireability-04: CTL 0 0 0 0 1 0 1 0

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed