Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2023-input.r423-tajo-167905976600322.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.....................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ShieldRVt-PT-050A, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-tajo-167905976600322
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 620K
-rw-r--r-- 1 mcc users 6.6K Feb 25 23:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 25 23:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 25 23:10 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 23:10 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 17:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 17:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 00:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 138K Feb 26 00:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.7K Feb 26 00:01 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 87K Feb 26 00:01 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 136K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-00
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-01
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-02
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-03
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-04
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-05
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-06
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-07
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-08
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-09
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-10
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-11
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-12
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-13
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-14
FORMULA_NAME ShieldRVt-PT-050A-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679246024624

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ShieldRVt-PT-050A
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 17:13:46] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 17:13:46] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 17:13:46] [INFO ] Load time of PNML (sax parser for PT used): 76 ms
[2023-03-19 17:13:46] [INFO ] Transformed 403 places.
[2023-03-19 17:13:46] [INFO ] Transformed 403 transitions.
[2023-03-19 17:13:46] [INFO ] Found NUPN structural information;
[2023-03-19 17:13:46] [INFO ] Parsed PT model containing 403 places and 403 transitions and 1706 arcs in 141 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 6 ms.
Initial state reduction rules removed 1 formulas.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
FORMULA ShieldRVt-PT-050A-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 186 out of 403 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 35 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
// Phase 1: matrix 402 rows 403 cols
[2023-03-19 17:13:46] [INFO ] Computed 201 place invariants in 12 ms
[2023-03-19 17:13:46] [INFO ] Implicit Places using invariants in 304 ms returned []
[2023-03-19 17:13:46] [INFO ] Invariant cache hit.
[2023-03-19 17:13:46] [INFO ] Implicit Places using invariants and state equation in 390 ms returned []
Implicit Place search using SMT with State Equation took 717 ms to find 0 implicit places.
[2023-03-19 17:13:46] [INFO ] Invariant cache hit.
[2023-03-19 17:13:47] [INFO ] Dead Transitions using invariants and state equation in 263 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1018 ms. Remains : 403/403 places, 402/402 transitions.
Support contains 186 out of 403 places after structural reductions.
[2023-03-19 17:13:47] [INFO ] Flatten gal took : 70 ms
[2023-03-19 17:13:47] [INFO ] Flatten gal took : 48 ms
[2023-03-19 17:13:47] [INFO ] Input system was already deterministic with 402 transitions.
Support contains 176 out of 403 places (down from 186) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 432 ms. (steps per millisecond=23 ) properties (out of 82) seen :21
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 61) seen :0
Running SMT prover for 61 properties.
[2023-03-19 17:13:48] [INFO ] Invariant cache hit.
[2023-03-19 17:13:49] [INFO ] [Real]Absence check using 201 positive place invariants in 36 ms returned sat
[2023-03-19 17:13:49] [INFO ] After 716ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:61
[2023-03-19 17:13:49] [INFO ] [Nat]Absence check using 201 positive place invariants in 76 ms returned sat
[2023-03-19 17:13:51] [INFO ] After 1734ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :61
[2023-03-19 17:13:54] [INFO ] After 4103ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :61
Attempting to minimize the solution found.
Minimization took 1936 ms.
[2023-03-19 17:13:56] [INFO ] After 6854ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :61
Parikh walk visited 11 properties in 1963 ms.
Support contains 114 out of 403 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 403/403 places, 402/402 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 402 transition count 401
Partial Free-agglomeration rule applied 32 times.
Drop transitions removed 32 transitions
Iterating global reduction 0 with 32 rules applied. Total rules applied 34 place count 402 transition count 401
Drop transitions removed 32 transitions
Redundant transition composition rules discarded 32 transitions
Iterating global reduction 0 with 32 rules applied. Total rules applied 66 place count 402 transition count 369
Applied a total of 66 rules in 61 ms. Remains 402 /403 variables (removed 1) and now considering 369/402 (removed 33) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 62 ms. Remains : 402/403 places, 369/402 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 257 ms. (steps per millisecond=38 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 50) seen :0
Interrupted probabilistic random walk after 456039 steps, run timeout after 3001 ms. (steps per millisecond=151 ) properties seen :{0=1, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 12=1, 13=1, 14=1, 15=1, 16=1, 17=1, 18=1, 19=1, 20=1, 21=1, 22=1, 23=1, 24=1, 25=1, 26=1, 27=1, 28=1, 29=1, 30=1, 31=1, 32=1, 33=1, 34=1, 35=1, 36=1, 37=1, 38=1, 39=1, 40=1, 41=1, 42=1, 43=1, 44=1, 45=1, 46=1, 47=1, 48=1, 49=1}
Probabilistic random walk after 456039 steps, saw 445780 distinct states, run finished after 3001 ms. (steps per millisecond=151 ) properties seen :49
Running SMT prover for 1 properties.
// Phase 1: matrix 369 rows 402 cols
[2023-03-19 17:14:01] [INFO ] Computed 201 place invariants in 8 ms
[2023-03-19 17:14:01] [INFO ] [Real]Absence check using 201 positive place invariants in 25 ms returned sat
[2023-03-19 17:14:01] [INFO ] After 134ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:14:02] [INFO ] [Nat]Absence check using 201 positive place invariants in 22 ms returned sat
[2023-03-19 17:14:02] [INFO ] After 229ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:14:02] [INFO ] State equation strengthened by 2 read => feed constraints.
[2023-03-19 17:14:02] [INFO ] After 21ms SMT Verify possible using 2 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:14:02] [INFO ] After 52ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 26 ms.
[2023-03-19 17:14:02] [INFO ] After 406ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 5 ms.
Support contains 8 out of 402 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 402/402 places, 369/369 transitions.
Partial Free-agglomeration rule applied 16 times.
Drop transitions removed 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 16 place count 402 transition count 369
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 402 transition count 353
Applied a total of 32 rules in 66 ms. Remains 402 /402 variables (removed 0) and now considering 353/369 (removed 16) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 67 ms. Remains : 402/402 places, 353/369 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 575322 steps, run timeout after 3001 ms. (steps per millisecond=191 ) properties seen :{}
Probabilistic random walk after 575322 steps, saw 562840 distinct states, run finished after 3002 ms. (steps per millisecond=191 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 353 rows 402 cols
[2023-03-19 17:14:05] [INFO ] Computed 201 place invariants in 4 ms
[2023-03-19 17:14:05] [INFO ] [Real]Absence check using 201 positive place invariants in 27 ms returned sat
[2023-03-19 17:14:05] [INFO ] After 168ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:14:05] [INFO ] [Nat]Absence check using 201 positive place invariants in 21 ms returned sat
[2023-03-19 17:14:05] [INFO ] After 136ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:14:05] [INFO ] State equation strengthened by 2 read => feed constraints.
[2023-03-19 17:14:05] [INFO ] After 15ms SMT Verify possible using 2 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:14:05] [INFO ] After 38ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 16 ms.
[2023-03-19 17:14:05] [INFO ] After 297ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 4 ms.
Support contains 8 out of 402 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 402/402 places, 353/353 transitions.
Applied a total of 0 rules in 12 ms. Remains 402 /402 variables (removed 0) and now considering 353/353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 12 ms. Remains : 402/402 places, 353/353 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 402/402 places, 353/353 transitions.
Applied a total of 0 rules in 13 ms. Remains 402 /402 variables (removed 0) and now considering 353/353 (removed 0) transitions.
[2023-03-19 17:14:05] [INFO ] Invariant cache hit.
[2023-03-19 17:14:06] [INFO ] Implicit Places using invariants in 189 ms returned [395]
Discarding 1 places :
Implicit Place search using SMT only with invariants took 191 ms to find 1 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 1 : 401/402 places, 353/353 transitions.
Applied a total of 0 rules in 12 ms. Remains 401 /401 variables (removed 0) and now considering 353/353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 2 iterations and 216 ms. Remains : 401/402 places, 353/353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 606902 steps, run timeout after 3001 ms. (steps per millisecond=202 ) properties seen :{}
Probabilistic random walk after 606902 steps, saw 593390 distinct states, run finished after 3002 ms. (steps per millisecond=202 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 353 rows 401 cols
[2023-03-19 17:14:09] [INFO ] Computed 200 place invariants in 5 ms
[2023-03-19 17:14:09] [INFO ] [Real]Absence check using 200 positive place invariants in 23 ms returned sat
[2023-03-19 17:14:09] [INFO ] After 105ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:14:09] [INFO ] [Nat]Absence check using 200 positive place invariants in 21 ms returned sat
[2023-03-19 17:14:09] [INFO ] After 120ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:14:09] [INFO ] After 151ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 19 ms.
[2023-03-19 17:14:09] [INFO ] After 270ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 6 ms.
Support contains 8 out of 401 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 401/401 places, 353/353 transitions.
Applied a total of 0 rules in 13 ms. Remains 401 /401 variables (removed 0) and now considering 353/353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 13 ms. Remains : 401/401 places, 353/353 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 401/401 places, 353/353 transitions.
Applied a total of 0 rules in 12 ms. Remains 401 /401 variables (removed 0) and now considering 353/353 (removed 0) transitions.
[2023-03-19 17:14:09] [INFO ] Invariant cache hit.
[2023-03-19 17:14:09] [INFO ] Implicit Places using invariants in 184 ms returned []
[2023-03-19 17:14:09] [INFO ] Invariant cache hit.
[2023-03-19 17:14:10] [INFO ] Implicit Places using invariants and state equation in 386 ms returned []
Implicit Place search using SMT with State Equation took 572 ms to find 0 implicit places.
[2023-03-19 17:14:10] [INFO ] Redundant transitions in 18 ms returned []
[2023-03-19 17:14:10] [INFO ] Invariant cache hit.
[2023-03-19 17:14:10] [INFO ] Dead Transitions using invariants and state equation in 162 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 770 ms. Remains : 401/401 places, 353/353 transitions.
Applied a total of 0 rules in 11 ms. Remains 401 /401 variables (removed 0) and now considering 353/353 (removed 0) transitions.
Running SMT prover for 1 properties.
[2023-03-19 17:14:10] [INFO ] Invariant cache hit.
[2023-03-19 17:14:10] [INFO ] [Real]Absence check using 200 positive place invariants in 24 ms returned sat
[2023-03-19 17:14:10] [INFO ] After 116ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:14:10] [INFO ] [Nat]Absence check using 200 positive place invariants in 24 ms returned sat
[2023-03-19 17:14:10] [INFO ] After 134ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:14:10] [INFO ] After 161ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 26 ms.
[2023-03-19 17:14:10] [INFO ] After 283ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:14:10] [INFO ] Flatten gal took : 29 ms
[2023-03-19 17:14:10] [INFO ] Flatten gal took : 25 ms
[2023-03-19 17:14:10] [INFO ] Input system was already deterministic with 402 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Reduce places removed 1 places and 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 400 transition count 400
Applied a total of 3 rules in 19 ms. Remains 400 /403 variables (removed 3) and now considering 400/402 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 400/403 places, 400/402 transitions.
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 15 ms
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 16 ms
[2023-03-19 17:14:11] [INFO ] Input system was already deterministic with 400 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 1) seen :0
Finished probabilistic random walk after 2070 steps, run visited all 1 properties in 16 ms. (steps per millisecond=129 )
Probabilistic random walk after 2070 steps, saw 1971 distinct states, run finished after 16 ms. (steps per millisecond=129 ) properties seen :1
FORMULA ShieldRVt-PT-050A-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 4 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 403/403 places, 402/402 transitions.
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 24 ms
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 24 ms
[2023-03-19 17:14:11] [INFO ] Input system was already deterministic with 402 transitions.
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 5 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 403/403 places, 402/402 transitions.
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 22 ms
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 22 ms
[2023-03-19 17:14:11] [INFO ] Input system was already deterministic with 402 transitions.
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 4 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 403/403 places, 402/402 transitions.
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 20 ms
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 19 ms
[2023-03-19 17:14:11] [INFO ] Input system was already deterministic with 402 transitions.
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 4 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 403/403 places, 402/402 transitions.
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 19 ms
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 18 ms
[2023-03-19 17:14:11] [INFO ] Input system was already deterministic with 402 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 402 transition count 401
Applied a total of 2 rules in 20 ms. Remains 402 /403 variables (removed 1) and now considering 401/402 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 402/403 places, 401/402 transitions.
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 14 ms
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 14 ms
[2023-03-19 17:14:11] [INFO ] Input system was already deterministic with 401 transitions.
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 4 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 403/403 places, 402/402 transitions.
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 13 ms
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 14 ms
[2023-03-19 17:14:11] [INFO ] Input system was already deterministic with 402 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 402 transition count 401
Applied a total of 2 rules in 15 ms. Remains 402 /403 variables (removed 1) and now considering 401/402 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 402/403 places, 401/402 transitions.
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 13 ms
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 14 ms
[2023-03-19 17:14:11] [INFO ] Input system was already deterministic with 401 transitions.
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 3 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 403/403 places, 402/402 transitions.
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 14 ms
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 15 ms
[2023-03-19 17:14:11] [INFO ] Input system was already deterministic with 402 transitions.
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 11 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 403/403 places, 402/402 transitions.
[2023-03-19 17:14:11] [INFO ] Flatten gal took : 13 ms
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 14 ms
[2023-03-19 17:14:12] [INFO ] Input system was already deterministic with 402 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 402 transition count 401
Applied a total of 2 rules in 14 ms. Remains 402 /403 variables (removed 1) and now considering 401/402 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 402/403 places, 401/402 transitions.
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 12 ms
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 13 ms
[2023-03-19 17:14:12] [INFO ] Input system was already deterministic with 401 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 1) seen :0
Finished probabilistic random walk after 2630 steps, run visited all 1 properties in 22 ms. (steps per millisecond=119 )
Probabilistic random walk after 2630 steps, saw 2517 distinct states, run finished after 22 ms. (steps per millisecond=119 ) properties seen :1
FORMULA ShieldRVt-PT-050A-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 3 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 403/403 places, 402/402 transitions.
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 12 ms
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 13 ms
[2023-03-19 17:14:12] [INFO ] Input system was already deterministic with 402 transitions.
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 3 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 403/403 places, 402/402 transitions.
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 12 ms
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 12 ms
[2023-03-19 17:14:12] [INFO ] Input system was already deterministic with 402 transitions.
Starting structural reductions in LTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Applied a total of 0 rules in 3 ms. Remains 403 /403 variables (removed 0) and now considering 402/402 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 403/403 places, 402/402 transitions.
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 12 ms
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 13 ms
[2023-03-19 17:14:12] [INFO ] Input system was already deterministic with 402 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 403/403 places, 402/402 transitions.
Reduce places removed 1 places and 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 400 transition count 400
Applied a total of 3 rules in 16 ms. Remains 400 /403 variables (removed 3) and now considering 400/402 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 400/403 places, 400/402 transitions.
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 9 ms
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 9 ms
[2023-03-19 17:14:12] [INFO ] Input system was already deterministic with 400 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 1) seen :0
Finished probabilistic random walk after 2070 steps, run visited all 1 properties in 15 ms. (steps per millisecond=138 )
Probabilistic random walk after 2070 steps, saw 1971 distinct states, run finished after 15 ms. (steps per millisecond=138 ) properties seen :1
FORMULA ShieldRVt-PT-050A-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 13 ms
[2023-03-19 17:14:12] [INFO ] Flatten gal took : 14 ms
[2023-03-19 17:14:12] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-19 17:14:12] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 403 places, 402 transitions and 1704 arcs took 2 ms.
Total runtime 26582 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ShieldRVt-PT-050A
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

FORMULA ShieldRVt-PT-050A-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVt-PT-050A-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVt-PT-050A-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVt-PT-050A-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVt-PT-050A-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679246200802

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 4 (type EXCL) for 3 ShieldRVt-PT-050A-CTLFireability-02
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 4 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-02
lola: result : true
lola: markings : 226
lola: fired transitions : 226
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 ShieldRVt-PT-050A-CTLFireability-01
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-01
lola: result : true
lola: markings : 68
lola: fired transitions : 68
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 ShieldRVt-PT-050A-CTLFireability-07
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:717
lola: rewrite Frontend/Parser/formula_rewrite.k:689
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 6 0 0 6 0 0 0
ShieldRVt-PT-050A-CTLFireability-13: CONJ 0 6 0 0 6 0 0 0
ShieldRVt-PT-050A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/179 13/32 ShieldRVt-PT-050A-CTLFireability-07 1809875 m, 361975 m/sec, 1990710 t fired, .

Time elapsed: 6 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 6 0 0 6 0 0 0
ShieldRVt-PT-050A-CTLFireability-13: CONJ 0 6 0 0 6 0 0 0
ShieldRVt-PT-050A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/179 26/32 ShieldRVt-PT-050A-CTLFireability-07 3693966 m, 376818 m/sec, 4061868 t fired, .

Time elapsed: 11 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 19 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 6 0 0 6 0 0 0
ShieldRVt-PT-050A-CTLFireability-13: CONJ 0 6 0 0 6 0 0 0
ShieldRVt-PT-050A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 16 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 74 (type EXCL) for 73 ShieldRVt-PT-050A-CTLFireability-14
lola: time limit : 188 sec
lola: memory limit: 32 pages
lola: FINISHED task # 74 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-14
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 71 (type EXCL) for 50 ShieldRVt-PT-050A-CTLFireability-13
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 71 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-13
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 69 (type EXCL) for 50 ShieldRVt-PT-050A-CTLFireability-13
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: FINISHED task # 69 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-13
lola: result : true
lola: markings : 53
lola: fired transitions : 52
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 65 (type EXCL) for 50 ShieldRVt-PT-050A-CTLFireability-13
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 65 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-13
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 27 ShieldRVt-PT-050A-CTLFireability-11
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-11
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 27 ShieldRVt-PT-050A-CTLFireability-11
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-11
lola: result : true
lola: markings : 38
lola: fired transitions : 37
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 ShieldRVt-PT-050A-CTLFireability-09
lola: time limit : 512 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/512 10/32 ShieldRVt-PT-050A-CTLFireability-09 1807898 m, 361579 m/sec, 2465576 t fired, .

Time elapsed: 21 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/512 17/32 ShieldRVt-PT-050A-CTLFireability-09 3521079 m, 342636 m/sec, 4802641 t fired, .

Time elapsed: 26 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/512 25/32 ShieldRVt-PT-050A-CTLFireability-09 5185455 m, 332875 m/sec, 7073187 t fired, .

Time elapsed: 31 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/512 32/32 ShieldRVt-PT-050A-CTLFireability-09 6835918 m, 330092 m/sec, 9324385 t fired, .

Time elapsed: 36 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 25 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 41 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 22 (type EXCL) for 21 ShieldRVt-PT-050A-CTLFireability-08
lola: time limit : 593 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-08
lola: result : true
lola: markings : 120
lola: fired transitions : 122
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 ShieldRVt-PT-050A-CTLFireability-06
lola: time limit : 711 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/711 14/32 ShieldRVt-PT-050A-CTLFireability-06 1889786 m, 377957 m/sec, 2077984 t fired, .

Time elapsed: 46 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/711 27/32 ShieldRVt-PT-050A-CTLFireability-06 3822261 m, 386495 m/sec, 4202336 t fired, .

Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 16 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 10 (type EXCL) for 9 ShieldRVt-PT-050A-CTLFireability-04
lola: time limit : 886 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/886 13/32 ShieldRVt-PT-050A-CTLFireability-04 1815581 m, 363116 m/sec, 1995830 t fired, .

Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/886 26/32 ShieldRVt-PT-050A-CTLFireability-04 3664500 m, 369783 m/sec, 4028331 t fired, .

Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 10 (type EXCL) for ShieldRVt-PT-050A-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 7 (type EXCL) for 6 ShieldRVt-PT-050A-CTLFireability-03
lola: time limit : 1176 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/1176 3/32 ShieldRVt-PT-050A-CTLFireability-03 398073 m, 79614 m/sec, 835648 t fired, .

Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/1176 6/32 ShieldRVt-PT-050A-CTLFireability-03 812785 m, 82942 m/sec, 1706249 t fired, .

Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/1176 9/32 ShieldRVt-PT-050A-CTLFireability-03 1231882 m, 83819 m/sec, 2586056 t fired, .

Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/1176 12/32 ShieldRVt-PT-050A-CTLFireability-03 1648384 m, 83300 m/sec, 3460414 t fired, .

Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/1176 15/32 ShieldRVt-PT-050A-CTLFireability-03 2069775 m, 84278 m/sec, 4345037 t fired, .

Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/1176 17/32 ShieldRVt-PT-050A-CTLFireability-03 2369181 m, 59881 m/sec, 4973579 t fired, .

Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/1176 19/32 ShieldRVt-PT-050A-CTLFireability-03 2624248 m, 51013 m/sec, 5509038 t fired, .

Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/1176 21/32 ShieldRVt-PT-050A-CTLFireability-03 2853639 m, 45878 m/sec, 5990596 t fired, .

Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/1176 22/32 ShieldRVt-PT-050A-CTLFireability-03 3104570 m, 50186 m/sec, 6517369 t fired, .

Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/1176 23/32 ShieldRVt-PT-050A-CTLFireability-03 3279810 m, 35048 m/sec, 6885251 t fired, .

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 55/1176 25/32 ShieldRVt-PT-050A-CTLFireability-03 3451668 m, 34371 m/sec, 7246034 t fired, .

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 60/1176 26/32 ShieldRVt-PT-050A-CTLFireability-03 3603826 m, 30431 m/sec, 7565458 t fired, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 65/1176 27/32 ShieldRVt-PT-050A-CTLFireability-03 3781358 m, 35506 m/sec, 7938148 t fired, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-050A-CTLFireability-01: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-02: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-08: CTL true CTL model checker
ShieldRVt-PT-050A-CTLFireability-13: CONJ false CTL model checker
ShieldRVt-PT-050A-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-050A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-050A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-050A-CTLFireability-11: CONJ 0 1 0 0 8 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 70/1176 28/32 ShieldRVt-PT-050A-CTLFireability-03 3977771 m, 39282 m/sec, 8350477 t fired, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 538 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldRVt-PT-050A"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ShieldRVt-PT-050A, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-tajo-167905976600322"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ShieldRVt-PT-050A.tgz
mv ShieldRVt-PT-050A execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;