About the Execution of LoLa+red for ShieldRVt-PT-003B
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
1127.691 | 90180.00 | 94832.00 | 97.60 | TFFTTTFF?FFFFTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2023-input.r423-tajo-167905976400218.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ShieldRVt-PT-003B, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-tajo-167905976400218
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 6.5K Feb 25 22:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 22:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 22:49 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K Feb 25 22:49 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 17:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 17:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 22:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 120K Feb 25 22:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.0K Feb 25 22:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 70K Feb 25 22:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 36K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-00
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-01
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-02
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-03
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-04
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-05
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-06
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-07
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-08
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-09
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-10
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-11
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-12
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-13
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-14
FORMULA_NAME ShieldRVt-PT-003B-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679244384891
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ShieldRVt-PT-003B
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 16:46:26] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 16:46:26] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 16:46:26] [INFO ] Load time of PNML (sax parser for PT used): 37 ms
[2023-03-19 16:46:26] [INFO ] Transformed 153 places.
[2023-03-19 16:46:26] [INFO ] Transformed 153 transitions.
[2023-03-19 16:46:26] [INFO ] Found NUPN structural information;
[2023-03-19 16:46:26] [INFO ] Parsed PT model containing 153 places and 153 transitions and 360 arcs in 109 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 96 out of 153 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 153/153 places, 153/153 transitions.
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 7 place count 146 transition count 146
Iterating global reduction 0 with 7 rules applied. Total rules applied 14 place count 146 transition count 146
Applied a total of 14 rules in 17 ms. Remains 146 /153 variables (removed 7) and now considering 146/153 (removed 7) transitions.
// Phase 1: matrix 146 rows 146 cols
[2023-03-19 16:46:26] [INFO ] Computed 13 place invariants in 8 ms
[2023-03-19 16:46:26] [INFO ] Implicit Places using invariants in 171 ms returned []
[2023-03-19 16:46:26] [INFO ] Invariant cache hit.
[2023-03-19 16:46:27] [INFO ] Implicit Places using invariants and state equation in 94 ms returned []
Implicit Place search using SMT with State Equation took 287 ms to find 0 implicit places.
[2023-03-19 16:46:27] [INFO ] Invariant cache hit.
[2023-03-19 16:46:27] [INFO ] Dead Transitions using invariants and state equation in 84 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 146/153 places, 146/153 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 389 ms. Remains : 146/153 places, 146/153 transitions.
Support contains 96 out of 146 places after structural reductions.
[2023-03-19 16:46:27] [INFO ] Flatten gal took : 31 ms
[2023-03-19 16:46:27] [INFO ] Flatten gal took : 12 ms
[2023-03-19 16:46:27] [INFO ] Input system was already deterministic with 146 transitions.
Support contains 94 out of 146 places (down from 96) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 448 ms. (steps per millisecond=22 ) properties (out of 89) seen :82
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
[2023-03-19 16:46:28] [INFO ] Invariant cache hit.
[2023-03-19 16:46:28] [INFO ] [Real]Absence check using 13 positive place invariants in 3 ms returned sat
[2023-03-19 16:46:28] [INFO ] After 77ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:4
[2023-03-19 16:46:28] [INFO ] [Nat]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-19 16:46:28] [INFO ] After 42ms SMT Verify possible using state equation in natural domain returned unsat :4 sat :1
[2023-03-19 16:46:28] [INFO ] Deduced a trap composed of 20 places in 46 ms of which 6 ms to minimize.
[2023-03-19 16:46:28] [INFO ] Deduced a trap composed of 25 places in 56 ms of which 12 ms to minimize.
[2023-03-19 16:46:28] [INFO ] Deduced a trap composed of 22 places in 29 ms of which 0 ms to minimize.
[2023-03-19 16:46:28] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 162 ms
[2023-03-19 16:46:28] [INFO ] After 210ms SMT Verify possible using trap constraints in natural domain returned unsat :4 sat :1
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-19 16:46:28] [INFO ] After 281ms SMT Verify possible using all constraints in natural domain returned unsat :4 sat :1
Fused 5 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 7 ms.
Support contains 2 out of 146 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 146/146 places, 146/146 transitions.
Drop transitions removed 40 transitions
Trivial Post-agglo rules discarded 40 transitions
Performed 40 trivial Post agglomeration. Transition count delta: 40
Iterating post reduction 0 with 40 rules applied. Total rules applied 40 place count 146 transition count 106
Reduce places removed 40 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 43 rules applied. Total rules applied 83 place count 106 transition count 103
Reduce places removed 2 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 3 rules applied. Total rules applied 86 place count 104 transition count 102
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 87 place count 103 transition count 102
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 13 Pre rules applied. Total rules applied 87 place count 103 transition count 89
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 4 with 26 rules applied. Total rules applied 113 place count 90 transition count 89
Discarding 17 places :
Symmetric choice reduction at 4 with 17 rule applications. Total rules 130 place count 73 transition count 72
Iterating global reduction 4 with 17 rules applied. Total rules applied 147 place count 73 transition count 72
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 9 Pre rules applied. Total rules applied 147 place count 73 transition count 63
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 4 with 18 rules applied. Total rules applied 165 place count 64 transition count 63
Performed 27 Post agglomeration using F-continuation condition.Transition count delta: 27
Deduced a syphon composed of 27 places in 0 ms
Reduce places removed 27 places and 0 transitions.
Iterating global reduction 4 with 54 rules applied. Total rules applied 219 place count 37 transition count 36
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: -6
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 4 with 16 rules applied. Total rules applied 235 place count 29 transition count 42
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 236 place count 29 transition count 41
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 5 with 1 rules applied. Total rules applied 237 place count 28 transition count 40
Applied a total of 237 rules in 29 ms. Remains 28 /146 variables (removed 118) and now considering 40/146 (removed 106) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 29 ms. Remains : 28/146 places, 40/146 transitions.
Incomplete random walk after 10000 steps, including 17 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=1250 ) properties (out of 1) seen :0
Probably explored full state space saw : 5890 states, properties seen :0
Probabilistic random walk after 44740 steps, saw 5890 distinct states, run finished after 47 ms. (steps per millisecond=951 ) properties seen :0
Explored full state space saw : 5890 states, properties seen :0
Exhaustive walk after 44740 steps, saw 5890 distinct states, run finished after 36 ms. (steps per millisecond=1242 ) properties seen :0
Successfully simplified 5 atomic propositions for a total of 16 simplifications.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 9 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 8 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 146 transitions.
Support contains 84 out of 146 places (down from 88) after GAL structural reductions.
Computed a total of 43 stabilizing places and 43 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 38 transitions
Trivial Post-agglo rules discarded 38 transitions
Performed 38 trivial Post agglomeration. Transition count delta: 38
Iterating post reduction 0 with 38 rules applied. Total rules applied 38 place count 145 transition count 107
Reduce places removed 38 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 40 rules applied. Total rules applied 78 place count 107 transition count 105
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 79 place count 106 transition count 105
Performed 15 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 15 Pre rules applied. Total rules applied 79 place count 106 transition count 90
Deduced a syphon composed of 15 places in 0 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 3 with 30 rules applied. Total rules applied 109 place count 91 transition count 90
Discarding 19 places :
Symmetric choice reduction at 3 with 19 rule applications. Total rules 128 place count 72 transition count 71
Iterating global reduction 3 with 19 rules applied. Total rules applied 147 place count 72 transition count 71
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 9 Pre rules applied. Total rules applied 147 place count 72 transition count 62
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 3 with 18 rules applied. Total rules applied 165 place count 63 transition count 62
Performed 22 Post agglomeration using F-continuation condition.Transition count delta: 22
Deduced a syphon composed of 22 places in 0 ms
Reduce places removed 22 places and 0 transitions.
Iterating global reduction 3 with 44 rules applied. Total rules applied 209 place count 41 transition count 40
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 211 place count 39 transition count 38
Applied a total of 211 rules in 19 ms. Remains 39 /146 variables (removed 107) and now considering 38/146 (removed 108) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 39/146 places, 38/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 38 transitions.
Finished random walk after 9 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=9 )
FORMULA ShieldRVt-PT-003B-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 32 transitions
Trivial Post-agglo rules discarded 32 transitions
Performed 32 trivial Post agglomeration. Transition count delta: 32
Iterating post reduction 0 with 32 rules applied. Total rules applied 32 place count 145 transition count 113
Reduce places removed 32 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 34 rules applied. Total rules applied 66 place count 113 transition count 111
Reduce places removed 1 places and 0 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 2 with 4 rules applied. Total rules applied 70 place count 112 transition count 108
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 73 place count 109 transition count 108
Performed 15 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 15 Pre rules applied. Total rules applied 73 place count 109 transition count 93
Deduced a syphon composed of 15 places in 0 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 4 with 30 rules applied. Total rules applied 103 place count 94 transition count 93
Discarding 16 places :
Symmetric choice reduction at 4 with 16 rule applications. Total rules 119 place count 78 transition count 77
Iterating global reduction 4 with 16 rules applied. Total rules applied 135 place count 78 transition count 77
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 7 Pre rules applied. Total rules applied 135 place count 78 transition count 70
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 4 with 14 rules applied. Total rules applied 149 place count 71 transition count 70
Performed 23 Post agglomeration using F-continuation condition.Transition count delta: 23
Deduced a syphon composed of 23 places in 0 ms
Reduce places removed 23 places and 0 transitions.
Iterating global reduction 4 with 46 rules applied. Total rules applied 195 place count 48 transition count 47
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 197 place count 46 transition count 45
Applied a total of 197 rules in 20 ms. Remains 46 /146 variables (removed 100) and now considering 45/146 (removed 101) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 21 ms. Remains : 46/146 places, 45/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 122 transition count 122
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 122 transition count 122
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 49 place count 121 transition count 121
Iterating global reduction 0 with 1 rules applied. Total rules applied 50 place count 121 transition count 121
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 51 place count 120 transition count 120
Iterating global reduction 0 with 1 rules applied. Total rules applied 52 place count 120 transition count 120
Applied a total of 52 rules in 15 ms. Remains 120 /146 variables (removed 26) and now considering 120/146 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 120/146 places, 120/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 120 transitions.
Starting structural reductions in LTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Discarding 18 places :
Symmetric choice reduction at 0 with 18 rule applications. Total rules 18 place count 128 transition count 128
Iterating global reduction 0 with 18 rules applied. Total rules applied 36 place count 128 transition count 128
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 37 place count 127 transition count 127
Iterating global reduction 0 with 1 rules applied. Total rules applied 38 place count 127 transition count 127
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 39 place count 126 transition count 126
Iterating global reduction 0 with 1 rules applied. Total rules applied 40 place count 126 transition count 126
Applied a total of 40 rules in 8 ms. Remains 126 /146 variables (removed 20) and now considering 126/146 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 126/146 places, 126/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 40 transitions
Trivial Post-agglo rules discarded 40 transitions
Performed 40 trivial Post agglomeration. Transition count delta: 40
Iterating post reduction 0 with 40 rules applied. Total rules applied 40 place count 145 transition count 105
Reduce places removed 40 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 43 rules applied. Total rules applied 83 place count 105 transition count 102
Reduce places removed 2 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 3 rules applied. Total rules applied 86 place count 103 transition count 101
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 87 place count 102 transition count 101
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 13 Pre rules applied. Total rules applied 87 place count 102 transition count 88
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 4 with 26 rules applied. Total rules applied 113 place count 89 transition count 88
Discarding 17 places :
Symmetric choice reduction at 4 with 17 rule applications. Total rules 130 place count 72 transition count 71
Iterating global reduction 4 with 17 rules applied. Total rules applied 147 place count 72 transition count 71
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 10 Pre rules applied. Total rules applied 147 place count 72 transition count 61
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 4 with 20 rules applied. Total rules applied 167 place count 62 transition count 61
Performed 22 Post agglomeration using F-continuation condition.Transition count delta: 22
Deduced a syphon composed of 22 places in 0 ms
Reduce places removed 22 places and 0 transitions.
Iterating global reduction 4 with 44 rules applied. Total rules applied 211 place count 40 transition count 39
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 213 place count 38 transition count 37
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 214 place count 37 transition count 37
Applied a total of 214 rules in 17 ms. Remains 37 /146 variables (removed 109) and now considering 37/146 (removed 109) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 37/146 places, 37/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 1 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 1 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 37 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 40 transitions
Trivial Post-agglo rules discarded 40 transitions
Performed 40 trivial Post agglomeration. Transition count delta: 40
Iterating post reduction 0 with 40 rules applied. Total rules applied 40 place count 145 transition count 105
Reduce places removed 40 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 43 rules applied. Total rules applied 83 place count 105 transition count 102
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 85 place count 103 transition count 102
Performed 12 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 12 Pre rules applied. Total rules applied 85 place count 103 transition count 90
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 3 with 24 rules applied. Total rules applied 109 place count 91 transition count 90
Discarding 18 places :
Symmetric choice reduction at 3 with 18 rule applications. Total rules 127 place count 73 transition count 72
Iterating global reduction 3 with 18 rules applied. Total rules applied 145 place count 73 transition count 72
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 10 Pre rules applied. Total rules applied 145 place count 73 transition count 62
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 165 place count 63 transition count 62
Performed 23 Post agglomeration using F-continuation condition.Transition count delta: 23
Deduced a syphon composed of 23 places in 0 ms
Reduce places removed 23 places and 0 transitions.
Iterating global reduction 3 with 46 rules applied. Total rules applied 211 place count 40 transition count 39
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 213 place count 38 transition count 37
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 214 place count 37 transition count 37
Applied a total of 214 rules in 15 ms. Remains 37 /146 variables (removed 109) and now considering 37/146 (removed 109) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 37/146 places, 37/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 37 transitions.
Starting structural reductions in LTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 123 transition count 123
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 123 transition count 123
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 47 place count 122 transition count 122
Iterating global reduction 0 with 1 rules applied. Total rules applied 48 place count 122 transition count 122
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 49 place count 121 transition count 121
Iterating global reduction 0 with 1 rules applied. Total rules applied 50 place count 121 transition count 121
Applied a total of 50 rules in 6 ms. Remains 121 /146 variables (removed 25) and now considering 121/146 (removed 25) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 121/146 places, 121/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 121 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 39 transitions
Trivial Post-agglo rules discarded 39 transitions
Performed 39 trivial Post agglomeration. Transition count delta: 39
Iterating post reduction 0 with 39 rules applied. Total rules applied 39 place count 145 transition count 106
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 42 rules applied. Total rules applied 81 place count 106 transition count 103
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 83 place count 104 transition count 103
Performed 14 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 14 Pre rules applied. Total rules applied 83 place count 104 transition count 89
Deduced a syphon composed of 14 places in 0 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 3 with 28 rules applied. Total rules applied 111 place count 90 transition count 89
Discarding 17 places :
Symmetric choice reduction at 3 with 17 rule applications. Total rules 128 place count 73 transition count 72
Iterating global reduction 3 with 17 rules applied. Total rules applied 145 place count 73 transition count 72
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 10 Pre rules applied. Total rules applied 145 place count 73 transition count 62
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 165 place count 63 transition count 62
Performed 23 Post agglomeration using F-continuation condition.Transition count delta: 23
Deduced a syphon composed of 23 places in 0 ms
Reduce places removed 23 places and 0 transitions.
Iterating global reduction 3 with 46 rules applied. Total rules applied 211 place count 40 transition count 39
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 213 place count 38 transition count 37
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 214 place count 37 transition count 37
Applied a total of 214 rules in 15 ms. Remains 37 /146 variables (removed 109) and now considering 37/146 (removed 109) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 37/146 places, 37/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 1 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 37 transitions.
Starting structural reductions in LTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 132 transition count 132
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 132 transition count 132
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 29 place count 131 transition count 131
Iterating global reduction 0 with 1 rules applied. Total rules applied 30 place count 131 transition count 131
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 31 place count 130 transition count 130
Iterating global reduction 0 with 1 rules applied. Total rules applied 32 place count 130 transition count 130
Applied a total of 32 rules in 7 ms. Remains 130 /146 variables (removed 16) and now considering 130/146 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 130/146 places, 130/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 5 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in LTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 120 transition count 120
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 120 transition count 120
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 53 place count 119 transition count 119
Iterating global reduction 0 with 1 rules applied. Total rules applied 54 place count 119 transition count 119
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 55 place count 118 transition count 118
Iterating global reduction 0 with 1 rules applied. Total rules applied 56 place count 118 transition count 118
Applied a total of 56 rules in 6 ms. Remains 118 /146 variables (removed 28) and now considering 118/146 (removed 28) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 118/146 places, 118/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 118 transitions.
Starting structural reductions in LTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 123 transition count 123
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 123 transition count 123
Applied a total of 46 rules in 3 ms. Remains 123 /146 variables (removed 23) and now considering 123/146 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 123/146 places, 123/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 3 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 3 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 123 transitions.
Starting structural reductions in LTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 122 transition count 122
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 122 transition count 122
Applied a total of 48 rules in 3 ms. Remains 122 /146 variables (removed 24) and now considering 122/146 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 122/146 places, 122/146 transitions.
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:28] [INFO ] Input system was already deterministic with 122 transitions.
Starting structural reductions in LTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 129 transition count 129
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 129 transition count 129
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 35 place count 128 transition count 128
Iterating global reduction 0 with 1 rules applied. Total rules applied 36 place count 128 transition count 128
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 37 place count 127 transition count 127
Iterating global reduction 0 with 1 rules applied. Total rules applied 38 place count 127 transition count 127
Applied a total of 38 rules in 6 ms. Remains 127 /146 variables (removed 19) and now considering 127/146 (removed 19) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 127/146 places, 127/146 transitions.
[2023-03-19 16:46:29] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:29] [INFO ] Flatten gal took : 3 ms
[2023-03-19 16:46:29] [INFO ] Input system was already deterministic with 127 transitions.
Starting structural reductions in LTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 120 transition count 120
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 120 transition count 120
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 53 place count 119 transition count 119
Iterating global reduction 0 with 1 rules applied. Total rules applied 54 place count 119 transition count 119
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 55 place count 118 transition count 118
Iterating global reduction 0 with 1 rules applied. Total rules applied 56 place count 118 transition count 118
Applied a total of 56 rules in 6 ms. Remains 118 /146 variables (removed 28) and now considering 118/146 (removed 28) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 118/146 places, 118/146 transitions.
[2023-03-19 16:46:29] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:29] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:29] [INFO ] Input system was already deterministic with 118 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 36 transitions
Trivial Post-agglo rules discarded 36 transitions
Performed 36 trivial Post agglomeration. Transition count delta: 36
Iterating post reduction 0 with 36 rules applied. Total rules applied 36 place count 145 transition count 109
Reduce places removed 36 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 39 rules applied. Total rules applied 75 place count 109 transition count 106
Reduce places removed 2 places and 0 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Iterating post reduction 2 with 6 rules applied. Total rules applied 81 place count 107 transition count 102
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 85 place count 103 transition count 102
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 13 Pre rules applied. Total rules applied 85 place count 103 transition count 89
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 4 with 26 rules applied. Total rules applied 111 place count 90 transition count 89
Discarding 16 places :
Symmetric choice reduction at 4 with 16 rule applications. Total rules 127 place count 74 transition count 73
Iterating global reduction 4 with 16 rules applied. Total rules applied 143 place count 74 transition count 73
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 8 Pre rules applied. Total rules applied 143 place count 74 transition count 65
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 4 with 16 rules applied. Total rules applied 159 place count 66 transition count 65
Performed 21 Post agglomeration using F-continuation condition.Transition count delta: 21
Deduced a syphon composed of 21 places in 0 ms
Reduce places removed 21 places and 0 transitions.
Iterating global reduction 4 with 42 rules applied. Total rules applied 201 place count 45 transition count 44
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 203 place count 43 transition count 42
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 204 place count 42 transition count 42
Applied a total of 204 rules in 13 ms. Remains 42 /146 variables (removed 104) and now considering 42/146 (removed 104) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 42/146 places, 42/146 transitions.
[2023-03-19 16:46:29] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:46:29] [INFO ] Flatten gal took : 1 ms
[2023-03-19 16:46:29] [INFO ] Input system was already deterministic with 42 transitions.
Starting structural reductions in LTL mode, iteration 0 : 146/146 places, 146/146 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 122 transition count 122
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 122 transition count 122
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 49 place count 121 transition count 121
Iterating global reduction 0 with 1 rules applied. Total rules applied 50 place count 121 transition count 121
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 51 place count 120 transition count 120
Iterating global reduction 0 with 1 rules applied. Total rules applied 52 place count 120 transition count 120
Applied a total of 52 rules in 6 ms. Remains 120 /146 variables (removed 26) and now considering 120/146 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 120/146 places, 120/146 transitions.
[2023-03-19 16:46:29] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:46:29] [INFO ] Flatten gal took : 3 ms
[2023-03-19 16:46:29] [INFO ] Input system was already deterministic with 120 transitions.
[2023-03-19 16:46:29] [INFO ] Flatten gal took : 5 ms
[2023-03-19 16:46:29] [INFO ] Flatten gal took : 5 ms
[2023-03-19 16:46:29] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 16:46:29] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 146 places, 146 transitions and 346 arcs took 0 ms.
Total runtime 2545 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ShieldRVt-PT-003B
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA ShieldRVt-PT-003B-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-003B-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679244475071
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 4 (type EXCL) for 3 ShieldRVt-PT-003B-CTLFireability-02
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 4 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-02
lola: result : false
lola: markings : 91
lola: fired transitions : 240
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 ShieldRVt-PT-003B-CTLFireability-08
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:730
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/240 3/32 ShieldRVt-PT-003B-CTLFireability-08 547708 m, 109541 m/sec, 4238321 t fired, .
Time elapsed: 5 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/240 5/32 ShieldRVt-PT-003B-CTLFireability-08 1047011 m, 99860 m/sec, 8499777 t fired, .
Time elapsed: 10 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/240 8/32 ShieldRVt-PT-003B-CTLFireability-08 1732753 m, 137148 m/sec, 12894726 t fired, .
Time elapsed: 15 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/240 10/32 ShieldRVt-PT-003B-CTLFireability-08 2213839 m, 96217 m/sec, 17491505 t fired, .
Time elapsed: 20 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 25/240 13/32 ShieldRVt-PT-003B-CTLFireability-08 2705922 m, 98416 m/sec, 21449408 t fired, .
Time elapsed: 25 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 30/240 14/32 ShieldRVt-PT-003B-CTLFireability-08 3095664 m, 77948 m/sec, 25064219 t fired, .
Time elapsed: 30 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 35/240 16/32 ShieldRVt-PT-003B-CTLFireability-08 3512811 m, 83429 m/sec, 28655965 t fired, .
Time elapsed: 35 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 40/240 18/32 ShieldRVt-PT-003B-CTLFireability-08 3974649 m, 92367 m/sec, 32789864 t fired, .
Time elapsed: 40 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 45/240 20/32 ShieldRVt-PT-003B-CTLFireability-08 4471754 m, 99421 m/sec, 37079578 t fired, .
Time elapsed: 45 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 50/240 23/32 ShieldRVt-PT-003B-CTLFireability-08 5050859 m, 115821 m/sec, 41463221 t fired, .
Time elapsed: 50 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 55/240 24/32 ShieldRVt-PT-003B-CTLFireability-08 5401981 m, 70224 m/sec, 45134073 t fired, .
Time elapsed: 55 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 60/240 27/32 ShieldRVt-PT-003B-CTLFireability-08 5877773 m, 95158 m/sec, 49261231 t fired, .
Time elapsed: 60 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 65/240 29/32 ShieldRVt-PT-003B-CTLFireability-08 6333979 m, 91241 m/sec, 53272052 t fired, .
Time elapsed: 65 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 70/240 30/32 ShieldRVt-PT-003B-CTLFireability-08 6722925 m, 77789 m/sec, 57483982 t fired, .
Time elapsed: 70 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 75/240 32/32 ShieldRVt-PT-003B-CTLFireability-08 7105798 m, 76574 m/sec, 61142663 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 22 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-04: EFEG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-003B-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ShieldRVt-PT-003B-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 47 (type EXCL) for 46 ShieldRVt-PT-003B-CTLFireability-15
lola: time limit : 251 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-15
lola: result : false
lola: markings : 71
lola: fired transitions : 72
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 ShieldRVt-PT-003B-CTLFireability-13
lola: time limit : 270 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-13
lola: result : true
lola: markings : 56
lola: fired transitions : 56
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 ShieldRVt-PT-003B-CTLFireability-12
lola: time limit : 293 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-12
lola: result : false
lola: markings : 63
lola: fired transitions : 129
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 ShieldRVt-PT-003B-CTLFireability-11
lola: time limit : 320 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-11
lola: result : false
lola: markings : 874
lola: fired transitions : 988
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 27 ShieldRVt-PT-003B-CTLFireability-10
lola: time limit : 352 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-10
lola: result : false
lola: markings : 55
lola: fired transitions : 55
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 ShieldRVt-PT-003B-CTLFireability-09
lola: time limit : 391 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-09
lola: result : false
lola: markings : 43
lola: fired transitions : 43
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 ShieldRVt-PT-003B-CTLFireability-06
lola: time limit : 440 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-06
lola: result : false
lola: markings : 57
lola: fired transitions : 60
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 ShieldRVt-PT-003B-CTLFireability-03
lola: time limit : 502 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-03
lola: result : true
lola: markings : 57
lola: fired transitions : 119
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 27 ShieldRVt-PT-003B-CTLFireability-10
lola: time limit : 586 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-10
lola: result : false
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 12 ShieldRVt-PT-003B-CTLFireability-05
lola: time limit : 704 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-05
lola: result : false
lola: markings : 5091
lola: fired transitions : 8205
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 ShieldRVt-PT-003B-CTLFireability-04
lola: time limit : 880 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-04
lola: result : true
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 ShieldRVt-PT-003B-CTLFireability-07
lola: time limit : 1173 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-07
lola: result : false
lola: markings : 7
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 ShieldRVt-PT-003B-CTLFireability-14
lola: time limit : 1760 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-03: CTL true CTL model checker
ShieldRVt-PT-003B-CTLFireability-04: EFEG true state space /EFEG
ShieldRVt-PT-003B-CTLFireability-05: EFAG true tscc_search
ShieldRVt-PT-003B-CTLFireability-06: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-07: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-09: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-10: DISJ false DISJ
ShieldRVt-PT-003B-CTLFireability-11: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-12: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-13: CTL true CTL model checker
ShieldRVt-PT-003B-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVt-PT-003B-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldRVt-PT-003B-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ShieldRVt-PT-003B-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 5/1760 4/32 ShieldRVt-PT-003B-CTLFireability-14 794628 m, 158925 m/sec, 4759456 t fired, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: FINISHED task # 44 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-14
lola: result : true
lola: markings : 802108
lola: fired transitions : 5053641
lola: time used : 5.000000
lola: memory pages used : 4
lola: LAUNCH task # 1 (type EXCL) for 0 ShieldRVt-PT-003B-CTLFireability-01
lola: time limit : 3515 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for ShieldRVt-PT-003B-CTLFireability-01
lola: result : false
lola: markings : 1818
lola: fired transitions : 5399
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVt-PT-003B-CTLFireability-01: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-02: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-03: CTL true CTL model checker
ShieldRVt-PT-003B-CTLFireability-04: EFEG true state space /EFEG
ShieldRVt-PT-003B-CTLFireability-05: EFAG true tscc_search
ShieldRVt-PT-003B-CTLFireability-06: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-07: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-08: CTL unknown AGGR
ShieldRVt-PT-003B-CTLFireability-09: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-10: DISJ false DISJ
ShieldRVt-PT-003B-CTLFireability-11: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-12: CTL false CTL model checker
ShieldRVt-PT-003B-CTLFireability-13: CTL true CTL model checker
ShieldRVt-PT-003B-CTLFireability-14: CTL true CTL model checker
ShieldRVt-PT-003B-CTLFireability-15: CTL false CTL model checker
Time elapsed: 85 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldRVt-PT-003B"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ShieldRVt-PT-003B, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-tajo-167905976400218"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ShieldRVt-PT-003B.tgz
mv ShieldRVt-PT-003B execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;