Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2023-input.r423-tajo-167905976200026.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ShieldRVs-PT-002B, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-tajo-167905976200026
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 440K
-rw-r--r-- 1 mcc users 6.1K Feb 26 18:25 CTLCardinality.txt
-rw-r--r-- 1 mcc users 63K Feb 26 18:25 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 26 18:24 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 26 18:24 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 17:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.8K Feb 26 18:26 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 104K Feb 26 18:26 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.8K Feb 26 18:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 26 18:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 24K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-00
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-01
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-02
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-03
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-04
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-05
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-06
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-07
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-08
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-09
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-10
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-11
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-12
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-13
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-14
FORMULA_NAME ShieldRVs-PT-002B-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679242082561

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ShieldRVs-PT-002B
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 16:08:04] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 16:08:04] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 16:08:04] [INFO ] Load time of PNML (sax parser for PT used): 33 ms
[2023-03-19 16:08:04] [INFO ] Transformed 83 places.
[2023-03-19 16:08:04] [INFO ] Transformed 93 transitions.
[2023-03-19 16:08:04] [INFO ] Found NUPN structural information;
[2023-03-19 16:08:04] [INFO ] Parsed PT model containing 83 places and 93 transitions and 288 arcs in 97 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 64 out of 83 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 93/93 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 82 transition count 92
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 82 transition count 92
Applied a total of 2 rules in 16 ms. Remains 82 /83 variables (removed 1) and now considering 92/93 (removed 1) transitions.
// Phase 1: matrix 92 rows 82 cols
[2023-03-19 16:08:04] [INFO ] Computed 9 place invariants in 8 ms
[2023-03-19 16:08:04] [INFO ] Implicit Places using invariants in 148 ms returned []
[2023-03-19 16:08:04] [INFO ] Invariant cache hit.
[2023-03-19 16:08:04] [INFO ] Implicit Places using invariants and state equation in 66 ms returned []
Implicit Place search using SMT with State Equation took 239 ms to find 0 implicit places.
[2023-03-19 16:08:04] [INFO ] Invariant cache hit.
[2023-03-19 16:08:04] [INFO ] Dead Transitions using invariants and state equation in 67 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 82/83 places, 92/93 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 324 ms. Remains : 82/83 places, 92/93 transitions.
Support contains 64 out of 82 places after structural reductions.
[2023-03-19 16:08:04] [INFO ] Flatten gal took : 27 ms
[2023-03-19 16:08:04] [INFO ] Flatten gal took : 10 ms
[2023-03-19 16:08:04] [INFO ] Input system was already deterministic with 92 transitions.
Incomplete random walk after 10000 steps, including 90 resets, run finished after 281 ms. (steps per millisecond=35 ) properties (out of 74) seen :71
Incomplete Best-First random walk after 10000 steps, including 24 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10000 steps, including 21 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
[2023-03-19 16:08:05] [INFO ] Invariant cache hit.
[2023-03-19 16:08:05] [INFO ] [Real]Absence check using 9 positive place invariants in 3 ms returned sat
[2023-03-19 16:08:05] [INFO ] After 100ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-19 16:08:05] [INFO ] [Nat]Absence check using 9 positive place invariants in 2 ms returned sat
[2023-03-19 16:08:05] [INFO ] After 37ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-19 16:08:05] [INFO ] Deduced a trap composed of 10 places in 45 ms of which 4 ms to minimize.
[2023-03-19 16:08:05] [INFO ] Deduced a trap composed of 25 places in 40 ms of which 0 ms to minimize.
[2023-03-19 16:08:05] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 104 ms
[2023-03-19 16:08:05] [INFO ] After 167ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 14 ms.
[2023-03-19 16:08:05] [INFO ] After 236ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Parikh walk visited 0 properties in 10 ms.
Support contains 7 out of 82 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 82/82 places, 92/92 transitions.
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 0 with 6 rules applied. Total rules applied 6 place count 82 transition count 86
Reduce places removed 6 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 7 rules applied. Total rules applied 13 place count 76 transition count 85
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 14 place count 75 transition count 85
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 9 Pre rules applied. Total rules applied 14 place count 75 transition count 76
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 3 with 18 rules applied. Total rules applied 32 place count 66 transition count 76
Discarding 10 places :
Symmetric choice reduction at 3 with 10 rule applications. Total rules 42 place count 56 transition count 66
Iterating global reduction 3 with 10 rules applied. Total rules applied 52 place count 56 transition count 66
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 4 Pre rules applied. Total rules applied 52 place count 56 transition count 62
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 60 place count 52 transition count 62
Performed 13 Post agglomeration using F-continuation condition.Transition count delta: 13
Deduced a syphon composed of 13 places in 1 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 3 with 26 rules applied. Total rules applied 86 place count 39 transition count 49
Partial Free-agglomeration rule applied 5 times.
Drop transitions removed 5 transitions
Iterating global reduction 3 with 5 rules applied. Total rules applied 91 place count 39 transition count 49
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 3 with 1 rules applied. Total rules applied 92 place count 38 transition count 48
Applied a total of 92 rules in 35 ms. Remains 38 /82 variables (removed 44) and now considering 48/92 (removed 44) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 35 ms. Remains : 38/82 places, 48/92 transitions.
Incomplete random walk after 10000 steps, including 186 resets, run finished after 175 ms. (steps per millisecond=57 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 72 resets, run finished after 59 ms. (steps per millisecond=169 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 51 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 48 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 3) seen :0
Probably explored full state space saw : 26953 states, properties seen :0
Probabilistic random walk after 141829 steps, saw 26953 distinct states, run finished after 483 ms. (steps per millisecond=293 ) properties seen :0
Explored full state space saw : 26953 states, properties seen :0
Exhaustive walk after 141829 steps, saw 26953 distinct states, run finished after 372 ms. (steps per millisecond=381 ) properties seen :0
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA ShieldRVs-PT-002B-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 7 ms
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 7 ms
[2023-03-19 16:08:06] [INFO ] Input system was already deterministic with 92 transitions.
Computed a total of 24 stabilizing places and 24 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 70 transition count 80
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 70 transition count 80
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 25 place count 69 transition count 79
Iterating global reduction 0 with 1 rules applied. Total rules applied 26 place count 69 transition count 79
Applied a total of 26 rules in 4 ms. Remains 69 /82 variables (removed 13) and now considering 79/92 (removed 13) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 69/82 places, 79/92 transitions.
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 5 ms
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:06] [INFO ] Input system was already deterministic with 79 transitions.
Starting structural reductions in LTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 69 transition count 79
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 69 transition count 79
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 27 place count 68 transition count 78
Iterating global reduction 0 with 1 rules applied. Total rules applied 28 place count 68 transition count 78
Applied a total of 28 rules in 5 ms. Remains 68 /82 variables (removed 14) and now considering 78/92 (removed 14) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 68/82 places, 78/92 transitions.
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 5 ms
[2023-03-19 16:08:06] [INFO ] Input system was already deterministic with 78 transitions.
Starting structural reductions in LTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 69 transition count 79
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 69 transition count 79
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 27 place count 68 transition count 78
Iterating global reduction 0 with 1 rules applied. Total rules applied 28 place count 68 transition count 78
Applied a total of 28 rules in 4 ms. Remains 68 /82 variables (removed 14) and now considering 78/92 (removed 14) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 68/82 places, 78/92 transitions.
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 5 ms
[2023-03-19 16:08:06] [INFO ] Input system was already deterministic with 78 transitions.
Starting structural reductions in LTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 70 transition count 80
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 70 transition count 80
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 25 place count 69 transition count 79
Iterating global reduction 0 with 1 rules applied. Total rules applied 26 place count 69 transition count 79
Applied a total of 26 rules in 4 ms. Remains 69 /82 variables (removed 13) and now considering 79/92 (removed 13) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 69/82 places, 79/92 transitions.
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:06] [INFO ] Input system was already deterministic with 79 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 81 transition count 84
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 14 place count 74 transition count 84
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 9 Pre rules applied. Total rules applied 14 place count 74 transition count 75
Deduced a syphon composed of 9 places in 1 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 2 with 18 rules applied. Total rules applied 32 place count 65 transition count 75
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 43 place count 54 transition count 64
Iterating global reduction 2 with 11 rules applied. Total rules applied 54 place count 54 transition count 64
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 4 Pre rules applied. Total rules applied 54 place count 54 transition count 60
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 62 place count 50 transition count 60
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 82 place count 40 transition count 50
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 2 with 1 rules applied. Total rules applied 83 place count 39 transition count 49
Applied a total of 83 rules in 13 ms. Remains 39 /82 variables (removed 43) and now considering 49/92 (removed 43) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 39/82 places, 49/92 transitions.
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:08:06] [INFO ] Input system was already deterministic with 49 transitions.
Starting structural reductions in LTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 70 transition count 80
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 70 transition count 80
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 25 place count 69 transition count 79
Iterating global reduction 0 with 1 rules applied. Total rules applied 26 place count 69 transition count 79
Applied a total of 26 rules in 3 ms. Remains 69 /82 variables (removed 13) and now considering 79/92 (removed 13) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 69/82 places, 79/92 transitions.
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:06] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:06] [INFO ] Input system was already deterministic with 79 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 81 transition count 84
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 14 place count 74 transition count 84
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 11 Pre rules applied. Total rules applied 14 place count 74 transition count 73
Deduced a syphon composed of 11 places in 0 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 2 with 22 rules applied. Total rules applied 36 place count 63 transition count 73
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 49 place count 50 transition count 60
Iterating global reduction 2 with 13 rules applied. Total rules applied 62 place count 50 transition count 60
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 5 Pre rules applied. Total rules applied 62 place count 50 transition count 55
Deduced a syphon composed of 5 places in 1 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 2 with 10 rules applied. Total rules applied 72 place count 45 transition count 55
Performed 12 Post agglomeration using F-continuation condition.Transition count delta: 12
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 2 with 24 rules applied. Total rules applied 96 place count 33 transition count 43
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 98 place count 31 transition count 41
Applied a total of 98 rules in 11 ms. Remains 31 /82 variables (removed 51) and now considering 41/92 (removed 51) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 31/82 places, 41/92 transitions.
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:08:07] [INFO ] Input system was already deterministic with 41 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 81 transition count 83
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 1 with 8 rules applied. Total rules applied 16 place count 73 transition count 83
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 11 Pre rules applied. Total rules applied 16 place count 73 transition count 72
Deduced a syphon composed of 11 places in 0 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 2 with 22 rules applied. Total rules applied 38 place count 62 transition count 72
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 50 place count 50 transition count 60
Iterating global reduction 2 with 12 rules applied. Total rules applied 62 place count 50 transition count 60
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 5 Pre rules applied. Total rules applied 62 place count 50 transition count 55
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 2 with 10 rules applied. Total rules applied 72 place count 45 transition count 55
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 92 place count 35 transition count 45
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 94 place count 33 transition count 43
Applied a total of 94 rules in 10 ms. Remains 33 /82 variables (removed 49) and now considering 43/92 (removed 49) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 33/82 places, 43/92 transitions.
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 3 ms
[2023-03-19 16:08:07] [INFO ] Input system was already deterministic with 43 transitions.
Starting structural reductions in LTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 73 transition count 83
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 73 transition count 83
Applied a total of 18 rules in 1 ms. Remains 73 /82 variables (removed 9) and now considering 83/92 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 73/82 places, 83/92 transitions.
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 5 ms
[2023-03-19 16:08:07] [INFO ] Input system was already deterministic with 83 transitions.
Starting structural reductions in LTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 71 transition count 81
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 71 transition count 81
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 23 place count 70 transition count 80
Iterating global reduction 0 with 1 rules applied. Total rules applied 24 place count 70 transition count 80
Applied a total of 24 rules in 1 ms. Remains 70 /82 variables (removed 12) and now considering 80/92 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 70/82 places, 80/92 transitions.
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:07] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 74 transition count 84
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 74 transition count 84
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 17 place count 73 transition count 83
Iterating global reduction 0 with 1 rules applied. Total rules applied 18 place count 73 transition count 83
Applied a total of 18 rules in 2 ms. Remains 73 /82 variables (removed 9) and now considering 83/92 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 73/82 places, 83/92 transitions.
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:07] [INFO ] Input system was already deterministic with 83 transitions.
Starting structural reductions in LTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 73 transition count 83
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 73 transition count 83
Applied a total of 18 rules in 2 ms. Remains 73 /82 variables (removed 9) and now considering 83/92 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 73/82 places, 83/92 transitions.
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 3 ms
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:07] [INFO ] Input system was already deterministic with 83 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 9 transitions
Trivial Post-agglo rules discarded 9 transitions
Performed 9 trivial Post agglomeration. Transition count delta: 9
Iterating post reduction 0 with 9 rules applied. Total rules applied 9 place count 81 transition count 82
Reduce places removed 9 places and 0 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 18 place count 72 transition count 82
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 6 Pre rules applied. Total rules applied 18 place count 72 transition count 76
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 2 with 12 rules applied. Total rules applied 30 place count 66 transition count 76
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 43 place count 53 transition count 63
Iterating global reduction 2 with 13 rules applied. Total rules applied 56 place count 53 transition count 63
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 56 place count 53 transition count 61
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 60 place count 51 transition count 61
Performed 11 Post agglomeration using F-continuation condition.Transition count delta: 11
Deduced a syphon composed of 11 places in 0 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 2 with 22 rules applied. Total rules applied 82 place count 40 transition count 50
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 84 place count 38 transition count 48
Applied a total of 84 rules in 8 ms. Remains 38 /82 variables (removed 44) and now considering 48/92 (removed 44) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 38/82 places, 48/92 transitions.
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:08:07] [INFO ] Input system was already deterministic with 48 transitions.
Starting structural reductions in LTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 70 transition count 80
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 70 transition count 80
Applied a total of 24 rules in 1 ms. Remains 70 /82 variables (removed 12) and now considering 80/92 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 70/82 places, 80/92 transitions.
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 3 ms
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 3 ms
[2023-03-19 16:08:07] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 82/82 places, 92/92 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 9 transitions
Trivial Post-agglo rules discarded 9 transitions
Performed 9 trivial Post agglomeration. Transition count delta: 9
Iterating post reduction 0 with 9 rules applied. Total rules applied 9 place count 81 transition count 82
Reduce places removed 9 places and 0 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 18 place count 72 transition count 82
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 10 Pre rules applied. Total rules applied 18 place count 72 transition count 72
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 38 place count 62 transition count 72
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 51 place count 49 transition count 59
Iterating global reduction 2 with 13 rules applied. Total rules applied 64 place count 49 transition count 59
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 5 Pre rules applied. Total rules applied 64 place count 49 transition count 54
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 2 with 10 rules applied. Total rules applied 74 place count 44 transition count 54
Performed 12 Post agglomeration using F-continuation condition.Transition count delta: 12
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 2 with 24 rules applied. Total rules applied 98 place count 32 transition count 42
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 100 place count 30 transition count 40
Applied a total of 100 rules in 8 ms. Remains 30 /82 variables (removed 52) and now considering 40/92 (removed 52) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 30/82 places, 40/92 transitions.
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 2 ms
[2023-03-19 16:08:07] [INFO ] Input system was already deterministic with 40 transitions.
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 4 ms
[2023-03-19 16:08:07] [INFO ] Flatten gal took : 5 ms
[2023-03-19 16:08:07] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 16:08:07] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 82 places, 92 transitions and 286 arcs took 1 ms.
Total runtime 3110 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ShieldRVs-PT-002B
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

FORMULA ShieldRVs-PT-002B-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldRVs-PT-002B-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679242181402

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 7 (type EXCL) for 6 ShieldRVs-PT-002B-CTLFireability-02
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: FINISHED task # 7 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-02
lola: result : true
lola: markings : 28
lola: fired transitions : 56
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 25 (type EXCL) for 24 ShieldRVs-PT-002B-CTLFireability-09
lola: time limit : 144 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 25 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-09
lola: result : true
lola: markings : 28
lola: fired transitions : 27
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 ShieldRVs-PT-002B-CTLFireability-01
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-01
lola: result : true
lola: markings : 213
lola: fired transitions : 212
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 53 (type EXCL) for 18 ShieldRVs-PT-002B-CTLFireability-07
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-07
lola: result : false
lola: markings : 298
lola: fired transitions : 555
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 27 ShieldRVs-PT-002B-CTLFireability-10
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 30 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-10
lola: result : false
lola: markings : 73
lola: fired transitions : 110
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 ShieldRVs-PT-002B-CTLFireability-11
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 35 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-11
lola: result : true
lola: markings : 34
lola: fired transitions : 33
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 37 ShieldRVs-PT-002B-CTLFireability-12
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-12
lola: result : false
lola: markings : 112
lola: fired transitions : 243
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 37 ShieldRVs-PT-002B-CTLFireability-12
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVs-PT-002B-CTLFireability-01: EXEF true state space /EXEF
ShieldRVs-PT-002B-CTLFireability-02: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-07: F true state space / EG
ShieldRVs-PT-002B-CTLFireability-09: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-11: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVs-PT-002B-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-10: DISJ 0 1 0 0 3 0 0 0
ShieldRVs-PT-002B-CTLFireability-12: DISJ 0 0 1 0 3 0 0 0
ShieldRVs-PT-002B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-15: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/360 3/32 ShieldRVs-PT-002B-CTLFireability-12 624752 m, 124950 m/sec, 5063952 t fired, .

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42 CTL EXCL 10/360 6/32 ShieldRVs-PT-002B-CTLFireability-12 1213070 m, 117663 m/sec, 10123550 t fired, .

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42 CTL EXCL 15/360 8/32 ShieldRVs-PT-002B-CTLFireability-12 1769621 m, 111310 m/sec, 14950061 t fired, .

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ShieldRVs-PT-002B-CTLFireability-12: DISJ false DISJ
ShieldRVs-PT-002B-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVs-PT-002B-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-15: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 19/708 10/32 ShieldRVs-PT-002B-CTLFireability-00 2136186 m, 98802 m/sec, 17776386 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVs-PT-002B-CTLFireability-01: EXEF true state space /EXEF
ShieldRVs-PT-002B-CTLFireability-02: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-03: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-05: CTL false CTL model checker
ShieldRVs-PT-002B-CTLFireability-07: F true state space / EG
ShieldRVs-PT-002B-CTLFireability-09: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-10: DISJ false DISJ
ShieldRVs-PT-002B-CTLFireability-11: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-12: DISJ false DISJ
ShieldRVs-PT-002B-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVs-PT-002B-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-15: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 24/708 12/32 ShieldRVs-PT-002B-CTLFireability-00 2634982 m, 99759 m/sec, 22163255 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVs-PT-002B-CTLFireability-01: EXEF true state space /EXEF
ShieldRVs-PT-002B-CTLFireability-02: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-03: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-05: CTL false CTL model checker
ShieldRVs-PT-002B-CTLFireability-07: F true state space / EG
ShieldRVs-PT-002B-CTLFireability-09: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-10: DISJ false DISJ
ShieldRVs-PT-002B-CTLFireability-11: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-12: DISJ false DISJ
ShieldRVs-PT-002B-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVs-PT-002B-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-15: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 29/708 14/32 ShieldRVs-PT-002B-CTLFireability-00 3105950 m, 94193 m/sec, 26421564 t fired, .

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ShieldRVs-PT-002B-CTLFireability-01: EXEF true state space /EXEF
ShieldRVs-PT-002B-CTLFireability-02: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-03: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-05: CTL false CTL model checker
ShieldRVs-PT-002B-CTLFireability-07: F true state space / EG
ShieldRVs-PT-002B-CTLFireability-09: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-10: DISJ false DISJ
ShieldRVs-PT-002B-CTLFireability-11: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-12: DISJ false DISJ
ShieldRVs-PT-002B-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldRVs-PT-002B-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ShieldRVs-PT-002B-CTLFireability-15: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 34/708 15/32 ShieldRVs-PT-002B-CTLFireability-00 3552774 m, 89364 m/sec, 30429076 t fired, .

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# running tasks: 1 of 4 Visible: 15
lola: FINISHED task # 1 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-00
lola: result : false
lola: markings : 3927473
lola: fired transitions : 33775802
lola: time used : 38.000000
lola: memory pages used : 17
lola: LAUNCH task # 51 (type EXCL) for 50 ShieldRVs-PT-002B-CTLFireability-15
lola: time limit : 876 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-15
lola: result : true
lola: markings : 63
lola: fired transitions : 62
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 ShieldRVs-PT-002B-CTLFireability-08
lola: time limit : 1168 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-08
lola: result : true
lola: markings : 67
lola: fired transitions : 183
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 ShieldRVs-PT-002B-CTLFireability-04
lola: time limit : 1753 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-04
lola: result : false
lola: markings : 26539
lola: fired transitions : 119413
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 ShieldRVs-PT-002B-CTLFireability-13
lola: time limit : 3506 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for ShieldRVs-PT-002B-CTLFireability-13
lola: result : true
lola: markings : 31
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldRVs-PT-002B-CTLFireability-00: CTL false CTL model checker
ShieldRVs-PT-002B-CTLFireability-01: EXEF true state space /EXEF
ShieldRVs-PT-002B-CTLFireability-02: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-03: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-04: CTL false CTL model checker
ShieldRVs-PT-002B-CTLFireability-05: CTL false CTL model checker
ShieldRVs-PT-002B-CTLFireability-07: F true state space / EG
ShieldRVs-PT-002B-CTLFireability-08: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-09: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-10: DISJ false DISJ
ShieldRVs-PT-002B-CTLFireability-11: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-12: DISJ false DISJ
ShieldRVs-PT-002B-CTLFireability-13: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-14: CTL true CTL model checker
ShieldRVs-PT-002B-CTLFireability-15: EG true state space / EG


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldRVs-PT-002B"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ShieldRVs-PT-002B, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-tajo-167905976200026"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ShieldRVs-PT-002B.tgz
mv ShieldRVs-PT-002B execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;