Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r391-oct2-167903714800034.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ShieldIIPs-PT-003A, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r391-oct2-167903714800034
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 5.6K Feb 25 15:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 57K Feb 25 15:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 15:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 15:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 16:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 15:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 145K Feb 25 15:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 15:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 101K Feb 25 15:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 26K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-00
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-01
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-02
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-03
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-04
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-05
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-06
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-07
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-08
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-09
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-10
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-11
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-12
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-13
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-14
FORMULA_NAME ShieldIIPs-PT-003A-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679265308612

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ShieldIIPs-PT-003A
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 22:35:12] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 22:35:12] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 22:35:12] [INFO ] Load time of PNML (sax parser for PT used): 70 ms
[2023-03-19 22:35:12] [INFO ] Transformed 78 places.
[2023-03-19 22:35:12] [INFO ] Transformed 75 transitions.
[2023-03-19 22:35:12] [INFO ] Found NUPN structural information;
[2023-03-19 22:35:12] [INFO ] Parsed PT model containing 78 places and 75 transitions and 330 arcs in 190 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 13 ms.
Support contains 62 out of 78 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 14 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
// Phase 1: matrix 75 rows 78 cols
[2023-03-19 22:35:12] [INFO ] Computed 28 place invariants in 6 ms
[2023-03-19 22:35:13] [INFO ] Implicit Places using invariants in 566 ms returned []
[2023-03-19 22:35:13] [INFO ] Invariant cache hit.
[2023-03-19 22:35:13] [INFO ] Implicit Places using invariants and state equation in 592 ms returned []
Implicit Place search using SMT with State Equation took 1207 ms to find 0 implicit places.
[2023-03-19 22:35:13] [INFO ] Invariant cache hit.
[2023-03-19 22:35:14] [INFO ] Dead Transitions using invariants and state equation in 754 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1982 ms. Remains : 78/78 places, 75/75 transitions.
Support contains 62 out of 78 places after structural reductions.
[2023-03-19 22:35:14] [INFO ] Flatten gal took : 27 ms
[2023-03-19 22:35:14] [INFO ] Flatten gal took : 10 ms
[2023-03-19 22:35:14] [INFO ] Input system was already deterministic with 75 transitions.
Support contains 61 out of 78 places (down from 62) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 52 resets, run finished after 431 ms. (steps per millisecond=23 ) properties (out of 55) seen :50
Incomplete Best-First random walk after 10000 steps, including 9 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 9 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 14 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 11 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 12 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 5) seen :1
Running SMT prover for 4 properties.
[2023-03-19 22:35:15] [INFO ] Invariant cache hit.
[2023-03-19 22:35:15] [INFO ] [Real]Absence check using 28 positive place invariants in 4 ms returned sat
[2023-03-19 22:35:15] [INFO ] After 61ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :0
Fused 4 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 4 atomic propositions for a total of 16 simplifications.
FORMULA ShieldIIPs-PT-003A-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 13 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 13 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 75 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 1 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 78/78 places, 75/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 2 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 78/78 places, 75/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 6 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 2 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 78/78 places, 75/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Reduce places removed 1 places and 1 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 77 transition count 73
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 75 transition count 73
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 5 place count 74 transition count 72
Applied a total of 5 rules in 14 ms. Remains 74 /78 variables (removed 4) and now considering 72/75 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 74/78 places, 72/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 72 transitions.
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 2 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 78/78 places, 75/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 1 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 78/78 places, 75/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 12 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 1 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 78/78 places, 75/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 78 transition count 74
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 77 transition count 74
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 4 place count 76 transition count 73
Applied a total of 4 rules in 6 ms. Remains 76 /78 variables (removed 2) and now considering 73/75 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 76/78 places, 73/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 73 transitions.
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 2 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 78/78 places, 75/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 5 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 78 transition count 74
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 77 transition count 74
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 4 place count 76 transition count 73
Applied a total of 4 rules in 6 ms. Remains 76 /78 variables (removed 2) and now considering 73/75 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 76/78 places, 73/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 73 transitions.
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 1 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 78/78 places, 75/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 1 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 78/78 places, 75/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Reduce places removed 1 places and 1 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 77 transition count 73
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 75 transition count 73
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 5 place count 74 transition count 72
Applied a total of 5 rules in 6 ms. Remains 74 /78 variables (removed 4) and now considering 72/75 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 74/78 places, 72/75 transitions.
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 3 ms
[2023-03-19 22:35:15] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:15] [INFO ] Input system was already deterministic with 72 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Reduce places removed 1 places and 1 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 77 transition count 73
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 75 transition count 73
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 5 place count 74 transition count 72
Applied a total of 5 rules in 5 ms. Remains 74 /78 variables (removed 4) and now considering 72/75 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 74/78 places, 72/75 transitions.
[2023-03-19 22:35:16] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:16] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:16] [INFO ] Input system was already deterministic with 72 transitions.
Starting structural reductions in LTL mode, iteration 0 : 78/78 places, 75/75 transitions.
Applied a total of 0 rules in 1 ms. Remains 78 /78 variables (removed 0) and now considering 75/75 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 78/78 places, 75/75 transitions.
[2023-03-19 22:35:16] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:16] [INFO ] Flatten gal took : 4 ms
[2023-03-19 22:35:16] [INFO ] Input system was already deterministic with 75 transitions.
[2023-03-19 22:35:16] [INFO ] Flatten gal took : 5 ms
[2023-03-19 22:35:16] [INFO ] Flatten gal took : 5 ms
[2023-03-19 22:35:16] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 22:35:16] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 78 places, 75 transitions and 330 arcs took 1 ms.
Total runtime 3943 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ShieldIIPs-PT-003A
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/378
CTLFireability

FORMULA ShieldIIPs-PT-003A-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldIIPs-PT-003A-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldIIPs-PT-003A-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldIIPs-PT-003A-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldIIPs-PT-003A-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldIIPs-PT-003A-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldIIPs-PT-003A-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldIIPs-PT-003A-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldIIPs-PT-003A-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ShieldIIPs-PT-003A-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679265511791

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/378/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/378/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/378/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: FINISHED task # 22 (type EXCL) for ShieldIIPs-PT-003A-CTLFireability-03
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
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lola: rewrite Frontend/Parser/formula_rewrite.k:815
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 36 (type EXCL) for ShieldIIPs-PT-003A-CTLFireability-05
lola: result : true
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldIIPs-PT-003A-CTLFireability-00: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-03: AGEF false tscc_search
ShieldIIPs-PT-003A-CTLFireability-05: DISJ true CTL model checker

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63 CTL EXCL 5/240 10/32 ShieldIIPs-PT-003A-CTLFireability-15 2294900 m, 458980 m/sec, 6457020 t fired, .

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63 CTL EXCL 10/240 19/32 ShieldIIPs-PT-003A-CTLFireability-15 4355614 m, 412142 m/sec, 12835517 t fired, .

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63 CTL EXCL 15/240 27/32 ShieldIIPs-PT-003A-CTLFireability-15 6278171 m, 384511 m/sec, 19031870 t fired, .

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ShieldIIPs-PT-003A-CTLFireability-00: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-03: AGEF false tscc_search
ShieldIIPs-PT-003A-CTLFireability-04: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-05: DISJ true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-07: CTL true CTL model checker
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19 CTL EXCL 5/397 11/32 ShieldIIPs-PT-003A-CTLFireability-02 2416353 m, 483270 m/sec, 6273675 t fired, .

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19 CTL EXCL 10/397 16/32 ShieldIIPs-PT-003A-CTLFireability-02 3640217 m, 244772 m/sec, 12832061 t fired, .

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19 CTL EXCL 15/397 19/32 ShieldIIPs-PT-003A-CTLFireability-02 4294982 m, 130953 m/sec, 18776783 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldIIPs-PT-003A-CTLFireability-02: CONJ 0 0 0 0 6 0 1 1
ShieldIIPs-PT-003A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldIIPs-PT-003A-CTLFireability-10: EFEG 0 0 0 0 1 0 1 0
ShieldIIPs-PT-003A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
ShieldIIPs-PT-003A-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 65/3485 27/32 ShieldIIPs-PT-003A-CTLFireability-08 6448056 m, 101092 m/sec, 62666961 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldIIPs-PT-003A-CTLFireability-00: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-01: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-03: AGEF false tscc_search
ShieldIIPs-PT-003A-CTLFireability-04: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-05: DISJ true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-07: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-09: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-11: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-12: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-14: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldIIPs-PT-003A-CTLFireability-02: CONJ 0 0 0 0 6 0 1 1
ShieldIIPs-PT-003A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldIIPs-PT-003A-CTLFireability-10: EFEG 0 0 0 0 1 0 1 0
ShieldIIPs-PT-003A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
ShieldIIPs-PT-003A-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 70/3485 30/32 ShieldIIPs-PT-003A-CTLFireability-08 6943218 m, 99032 m/sec, 67407624 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldIIPs-PT-003A-CTLFireability-00: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-01: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-03: AGEF false tscc_search
ShieldIIPs-PT-003A-CTLFireability-04: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-05: DISJ true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-07: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-09: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-11: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-12: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-14: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldIIPs-PT-003A-CTLFireability-02: CONJ 0 0 0 0 6 0 1 1
ShieldIIPs-PT-003A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ShieldIIPs-PT-003A-CTLFireability-10: EFEG 0 0 0 0 1 0 1 0
ShieldIIPs-PT-003A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
ShieldIIPs-PT-003A-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 75/3485 32/32 ShieldIIPs-PT-003A-CTLFireability-08 7431926 m, 97741 m/sec, 72227324 t fired, .

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lola: CANCELED task # 42 (type EXCL) for ShieldIIPs-PT-003A-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldIIPs-PT-003A-CTLFireability-00: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-01: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-03: AGEF false tscc_search
ShieldIIPs-PT-003A-CTLFireability-04: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-05: DISJ true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-07: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-09: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-11: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-12: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-14: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ShieldIIPs-PT-003A-CTLFireability-02: CONJ 0 0 0 0 6 0 1 1
ShieldIIPs-PT-003A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ShieldIIPs-PT-003A-CTLFireability-10: EFEG 0 0 0 0 1 0 1 0
ShieldIIPs-PT-003A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
ShieldIIPs-PT-003A-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldIIPs-PT-003A-CTLFireability-00: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-01: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-02: CONJ unknown CONJ
ShieldIIPs-PT-003A-CTLFireability-03: AGEF false tscc_search
ShieldIIPs-PT-003A-CTLFireability-04: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-05: DISJ true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-07: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-08: CTL unknown AGGR
ShieldIIPs-PT-003A-CTLFireability-09: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-10: EFEG unknown AGGR
ShieldIIPs-PT-003A-CTLFireability-11: CTL false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-12: CTL true CTL model checker
ShieldIIPs-PT-003A-CTLFireability-13: CTL unknown AGGR
ShieldIIPs-PT-003A-CTLFireability-14: AFAG false CTL model checker
ShieldIIPs-PT-003A-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldIIPs-PT-003A"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ShieldIIPs-PT-003A, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r391-oct2-167903714800034"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ShieldIIPs-PT-003A.tgz
mv ShieldIIPs-PT-003A execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;