About the Execution of LoLA for ShieldPPPt-PT-040A
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15409.508 | 209578.00 | 407821.00 | 15.10 | TF?FFF?TF???TFT? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r390-oct2-167903714700658.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ShieldPPPt-PT-040A, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r390-oct2-167903714700658
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 744K
-rw-r--r-- 1 mcc users 8.6K Feb 25 21:10 CTLCardinality.txt
-rw-r--r-- 1 mcc users 99K Feb 25 21:10 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Feb 25 21:02 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 25 21:02 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 17:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 21:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 137K Feb 25 21:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Feb 25 21:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 25 21:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 268K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-00
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-01
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-02
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-03
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-04
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-05
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-06
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-07
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-08
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-09
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-10
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-11
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-12
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-13
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-14
FORMULA_NAME ShieldPPPt-PT-040A-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679257621115
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ShieldPPPt-PT-040A
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT ShieldPPPt-PT-040A
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA ShieldPPPt-PT-040A-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPt-PT-040A-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPt-PT-040A-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPt-PT-040A-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPt-PT-040A-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPt-PT-040A-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPt-PT-040A-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPt-PT-040A-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPt-PT-040A-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPt-PT-040A-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679257830693
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 7 (type EXCL) for 6 ShieldPPPt-PT-040A-CTLFireability-02
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 66 (type FNDP) for 19 ShieldPPPt-PT-040A-CTLFireability-05
lola: time limit : 32000000 sec
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lola: LAUNCH task # 67 (type EQUN) for 19 ShieldPPPt-PT-040A-CTLFireability-05
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lola: LAUNCH task # 69 (type SRCH) for 19 ShieldPPPt-PT-040A-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 66 (type FNDP) for ShieldPPPt-PT-040A-CTLFireability-05
lola: result : true
lola: fired transitions : 40
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 67 (type EQUN) for ShieldPPPt-PT-040A-CTLFireability-05 (obsolete)
lola: CANCELED task # 69 (type SRCH) for ShieldPPPt-PT-040A-CTLFireability-05 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 69 (type SRCH) for ShieldPPPt-PT-040A-CTLFireability-05
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-67.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldPPPt-PT-040A-CTLFireability-05: AG false findpath
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ShieldPPPt-PT-040A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 4/189 4/32 ShieldPPPt-PT-040A-CTLFireability-02 455314 m, 91062 m/sec, 1622890 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 9/189 7/32 ShieldPPPt-PT-040A-CTLFireability-02 896176 m, 88172 m/sec, 3309039 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 14/189 11/32 ShieldPPPt-PT-040A-CTLFireability-02 1344775 m, 89719 m/sec, 5103851 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 19/189 14/32 ShieldPPPt-PT-040A-CTLFireability-02 1781952 m, 87435 m/sec, 6852462 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 24/189 17/32 ShieldPPPt-PT-040A-CTLFireability-02 2208396 m, 85288 m/sec, 8609294 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 29/189 20/32 ShieldPPPt-PT-040A-CTLFireability-02 2625384 m, 83397 m/sec, 10341715 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 34/189 24/32 ShieldPPPt-PT-040A-CTLFireability-02 3034940 m, 81911 m/sec, 12026807 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 39/189 27/32 ShieldPPPt-PT-040A-CTLFireability-02 3442440 m, 81500 m/sec, 13748197 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 44/189 30/32 ShieldPPPt-PT-040A-CTLFireability-02 3845827 m, 80677 m/sec, 15449054 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ShieldPPPt-PT-040A-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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lola: result : true
lola: markings : 271622
lola: fired transitions : 274470
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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ShieldPPPt-PT-040A-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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46 CTL EXCL 9/221 7/32 ShieldPPPt-PT-040A-CTLFireability-11 868403 m, 85269 m/sec, 3862936 t fired, .
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46 CTL EXCL 29/221 19/32 ShieldPPPt-PT-040A-CTLFireability-11 2406269 m, 74408 m/sec, 11619219 t fired, .
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46 CTL EXCL 34/221 21/32 ShieldPPPt-PT-040A-CTLFireability-11 2746168 m, 67979 m/sec, 13373618 t fired, .
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46 CTL EXCL 39/221 24/32 ShieldPPPt-PT-040A-CTLFireability-11 3109722 m, 72710 m/sec, 15234586 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 0 0 0 3 0 1 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 1 0 0 3 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 CTL EXCL 5/684 7/32 ShieldPPPt-PT-040A-CTLFireability-15 751689 m, 150337 m/sec, 2636248 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-03: CONJ false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-04: CTL false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-05: AG false findpath
ShieldPPPt-PT-040A-CTLFireability-12: EXEF true state space /EXEF
ShieldPPPt-PT-040A-CTLFireability-14: CTL true CTL model checker
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ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 1 0 0 3 0 0 0
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62 CTL EXCL 10/684 13/32 ShieldPPPt-PT-040A-CTLFireability-15 1435950 m, 136852 m/sec, 5137749 t fired, .
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ShieldPPPt-PT-040A-CTLFireability-00: CTL true CTL model checker
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ShieldPPPt-PT-040A-CTLFireability-03: CONJ false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-04: CTL false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-05: AG false findpath
ShieldPPPt-PT-040A-CTLFireability-12: EXEF true state space /EXEF
ShieldPPPt-PT-040A-CTLFireability-14: CTL true CTL model checker
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ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 1 0 0 3 0 0 0
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ShieldPPPt-PT-040A-CTLFireability-01: CTL false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-03: CONJ false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-04: CTL false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-05: AG false findpath
ShieldPPPt-PT-040A-CTLFireability-12: EXEF true state space /EXEF
ShieldPPPt-PT-040A-CTLFireability-14: CTL true CTL model checker
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ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 1 0 0 3 0 0 0
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ShieldPPPt-PT-040A-CTLFireability-03: CONJ false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-04: CTL false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-05: AG false findpath
ShieldPPPt-PT-040A-CTLFireability-12: EXEF true state space /EXEF
ShieldPPPt-PT-040A-CTLFireability-14: CTL true CTL model checker
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ShieldPPPt-PT-040A-CTLFireability-00: CTL true CTL model checker
ShieldPPPt-PT-040A-CTLFireability-01: CTL false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-03: CONJ false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-04: CTL false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-05: AG false findpath
ShieldPPPt-PT-040A-CTLFireability-12: EXEF true state space /EXEF
ShieldPPPt-PT-040A-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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ShieldPPPt-PT-040A-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ShieldPPPt-PT-040A-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
ShieldPPPt-PT-040A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ShieldPPPt-PT-040A-CTLFireability-09: DISJ 0 0 0 0 3 0 1 0
ShieldPPPt-PT-040A-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
ShieldPPPt-PT-040A-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
ShieldPPPt-PT-040A-CTLFireability-13: DISJ 0 1 0 0 3 0 0 0
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lola: LAUNCH task # 28 (type EXCL) for 25 ShieldPPPt-PT-040A-CTLFireability-07
lola: time limit : 848 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for ShieldPPPt-PT-040A-CTLFireability-07
lola: result : true
lola: markings : 13032
lola: fired transitions : 15252
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 51 ShieldPPPt-PT-040A-CTLFireability-13
lola: time limit : 1696 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for ShieldPPPt-PT-040A-CTLFireability-13
lola: result : false
lola: markings : 71105
lola: fired transitions : 90351
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 ShieldPPPt-PT-040A-CTLFireability-08
lola: time limit : 3391 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for ShieldPPPt-PT-040A-CTLFireability-08
lola: result : false
lola: markings : 170
lola: fired transitions : 171
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ShieldPPPt-PT-040A-CTLFireability-00: CTL true CTL model checker
ShieldPPPt-PT-040A-CTLFireability-01: CTL false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-02: CTL unknown AGGR
ShieldPPPt-PT-040A-CTLFireability-03: CONJ false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-04: CTL false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-05: AG false findpath
ShieldPPPt-PT-040A-CTLFireability-06: CTL unknown AGGR
ShieldPPPt-PT-040A-CTLFireability-07: DISJ true CTL model checker
ShieldPPPt-PT-040A-CTLFireability-08: CTL false CTL model checker
ShieldPPPt-PT-040A-CTLFireability-09: DISJ unknown DISJ
ShieldPPPt-PT-040A-CTLFireability-10: CTL unknown AGGR
ShieldPPPt-PT-040A-CTLFireability-11: CTL unknown AGGR
ShieldPPPt-PT-040A-CTLFireability-12: EXEF true state space /EXEF
ShieldPPPt-PT-040A-CTLFireability-13: DISJ false DISJ
ShieldPPPt-PT-040A-CTLFireability-14: CTL true CTL model checker
ShieldPPPt-PT-040A-CTLFireability-15: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldPPPt-PT-040A"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ShieldPPPt-PT-040A, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r390-oct2-167903714700658"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ShieldPPPt-PT-040A.tgz
mv ShieldPPPt-PT-040A execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;