Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r361-smll-167891811000194.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool ltsminxred
Input is RwMutex-PT-r2000w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r361-smll-167891811000194
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.9M
-rw-r--r-- 1 mcc users 8.0K Feb 25 22:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 90K Feb 25 22:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 25 22:47 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 22:47 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 21K Feb 25 16:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 23:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Feb 25 23:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 23:06 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 95K Feb 25 23:06 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.4M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-00
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-01
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-02
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-03
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-04
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-05
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-06
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-07
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-08
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-09
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-10
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-11
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-12
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-13
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-14
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679081883751

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r2000w0010
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202303021504
[2023-03-17 19:38:06] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 19:38:06] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 19:38:07] [INFO ] Load time of PNML (sax parser for PT used): 749 ms
[2023-03-17 19:38:07] [INFO ] Transformed 6020 places.
[2023-03-17 19:38:07] [INFO ] Transformed 4020 transitions.
[2023-03-17 19:38:07] [INFO ] Found NUPN structural information;
[2023-03-17 19:38:07] [INFO ] Parsed PT model containing 6020 places and 4020 transitions and 52040 arcs in 935 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 23 ms.
Support contains 2110 out of 6020 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 665 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
// Phase 1: matrix 4020 rows 6020 cols
[2023-03-17 19:38:08] [INFO ] Computed 4010 place invariants in 119 ms
[2023-03-17 19:38:10] [INFO ] Implicit Places using invariants in 2135 ms returned []
[2023-03-17 19:38:10] [INFO ] Invariant cache hit.
[2023-03-17 19:38:12] [INFO ] Implicit Places using invariants and state equation in 1576 ms returned []
Implicit Place search using SMT with State Equation took 3760 ms to find 0 implicit places.
[2023-03-17 19:38:12] [INFO ] Invariant cache hit.
[2023-03-17 19:38:13] [INFO ] Dead Transitions using invariants and state equation in 1403 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5841 ms. Remains : 6020/6020 places, 4020/4020 transitions.
Support contains 2110 out of 6020 places after structural reductions.
[2023-03-17 19:38:25] [INFO ] Flatten gal took : 11688 ms
[2023-03-17 19:38:36] [INFO ] Flatten gal took : 11162 ms
[2023-03-17 19:38:38] [INFO ] Input system was already deterministic with 4020 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 4494 ms. (steps per millisecond=2 ) properties (out of 87) seen :85
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 711 ms. (steps per millisecond=14 ) properties (out of 2) seen :1
Finished Best-First random walk after 2011 steps, including 0 resets, run visited all 1 properties in 167 ms. (steps per millisecond=12 )
[2023-03-17 19:38:54] [INFO ] Flatten gal took : 11175 ms
[2023-03-17 19:39:06] [INFO ] Flatten gal took : 11198 ms
[2023-03-17 19:39:06] [INFO ] Input system was already deterministic with 4020 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Drop transitions removed 1997 transitions
Trivial Post-agglo rules discarded 1997 transitions
Performed 1997 trivial Post agglomeration. Transition count delta: 1997
Iterating post reduction 0 with 1997 rules applied. Total rules applied 1997 place count 6020 transition count 2023
Reduce places removed 3994 places and 0 transitions.
Iterating post reduction 1 with 3994 rules applied. Total rules applied 5991 place count 2026 transition count 2023
Applied a total of 5991 rules in 1968 ms. Remains 2026 /6020 variables (removed 3994) and now considering 2023/4020 (removed 1997) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1974 ms. Remains : 2026/6020 places, 2023/4020 transitions.
[2023-03-17 19:39:19] [INFO ] Flatten gal took : 10605 ms
[2023-03-17 19:39:30] [INFO ] Flatten gal took : 10423 ms
[2023-03-17 19:39:30] [INFO ] Input system was already deterministic with 2023 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 688 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 690 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:39:41] [INFO ] Flatten gal took : 10586 ms
[2023-03-17 19:39:52] [INFO ] Flatten gal took : 10918 ms
[2023-03-17 19:39:53] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 684 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 690 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:40:05] [INFO ] Flatten gal took : 10810 ms
[2023-03-17 19:40:15] [INFO ] Flatten gal took : 10750 ms
[2023-03-17 19:40:16] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 578 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 586 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:40:27] [INFO ] Flatten gal took : 10699 ms
[2023-03-17 19:40:38] [INFO ] Flatten gal took : 10567 ms
[2023-03-17 19:40:39] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 684 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 685 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:40:50] [INFO ] Flatten gal took : 10681 ms
[2023-03-17 19:41:00] [INFO ] Flatten gal took : 10166 ms
[2023-03-17 19:41:01] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 664 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 665 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:41:12] [INFO ] Flatten gal took : 9893 ms
[2023-03-17 19:41:22] [INFO ] Flatten gal took : 10327 ms
[2023-03-17 19:41:23] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 692 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 693 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:41:34] [INFO ] Flatten gal took : 10191 ms
[2023-03-17 19:41:44] [INFO ] Flatten gal took : 9981 ms
[2023-03-17 19:41:44] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Drop transitions removed 1988 transitions
Trivial Post-agglo rules discarded 1988 transitions
Performed 1988 trivial Post agglomeration. Transition count delta: 1988
Iterating post reduction 0 with 1988 rules applied. Total rules applied 1988 place count 6020 transition count 2032
Reduce places removed 3976 places and 0 transitions.
Iterating post reduction 1 with 3976 rules applied. Total rules applied 5964 place count 2044 transition count 2032
Applied a total of 5964 rules in 1492 ms. Remains 2044 /6020 variables (removed 3976) and now considering 2032/4020 (removed 1988) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1496 ms. Remains : 2044/6020 places, 2032/4020 transitions.
[2023-03-17 19:41:57] [INFO ] Flatten gal took : 10809 ms
[2023-03-17 19:42:07] [INFO ] Flatten gal took : 10233 ms
[2023-03-17 19:42:07] [INFO ] Input system was already deterministic with 2032 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 914 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 915 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:42:18] [INFO ] Flatten gal took : 10152 ms
[2023-03-17 19:42:29] [INFO ] Flatten gal took : 10854 ms
[2023-03-17 19:42:30] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 884 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 888 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:42:41] [INFO ] Flatten gal took : 10481 ms
[2023-03-17 19:42:52] [INFO ] Flatten gal took : 10649 ms
[2023-03-17 19:42:53] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 668 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 672 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:43:04] [INFO ] Flatten gal took : 10652 ms
[2023-03-17 19:43:15] [INFO ] Flatten gal took : 10620 ms
[2023-03-17 19:43:15] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 704 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 707 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:43:27] [INFO ] Flatten gal took : 10788 ms
[2023-03-17 19:43:38] [INFO ] Flatten gal took : 10911 ms
[2023-03-17 19:43:38] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 700 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 701 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:43:50] [INFO ] Flatten gal took : 10861 ms
[2023-03-17 19:44:01] [INFO ] Flatten gal took : 10801 ms
[2023-03-17 19:44:01] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Drop transitions removed 2006 transitions
Trivial Post-agglo rules discarded 2006 transitions
Performed 2006 trivial Post agglomeration. Transition count delta: 2006
Iterating post reduction 0 with 2006 rules applied. Total rules applied 2006 place count 6020 transition count 2014
Reduce places removed 6008 places and 0 transitions.
Ensure Unique test removed 2004 transitions
Reduce isomorphic transitions removed 2004 transitions.
Iterating post reduction 1 with 8012 rules applied. Total rules applied 10018 place count 12 transition count 10
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 10019 place count 12 transition count 9
Ensure Unique test removed 4 places
Iterating post reduction 2 with 4 rules applied. Total rules applied 10023 place count 8 transition count 9
Applied a total of 10023 rules in 61 ms. Remains 8 /6020 variables (removed 6012) and now considering 9/4020 (removed 4011) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 62 ms. Remains : 8/6020 places, 9/4020 transitions.
[2023-03-17 19:44:02] [INFO ] Flatten gal took : 1 ms
[2023-03-17 19:44:02] [INFO ] Flatten gal took : 0 ms
[2023-03-17 19:44:02] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 736 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 737 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-17 19:44:13] [INFO ] Flatten gal took : 10538 ms
[2023-03-17 19:44:23] [INFO ] Flatten gal took : 10620 ms
[2023-03-17 19:44:24] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Drop transitions removed 1999 transitions
Trivial Post-agglo rules discarded 1999 transitions
Performed 1999 trivial Post agglomeration. Transition count delta: 1999
Iterating post reduction 0 with 1999 rules applied. Total rules applied 1999 place count 6020 transition count 2021
Reduce places removed 3998 places and 0 transitions.
Iterating post reduction 1 with 3998 rules applied. Total rules applied 5997 place count 2022 transition count 2021
Applied a total of 5997 rules in 1418 ms. Remains 2022 /6020 variables (removed 3998) and now considering 2021/4020 (removed 1999) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1422 ms. Remains : 2022/6020 places, 2021/4020 transitions.
[2023-03-17 19:44:36] [INFO ] Flatten gal took : 10771 ms
[2023-03-17 19:44:47] [INFO ] Flatten gal took : 10378 ms
[2023-03-17 19:44:47] [INFO ] Input system was already deterministic with 2021 transitions.
[2023-03-17 19:44:58] [INFO ] Flatten gal took : 10827 ms
[2023-03-17 19:45:09] [INFO ] Flatten gal took : 10993 ms
[2023-03-17 19:45:09] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 16 ms.
[2023-03-17 19:45:09] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 6020 places, 4020 transitions and 52040 arcs took 67 ms.
Total runtime 423171 ms.
There are residual formulas that ITS could not solve within timeout
pnml2lts-sym model.pnml --lace-workers=4 --vset=lddmc --saturation=sat -rbs,w2W,ru,hf --sylvan-sizes=20,28,20,28 --ctl=/tmp/486/ctl_0_ --ctl=/tmp/486/ctl_1_ --ctl=/tmp/486/ctl_2_ --ctl=/tmp/486/ctl_3_ --ctl=/tmp/486/ctl_4_ --ctl=/tmp/486/ctl_5_ --ctl=/tmp/486/ctl_6_ --ctl=/tmp/486/ctl_7_ --ctl=/tmp/486/ctl_8_ --ctl=/tmp/486/ctl_9_ --ctl=/tmp/486/ctl_10_ --ctl=/tmp/486/ctl_11_ --ctl=/tmp/486/ctl_12_ --ctl=/tmp/486/ctl_13_ --ctl=/tmp/486/ctl_14_ --ctl=/tmp/486/ctl_15_ --mu-par --mu-opt
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 15850760 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16085972 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2023

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r2000w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool ltsminxred"
echo " Input is RwMutex-PT-r2000w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r361-smll-167891811000194"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r2000w0010.tgz
mv RwMutex-PT-r2000w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;