About the Execution of LoLa+red for SharedMemory-PT-000010
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2995.447 | 284014.00 | 300291.00 | 1465.40 | FTFTTFFTFFFFTTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r359-smll-167891809300666.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SharedMemory-PT-000010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891809300666
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.6M
-rw-r--r-- 1 mcc users 37K Feb 25 14:08 CTLCardinality.txt
-rw-r--r-- 1 mcc users 200K Feb 25 14:08 CTLCardinality.xml
-rw-r--r-- 1 mcc users 67K Feb 25 14:03 CTLFireability.txt
-rw-r--r-- 1 mcc users 302K Feb 25 14:03 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 17K Feb 25 16:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 63K Feb 25 16:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 34K Feb 25 16:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 115K Feb 25 16:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 94K Feb 25 14:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 523K Feb 25 14:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 189K Feb 25 14:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 836K Feb 25 14:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 8.7K Feb 25 16:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 104K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-00
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-01
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-02
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-03
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-04
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-05
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-06
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-07
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-08
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-09
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-10
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-11
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-12
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-13
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-14
FORMULA_NAME SharedMemory-PT-000010-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679271831532
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SharedMemory-PT-000010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-20 00:23:55] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-20 00:23:55] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-20 00:23:55] [INFO ] Load time of PNML (sax parser for PT used): 101 ms
[2023-03-20 00:23:55] [INFO ] Transformed 131 places.
[2023-03-20 00:23:55] [INFO ] Transformed 210 transitions.
[2023-03-20 00:23:55] [INFO ] Found NUPN structural information;
[2023-03-20 00:23:55] [INFO ] Completing missing partition info from NUPN : creating a component with [Ext_Mem_Acc_10_6, Ext_Mem_Acc_8_7]
[2023-03-20 00:23:55] [INFO ] Parsed PT model containing 131 places and 210 transitions and 800 arcs in 222 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 38 ms.
Support contains 131 out of 131 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 22 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
// Phase 1: matrix 210 rows 131 cols
[2023-03-20 00:23:55] [INFO ] Computed 21 place invariants in 28 ms
[2023-03-20 00:23:55] [INFO ] Implicit Places using invariants in 377 ms returned []
[2023-03-20 00:23:55] [INFO ] Invariant cache hit.
[2023-03-20 00:23:56] [INFO ] Implicit Places using invariants and state equation in 199 ms returned []
Implicit Place search using SMT with State Equation took 631 ms to find 0 implicit places.
[2023-03-20 00:23:56] [INFO ] Invariant cache hit.
[2023-03-20 00:23:56] [INFO ] Dead Transitions using invariants and state equation in 352 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1010 ms. Remains : 131/131 places, 210/210 transitions.
Support contains 131 out of 131 places after structural reductions.
[2023-03-20 00:23:57] [INFO ] Flatten gal took : 188 ms
[2023-03-20 00:23:58] [INFO ] Flatten gal took : 100 ms
[2023-03-20 00:23:58] [INFO ] Input system was already deterministic with 210 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 972 ms. (steps per millisecond=10 ) properties (out of 56) seen :50
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 296 ms. (steps per millisecond=33 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-20 00:24:00] [INFO ] Invariant cache hit.
[2023-03-20 00:24:00] [INFO ] [Real]Absence check using 21 positive place invariants in 11 ms returned sat
[2023-03-20 00:24:00] [INFO ] After 159ms SMT Verify possible using all constraints in real domain returned unsat :5 sat :0 real:1
[2023-03-20 00:24:00] [INFO ] [Nat]Absence check using 21 positive place invariants in 13 ms returned sat
[2023-03-20 00:24:00] [INFO ] After 88ms SMT Verify possible using all constraints in natural domain returned unsat :6 sat :0
Fused 6 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 6 atomic propositions for a total of 16 simplifications.
[2023-03-20 00:24:00] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2023-03-20 00:24:00] [INFO ] Flatten gal took : 34 ms
FORMULA SharedMemory-PT-000010-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SharedMemory-PT-000010-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-20 00:24:00] [INFO ] Flatten gal took : 61 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 3 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 20 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 26 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 17 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 16 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 19 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 3 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 13 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 14 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 2 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 13 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 20 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 2 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 14 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 18 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 18 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 13 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 13 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 1 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 12 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 16 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 6 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 11 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 12 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 7 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 10 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 11 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 7 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 9 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 9 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 7 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 8 ms
[2023-03-20 00:24:01] [INFO ] Flatten gal took : 9 ms
[2023-03-20 00:24:01] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 20 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:02] [INFO ] Flatten gal took : 8 ms
[2023-03-20 00:24:02] [INFO ] Flatten gal took : 8 ms
[2023-03-20 00:24:02] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 3 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:02] [INFO ] Flatten gal took : 8 ms
[2023-03-20 00:24:02] [INFO ] Flatten gal took : 8 ms
[2023-03-20 00:24:02] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 3 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-20 00:24:02] [INFO ] Flatten gal took : 7 ms
[2023-03-20 00:24:02] [INFO ] Flatten gal took : 8 ms
[2023-03-20 00:24:02] [INFO ] Input system was already deterministic with 210 transitions.
[2023-03-20 00:24:02] [INFO ] Flatten gal took : 30 ms
[2023-03-20 00:24:02] [INFO ] Flatten gal took : 30 ms
[2023-03-20 00:24:02] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 46 ms.
[2023-03-20 00:24:02] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 131 places, 210 transitions and 800 arcs took 2 ms.
Total runtime 7508 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SharedMemory-PT-000010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability
FORMULA SharedMemory-PT-000010-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SharedMemory-PT-000010-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679272115546
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type SKEL/FNDP) for 36 SharedMemory-PT-000010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SKEL/EQUN) for 36 SharedMemory-PT-000010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type SKEL/SRCH) for 36 SharedMemory-PT-000010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/SRCH) for 36 SharedMemory-PT-000010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 54 (type SKEL/SRCH) for SharedMemory-PT-000010-CTLFireability-14
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH INITIAL
lola: LAUNCH task # 43 (type CNST) for 36 SharedMemory-PT-000010-CTLFireability-14
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 51 (type SKEL/FNDP) for SharedMemory-PT-000010-CTLFireability-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 52 (type EQUN) for SharedMemory-PT-000010-CTLFireability-14 (obsolete)
lola: CANCELED task # 53 (type SRCH) for SharedMemory-PT-000010-CTLFireability-14 (obsolete)
lola: FINISHED task # 53 (type SKEL/SRCH) for SharedMemory-PT-000010-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 43 (type CNST) for SharedMemory-PT-000010-CTLFireability-14
lola: result : true
lola: LAUNCH task # 7 (type EXCL) for 6 SharedMemory-PT-000010-CTLFireability-02
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 7 (type EXCL) for SharedMemory-PT-000010-CTLFireability-02
lola: result : false
lola: markings : 68
lola: fired transitions : 186
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 SharedMemory-PT-000010-CTLFireability-07
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 22 (type EXCL) for SharedMemory-PT-000010-CTLFireability-07
lola: result : true
lola: markings : 69
lola: fired transitions : 252
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 25 (type EXCL) for 24 SharedMemory-PT-000010-CTLFireability-08
lola: time limit : 239 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/372/CTLFireability-52.sara.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 52 (type SKEL/EQUN) for SharedMemory-PT-000010-CTLFireability-14
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 55 (type FNDP) for 36 SharedMemory-PT-000010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 36 SharedMemory-PT-000010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 58 (type SRCH) for 36 SharedMemory-PT-000010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 58 (type SRCH) for SharedMemory-PT-000010-CTLFireability-14
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 55 (type FNDP) for SharedMemory-PT-000010-CTLFireability-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 56 (type EQUN) for SharedMemory-PT-000010-CTLFireability-14 (obsolete)
sara: try reading problem file /home/mcc/execution/372/CTLFireability-56.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 56 (type EQUN) for SharedMemory-PT-000010-CTLFireability-14
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SharedMemory-PT-000010-CTLFireability-14: CONJ 0 1 0 0 8 0 0 1
SharedMemory-PT-000010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/299 3/32 SharedMemory-PT-000010-CTLFireability-08 396191 m, 79238 m/sec, 3047489 t fired, .
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SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SharedMemory-PT-000010-CTLFireability-14: CONJ 0 1 0 0 8 0 0 1
SharedMemory-PT-000010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/299 4/32 SharedMemory-PT-000010-CTLFireability-08 712663 m, 63294 m/sec, 6304074 t fired, .
Time elapsed: 18 secs. Pages in use: 4
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SharedMemory-PT-000010-CTLFireability-14: CONJ 0 1 0 0 8 0 0 1
SharedMemory-PT-000010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/299 6/32 SharedMemory-PT-000010-CTLFireability-08 1015023 m, 60472 m/sec, 9694001 t fired, .
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SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SharedMemory-PT-000010-CTLFireability-14: CONJ 0 1 0 0 8 0 0 1
SharedMemory-PT-000010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/299 7/32 SharedMemory-PT-000010-CTLFireability-08 1299208 m, 56837 m/sec, 12998143 t fired, .
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SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-14: CONJ 0 1 0 0 8 0 0 1
SharedMemory-PT-000010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/299 9/32 SharedMemory-PT-000010-CTLFireability-08 1564202 m, 52998 m/sec, 16151969 t fired, .
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SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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SharedMemory-PT-000010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-14: CONJ 0 1 0 0 8 0 0 1
SharedMemory-PT-000010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 30/299 10/32 SharedMemory-PT-000010-CTLFireability-08 1801288 m, 47417 m/sec, 19200465 t fired, .
Time elapsed: 38 secs. Pages in use: 10
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lola: FINISHED task # 25 (type EXCL) for SharedMemory-PT-000010-CTLFireability-08
lola: result : false
lola: markings : 1830519
lola: fired transitions : 21881520
lola: time used : 34.000000
lola: memory pages used : 10
lola: LAUNCH task # 48 (type EXCL) for 47 SharedMemory-PT-000010-CTLFireability-15
lola: time limit : 323 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
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SharedMemory-PT-000010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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48 CTL EXCL 1/323 1/32 SharedMemory-PT-000010-CTLFireability-15 100286 m, 20057 m/sec, 566520 t fired, .
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48 CTL EXCL 6/323 3/32 SharedMemory-PT-000010-CTLFireability-15 504923 m, 80927 m/sec, 3965319 t fired, .
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48 CTL EXCL 11/323 5/32 SharedMemory-PT-000010-CTLFireability-15 821811 m, 63377 m/sec, 7284893 t fired, .
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48 CTL EXCL 16/323 6/32 SharedMemory-PT-000010-CTLFireability-15 1122790 m, 60195 m/sec, 10623722 t fired, .
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48 CTL EXCL 21/323 8/32 SharedMemory-PT-000010-CTLFireability-15 1393846 m, 54211 m/sec, 13789888 t fired, .
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SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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SharedMemory-PT-000010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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48 CTL EXCL 26/323 9/32 SharedMemory-PT-000010-CTLFireability-15 1666683 m, 54567 m/sec, 16912003 t fired, .
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SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-14: CONJ 0 1 0 0 8 0 0 1
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48 CTL EXCL 31/323 10/32 SharedMemory-PT-000010-CTLFireability-15 1830518 m, 32767 m/sec, 19944461 t fired, .
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lola: FINISHED task # 48 (type EXCL) for SharedMemory-PT-000010-CTLFireability-15
lola: result : false
lola: markings : 1830519
lola: fired transitions : 21327007
lola: time used : 33.000000
lola: memory pages used : 10
lola: LAUNCH task # 45 (type EXCL) for 36 SharedMemory-PT-000010-CTLFireability-14
lola: time limit : 352 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for SharedMemory-PT-000010-CTLFireability-14
lola: result : true
lola: markings : 9
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 SharedMemory-PT-000010-CTLFireability-11
lola: time limit : 391 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
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SharedMemory-PT-000010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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31 CTL EXCL 3/391 2/32 SharedMemory-PT-000010-CTLFireability-11 199901 m, 39980 m/sec, 1910972 t fired, .
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SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
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31 CTL EXCL 8/391 3/32 SharedMemory-PT-000010-CTLFireability-11 460661 m, 52152 m/sec, 5074786 t fired, .
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31 CTL EXCL 13/391 4/32 SharedMemory-PT-000010-CTLFireability-11 691530 m, 46173 m/sec, 8213100 t fired, .
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31 CTL EXCL 18/391 5/32 SharedMemory-PT-000010-CTLFireability-11 917385 m, 45171 m/sec, 11387562 t fired, .
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31 CTL EXCL 23/391 6/32 SharedMemory-PT-000010-CTLFireability-11 1126646 m, 41852 m/sec, 14494251 t fired, .
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31 CTL EXCL 28/391 7/32 SharedMemory-PT-000010-CTLFireability-11 1337057 m, 42082 m/sec, 17587836 t fired, .
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31 CTL EXCL 33/391 8/32 SharedMemory-PT-000010-CTLFireability-11 1539777 m, 40544 m/sec, 20613746 t fired, .
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31 CTL EXCL 38/391 9/32 SharedMemory-PT-000010-CTLFireability-11 1731872 m, 38419 m/sec, 23556159 t fired, .
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31 CTL EXCL 43/391 10/32 SharedMemory-PT-000010-CTLFireability-11 1830519 m, 19729 m/sec, 26573035 t fired, .
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lola: FINISHED task # 31 (type EXCL) for SharedMemory-PT-000010-CTLFireability-11
lola: result : false
lola: markings : 1830519
lola: fired transitions : 27560168
lola: time used : 44.000000
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lola: FINISHED task # 28 (type EXCL) for SharedMemory-PT-000010-CTLFireability-10
lola: result : false
lola: markings : 211
lola: fired transitions : 759
lola: time used : 0.000000
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lola: LAUNCH task # 19 (type EXCL) for 18 SharedMemory-PT-000010-CTLFireability-06
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19 CTL EXCL 4/497 3/32 SharedMemory-PT-000010-CTLFireability-06 396766 m, 79353 m/sec, 893312 t fired, .
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19 CTL EXCL 9/497 4/32 SharedMemory-PT-000010-CTLFireability-06 733728 m, 67392 m/sec, 2011241 t fired, .
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19 CTL EXCL 14/497 6/32 SharedMemory-PT-000010-CTLFireability-06 1007944 m, 54843 m/sec, 3025025 t fired, .
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19 CTL EXCL 19/497 7/32 SharedMemory-PT-000010-CTLFireability-06 1290757 m, 56562 m/sec, 4104876 t fired, .
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19 CTL EXCL 24/497 9/32 SharedMemory-PT-000010-CTLFireability-06 1559504 m, 53749 m/sec, 5149764 t fired, .
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19 CTL EXCL 29/497 10/32 SharedMemory-PT-000010-CTLFireability-06 1829508 m, 54000 m/sec, 6289800 t fired, .
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19 CTL EXCL 39/497 10/32 SharedMemory-PT-000010-CTLFireability-06 1830509 m, 200 m/sec, 13365911 t fired, .
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19 CTL EXCL 44/497 10/32 SharedMemory-PT-000010-CTLFireability-06 1830519 m, 2 m/sec, 17053644 t fired, .
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19 CTL EXCL 49/497 10/32 SharedMemory-PT-000010-CTLFireability-06 1830519 m, 0 m/sec, 20074350 t fired, .
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lola: FINISHED task # 19 (type EXCL) for SharedMemory-PT-000010-CTLFireability-06
lola: result : false
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SharedMemory-PT-000010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 11/568 4/32 SharedMemory-PT-000010-CTLFireability-04 607136 m, 51266 m/sec, 6311116 t fired, .
Time elapsed: 198 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 16/568 5/32 SharedMemory-PT-000010-CTLFireability-04 846392 m, 47851 m/sec, 9371709 t fired, .
Time elapsed: 203 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 21/568 6/32 SharedMemory-PT-000010-CTLFireability-04 1074088 m, 45539 m/sec, 12415460 t fired, .
Time elapsed: 208 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 26/568 7/32 SharedMemory-PT-000010-CTLFireability-04 1295719 m, 44326 m/sec, 15372706 t fired, .
Time elapsed: 213 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 31/568 8/32 SharedMemory-PT-000010-CTLFireability-04 1502279 m, 41312 m/sec, 18239257 t fired, .
Time elapsed: 218 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 36/568 9/32 SharedMemory-PT-000010-CTLFireability-04 1708173 m, 41178 m/sec, 21057694 t fired, .
Time elapsed: 223 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 41/568 10/32 SharedMemory-PT-000010-CTLFireability-04 1830518 m, 24469 m/sec, 23850158 t fired, .
Time elapsed: 228 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 13 (type EXCL) for SharedMemory-PT-000010-CTLFireability-04
lola: result : true
lola: markings : 1830519
lola: fired transitions : 25253590
lola: time used : 43.000000
lola: memory pages used : 10
lola: LAUNCH task # 10 (type EXCL) for 9 SharedMemory-PT-000010-CTLFireability-03
lola: time limit : 674 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for SharedMemory-PT-000010-CTLFireability-03
lola: result : true
lola: markings : 107
lola: fired transitions : 803
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 SharedMemory-PT-000010-CTLFireability-00
lola: time limit : 842 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for SharedMemory-PT-000010-CTLFireability-00
lola: result : false
lola: markings : 654
lola: fired transitions : 2994
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 SharedMemory-PT-000010-CTLFireability-13
lola: time limit : 1123 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for SharedMemory-PT-000010-CTLFireability-13
lola: result : true
lola: markings : 204
lola: fired transitions : 1472
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 SharedMemory-PT-000010-CTLFireability-05
lola: time limit : 1685 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-13: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 3/1685 2/32 SharedMemory-PT-000010-CTLFireability-05 176991 m, 35398 m/sec, 1579735 t fired, .
Time elapsed: 233 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-13: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 8/1685 3/32 SharedMemory-PT-000010-CTLFireability-05 459769 m, 56555 m/sec, 4702547 t fired, .
Time elapsed: 238 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-13: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 13/1685 4/32 SharedMemory-PT-000010-CTLFireability-05 710173 m, 50080 m/sec, 7820115 t fired, .
Time elapsed: 243 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-13: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 18/1685 5/32 SharedMemory-PT-000010-CTLFireability-05 955415 m, 49048 m/sec, 11012984 t fired, .
Time elapsed: 248 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-13: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 23/1685 7/32 SharedMemory-PT-000010-CTLFireability-05 1186842 m, 46285 m/sec, 14133456 t fired, .
Time elapsed: 253 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-13: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 28/1685 8/32 SharedMemory-PT-000010-CTLFireability-05 1409430 m, 44517 m/sec, 17166825 t fired, .
Time elapsed: 258 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-13: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 33/1685 9/32 SharedMemory-PT-000010-CTLFireability-05 1627886 m, 43691 m/sec, 20154319 t fired, .
Time elapsed: 263 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-13: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-PT-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-PT-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 38/1685 10/32 SharedMemory-PT-000010-CTLFireability-05 1809885 m, 36399 m/sec, 23059262 t fired, .
Time elapsed: 268 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 16 (type EXCL) for SharedMemory-PT-000010-CTLFireability-05
lola: result : false
lola: markings : 1830519
lola: fired transitions : 25491101
lola: time used : 42.000000
lola: memory pages used : 10
lola: LAUNCH task # 4 (type EXCL) for 3 SharedMemory-PT-000010-CTLFireability-01
lola: time limit : 3328 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for SharedMemory-PT-000010-CTLFireability-01
lola: result : true
lola: markings : 79
lola: fired transitions : 293
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-PT-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-01: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-05: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-08: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-10: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-11: CTL false CTL model checker
SharedMemory-PT-000010-CTLFireability-13: CTL true CTL model checker
SharedMemory-PT-000010-CTLFireability-14: CONJ true CONJ
SharedMemory-PT-000010-CTLFireability-15: CTL false CTL model checker
Time elapsed: 272 secs. Pages in use: 10
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SharedMemory-PT-000010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SharedMemory-PT-000010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891809300666"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SharedMemory-PT-000010.tgz
mv SharedMemory-PT-000010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;