Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r359-smll-167891809200554.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SharedMemory-COL-000010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891809200554
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 520K
-rw-r--r-- 1 mcc users 8.9K Feb 25 14:06 CTLCardinality.txt
-rw-r--r-- 1 mcc users 93K Feb 25 14:06 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 25 14:01 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 25 14:01 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 16:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 14:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 114K Feb 25 14:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 25 14:11 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 96K Feb 25 14:11 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 12K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-00
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-01
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-02
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-03
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-04
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-05
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-06
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-07
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-08
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-09
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-10
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-11
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-12
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-13
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-14
FORMULA_NAME SharedMemory-COL-000010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679166339609

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SharedMemory-COL-000010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-18 19:05:43] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-18 19:05:43] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-18 19:05:43] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-18 19:05:43] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-18 19:05:43] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 713 ms
[2023-03-18 19:05:44] [INFO ] Imported 6 HL places and 5 HL transitions for a total of 141 PT places and 320.0 transition bindings in 28 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 29 ms.
[2023-03-18 19:05:44] [INFO ] Built PT skeleton of HLPN with 6 places and 5 transitions 16 arcs in 7 ms.
[2023-03-18 19:05:44] [INFO ] Skeletonized 8 HLPN properties in 3 ms. Removed 8 properties that had guard overlaps.
Computed a total of 0 stabilizing places and 0 stable transitions
All 16 properties of the HLPN use transition enablings in a way that makes the skeleton too coarse.
Domain [P(10), P(10)] of place Ext_Mem_Acc breaks symmetries in sort P
[2023-03-18 19:05:44] [INFO ] Unfolded HLPN to a Petri net with 141 places and 220 transitions 840 arcs in 33 ms.
[2023-03-18 19:05:44] [INFO ] Unfolded 16 HLPN properties in 2 ms.
Deduced a syphon composed of 10 places in 13 ms
Reduce places removed 10 places and 10 transitions.
Support contains 131 out of 131 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 14 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
// Phase 1: matrix 210 rows 131 cols
[2023-03-18 19:05:44] [INFO ] Computed 21 place invariants in 21 ms
[2023-03-18 19:05:44] [INFO ] Implicit Places using invariants in 316 ms returned []
[2023-03-18 19:05:44] [INFO ] Invariant cache hit.
[2023-03-18 19:05:44] [INFO ] Implicit Places using invariants and state equation in 214 ms returned []
Implicit Place search using SMT with State Equation took 585 ms to find 0 implicit places.
[2023-03-18 19:05:44] [INFO ] Invariant cache hit.
[2023-03-18 19:05:45] [INFO ] Dead Transitions using invariants and state equation in 345 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 955 ms. Remains : 131/131 places, 210/210 transitions.
Support contains 131 out of 131 places after structural reductions.
[2023-03-18 19:05:45] [INFO ] Flatten gal took : 133 ms
[2023-03-18 19:05:46] [INFO ] Flatten gal took : 66 ms
[2023-03-18 19:05:46] [INFO ] Input system was already deterministic with 210 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 391 ms. (steps per millisecond=25 ) properties (out of 28) seen :27
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 177 ms. (steps per millisecond=56 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-18 19:05:47] [INFO ] Invariant cache hit.
[2023-03-18 19:05:47] [INFO ] [Real]Absence check using 21 positive place invariants in 22 ms returned sat
[2023-03-18 19:05:47] [INFO ] After 105ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-18 19:05:47] [INFO ] Flatten gal took : 54 ms
[2023-03-18 19:05:48] [INFO ] Flatten gal took : 80 ms
[2023-03-18 19:05:48] [INFO ] Input system was already deterministic with 210 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 3 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:48] [INFO ] Flatten gal took : 16 ms
[2023-03-18 19:05:48] [INFO ] Flatten gal took : 23 ms
[2023-03-18 19:05:48] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 18 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:48] [INFO ] Flatten gal took : 16 ms
[2023-03-18 19:05:48] [INFO ] Flatten gal took : 18 ms
[2023-03-18 19:05:48] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 3 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 13 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 13 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 2 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 14 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 16 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 2 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 14 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 14 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 19 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 12 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 12 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 2 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 12 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 14 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 7 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 10 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 10 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 9 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 10 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 10 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 10 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 8 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 10 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 6 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 8 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 9 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 1 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 7 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 7 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 1 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 9 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 12 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 7 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 7 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 7 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 2 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 7 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 10 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 131/131 places, 210/210 transitions.
Applied a total of 0 rules in 1 ms. Remains 131 /131 variables (removed 0) and now considering 210/210 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 131/131 places, 210/210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 7 ms
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 9 ms
[2023-03-18 19:05:49] [INFO ] Input system was already deterministic with 210 transitions.
[2023-03-18 19:05:49] [INFO ] Flatten gal took : 41 ms
[2023-03-18 19:05:50] [INFO ] Flatten gal took : 40 ms
[2023-03-18 19:05:50] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 41 ms.
[2023-03-18 19:05:50] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 131 places, 210 transitions and 800 arcs took 2 ms.
Total runtime 7305 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SharedMemory-COL-000010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA SharedMemory-COL-000010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SharedMemory-COL-000010-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679166681521

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
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1 CTL EXCL 40/211 9/32 SharedMemory-COL-000010-CTLFireability-00 1683342 m, 45320 m/sec, 8153058 t fired, .

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1 CTL EXCL 45/211 10/32 SharedMemory-COL-000010-CTLFireability-00 1816923 m, 26716 m/sec, 10267451 t fired, .

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47 CTL EXCL 4/236 4/32 SharedMemory-COL-000010-CTLFireability-14 596133 m, 119226 m/sec, 2495373 t fired, .

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47 CTL EXCL 9/236 7/32 SharedMemory-COL-000010-CTLFireability-14 1254024 m, 131578 m/sec, 5170133 t fired, .

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47 CTL EXCL 14/236 10/32 SharedMemory-COL-000010-CTLFireability-14 1722029 m, 93601 m/sec, 8032822 t fired, .

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47 CTL EXCL 19/236 10/32 SharedMemory-COL-000010-CTLFireability-14 1819711 m, 19536 m/sec, 10872831 t fired, .

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47 CTL EXCL 24/236 10/32 SharedMemory-COL-000010-CTLFireability-14 1826181 m, 1294 m/sec, 13609169 t fired, .

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47 CTL EXCL 29/236 10/32 SharedMemory-COL-000010-CTLFireability-14 1829167 m, 597 m/sec, 16515325 t fired, .

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47 CTL EXCL 34/236 10/32 SharedMemory-COL-000010-CTLFireability-14 1830376 m, 241 m/sec, 19552172 t fired, .

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41 CTL EXCL 2/270 1/32 SharedMemory-COL-000010-CTLFireability-12 116501 m, 23300 m/sec, 610255 t fired, .

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41 CTL EXCL 7/270 2/32 SharedMemory-COL-000010-CTLFireability-12 346339 m, 45967 m/sec, 1986215 t fired, .

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41 CTL EXCL 12/270 3/32 SharedMemory-COL-000010-CTLFireability-12 552416 m, 41215 m/sec, 3213026 t fired, .

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41 CTL EXCL 17/270 4/32 SharedMemory-COL-000010-CTLFireability-12 745033 m, 38523 m/sec, 4337836 t fired, .

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41 CTL EXCL 22/270 5/32 SharedMemory-COL-000010-CTLFireability-12 924898 m, 35973 m/sec, 5374537 t fired, .

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41 CTL EXCL 27/270 6/32 SharedMemory-COL-000010-CTLFireability-12 1077189 m, 30458 m/sec, 6248061 t fired, .

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41 CTL EXCL 32/270 7/32 SharedMemory-COL-000010-CTLFireability-12 1232082 m, 30978 m/sec, 7120705 t fired, .

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41 CTL EXCL 37/270 8/32 SharedMemory-COL-000010-CTLFireability-12 1372021 m, 27987 m/sec, 7906095 t fired, .

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41 CTL EXCL 42/270 8/32 SharedMemory-COL-000010-CTLFireability-12 1514723 m, 28540 m/sec, 8849782 t fired, .

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41 CTL EXCL 47/270 9/32 SharedMemory-COL-000010-CTLFireability-12 1691117 m, 35278 m/sec, 10506921 t fired, .

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41 CTL EXCL 52/270 10/32 SharedMemory-COL-000010-CTLFireability-12 1808221 m, 23420 m/sec, 12442500 t fired, .

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41 CTL EXCL 57/270 10/32 SharedMemory-COL-000010-CTLFireability-12 1822635 m, 2882 m/sec, 14834353 t fired, .

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41 CTL EXCL 62/270 10/32 SharedMemory-COL-000010-CTLFireability-12 1827359 m, 944 m/sec, 17417872 t fired, .

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41 CTL EXCL 67/270 10/32 SharedMemory-COL-000010-CTLFireability-12 1829516 m, 431 m/sec, 20110234 t fired, .

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41 CTL EXCL 72/270 10/32 SharedMemory-COL-000010-CTLFireability-12 1830454 m, 187 m/sec, 22962660 t fired, .

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19 CTL EXCL 3/491 2/32 SharedMemory-COL-000010-CTLFireability-06 206149 m, 41229 m/sec, 760227 t fired, .

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19 CTL EXCL 8/491 4/32 SharedMemory-COL-000010-CTLFireability-06 596115 m, 77993 m/sec, 2179701 t fired, .

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19 CTL EXCL 13/491 6/32 SharedMemory-COL-000010-CTLFireability-06 971224 m, 75021 m/sec, 3581467 t fired, .

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19 CTL EXCL 18/491 8/32 SharedMemory-COL-000010-CTLFireability-06 1335480 m, 72851 m/sec, 4961229 t fired, .

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19 CTL EXCL 23/491 9/32 SharedMemory-COL-000010-CTLFireability-06 1684107 m, 69725 m/sec, 6325231 t fired, .

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19 CTL EXCL 28/491 10/32 SharedMemory-COL-000010-CTLFireability-06 1830517 m, 29282 m/sec, 8614918 t fired, .

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19 CTL EXCL 33/491 10/32 SharedMemory-COL-000010-CTLFireability-06 1830518 m, 0 m/sec, 11835207 t fired, .

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19 CTL EXCL 38/491 10/32 SharedMemory-COL-000010-CTLFireability-06 1830518 m, 0 m/sec, 14900850 t fired, .

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19 CTL EXCL 43/491 10/32 SharedMemory-COL-000010-CTLFireability-06 1830518 m, 0 m/sec, 17977405 t fired, .

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19 CTL EXCL 48/491 10/32 SharedMemory-COL-000010-CTLFireability-06 1830518 m, 0 m/sec, 21078587 t fired, .

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19 CTL EXCL 53/491 10/32 SharedMemory-COL-000010-CTLFireability-06 1830518 m, 0 m/sec, 23765299 t fired, .

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19 CTL EXCL 58/491 10/32 SharedMemory-COL-000010-CTLFireability-06 1830518 m, 0 m/sec, 26604820 t fired, .

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19 CTL EXCL 63/491 10/32 SharedMemory-COL-000010-CTLFireability-06 1830518 m, 0 m/sec, 29490882 t fired, .

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19 CTL EXCL 68/491 10/32 SharedMemory-COL-000010-CTLFireability-06 1830519 m, 0 m/sec, 32535335 t fired, .

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lola: FINISHED task # 19 (type EXCL) for SharedMemory-COL-000010-CTLFireability-06
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13 CTL EXCL 5/561 3/32 SharedMemory-COL-000010-CTLFireability-04 528995 m, 105799 m/sec, 3291740 t fired, .

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13 CTL EXCL 10/561 6/32 SharedMemory-COL-000010-CTLFireability-04 1033975 m, 100996 m/sec, 6404627 t fired, .

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13 CTL EXCL 15/561 8/32 SharedMemory-COL-000010-CTLFireability-04 1485181 m, 90241 m/sec, 9294899 t fired, .

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13 CTL EXCL 20/561 10/32 SharedMemory-COL-000010-CTLFireability-04 1766791 m, 56322 m/sec, 12333637 t fired, .

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13 CTL EXCL 25/561 10/32 SharedMemory-COL-000010-CTLFireability-04 1820628 m, 10767 m/sec, 15033704 t fired, .

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SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/561 10/32 SharedMemory-COL-000010-CTLFireability-04 1826599 m, 1194 m/sec, 17740520 t fired, .

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SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SharedMemory-COL-000010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/561 10/32 SharedMemory-COL-000010-CTLFireability-04 1829242 m, 528 m/sec, 20521851 t fired, .

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SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/561 10/32 SharedMemory-COL-000010-CTLFireability-04 1830367 m, 225 m/sec, 23412405 t fired, .

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lola: FINISHED task # 13 (type EXCL) for SharedMemory-COL-000010-CTLFireability-04
lola: result : true
lola: markings : 1830519
lola: fired transitions : 25249804
lola: time used : 43.000000
lola: memory pages used : 10
lola: LAUNCH task # 10 (type EXCL) for 9 SharedMemory-COL-000010-CTLFireability-03
lola: time limit : 665 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for SharedMemory-COL-000010-CTLFireability-03
lola: result : true
lola: markings : 2207
lola: fired transitions : 15843
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 SharedMemory-COL-000010-CTLFireability-02
lola: time limit : 831 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for SharedMemory-COL-000010-CTLFireability-02
lola: result : false
lola: markings : 2225
lola: fired transitions : 7176
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 SharedMemory-COL-000010-CTLFireability-05
lola: time limit : 1108 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 2/1108 1/32 SharedMemory-COL-000010-CTLFireability-05 172339 m, 34467 m/sec, 1198769 t fired, .

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SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 7/1108 3/32 SharedMemory-COL-000010-CTLFireability-05 541639 m, 73860 m/sec, 3723046 t fired, .

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SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 12/1108 5/32 SharedMemory-COL-000010-CTLFireability-05 873134 m, 66299 m/sec, 6018299 t fired, .

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SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
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SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 17/1108 7/32 SharedMemory-COL-000010-CTLFireability-05 1187231 m, 62819 m/sec, 8245136 t fired, .

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SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
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SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 22/1108 8/32 SharedMemory-COL-000010-CTLFireability-05 1474898 m, 57533 m/sec, 10379762 t fired, .

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SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
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SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 27/1108 9/32 SharedMemory-COL-000010-CTLFireability-05 1684721 m, 41964 m/sec, 12690956 t fired, .

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SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 32/1108 10/32 SharedMemory-COL-000010-CTLFireability-05 1796884 m, 22432 m/sec, 15615014 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 37/1108 10/32 SharedMemory-COL-000010-CTLFireability-05 1823825 m, 5388 m/sec, 18417822 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 42/1108 10/32 SharedMemory-COL-000010-CTLFireability-05 1827850 m, 805 m/sec, 21264473 t fired, .

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SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 47/1108 10/32 SharedMemory-COL-000010-CTLFireability-05 1829600 m, 350 m/sec, 24098987 t fired, .

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SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SharedMemory-COL-000010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SharedMemory-COL-000010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 52/1108 10/32 SharedMemory-COL-000010-CTLFireability-05 1830412 m, 162 m/sec, 27031428 t fired, .

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# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 16 (type EXCL) for SharedMemory-COL-000010-CTLFireability-05
lola: result : false
lola: markings : 1830519
lola: fired transitions : 28752376
lola: time used : 55.000000
lola: memory pages used : 10
lola: LAUNCH task # 28 (type EXCL) for 27 SharedMemory-COL-000010-CTLFireability-09
lola: time limit : 1635 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for SharedMemory-COL-000010-CTLFireability-09
lola: result : true
lola: markings : 126827
lola: fired transitions : 398934
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 SharedMemory-COL-000010-CTLFireability-01
lola: time limit : 3270 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for SharedMemory-COL-000010-CTLFireability-01
lola: result : true
lola: markings : 487
lola: fired transitions : 5784
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SharedMemory-COL-000010-CTLFireability-00: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-01: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-02: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-03: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-04: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-05: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-06: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-07: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-08: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-09: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-10: CTL true CTL model checker
SharedMemory-COL-000010-CTLFireability-11: DISJ true CTL model checker
SharedMemory-COL-000010-CTLFireability-12: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-13: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-14: CTL false CTL model checker
SharedMemory-COL-000010-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SharedMemory-COL-000010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SharedMemory-COL-000010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891809200554"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SharedMemory-COL-000010.tgz
mv SharedMemory-COL-000010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;