Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r359-smll-167891809100498.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ServersAndClients-PT-200040, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891809100498
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.6M
-rw-r--r-- 1 mcc users 7.6K Feb 26 03:35 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K Feb 26 03:35 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.2K Feb 26 03:33 CTLFireability.txt
-rw-r--r-- 1 mcc users 29K Feb 26 03:33 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 16:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 16:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 03:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 170K Feb 26 03:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 03:37 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 96K Feb 26 03:37 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 5.1M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-00
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-01
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-02
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-03
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-04
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-05
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-06
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-07
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-08
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-09
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-10
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-11
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-12
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-13
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-14
FORMULA_NAME ServersAndClients-PT-200040-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679131239773

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ServersAndClients-PT-200040
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-18 09:20:42] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-18 09:20:42] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-18 09:20:43] [INFO ] Load time of PNML (sax parser for PT used): 801 ms
[2023-03-18 09:20:43] [INFO ] Transformed 8841 places.
[2023-03-18 09:20:43] [INFO ] Transformed 16400 transitions.
[2023-03-18 09:20:43] [INFO ] Parsed PT model containing 8841 places and 16400 transitions and 49600 arcs in 1022 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 25 ms.
Support contains 82 out of 8841 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Applied a total of 0 rules in 3190 ms. Remains 8841 /8841 variables (removed 0) and now considering 16400/16400 (removed 0) transitions.
// Phase 1: matrix 16400 rows 8841 cols
[2023-03-18 09:20:47] [INFO ] Computed 441 place invariants in 405 ms
[2023-03-18 09:20:49] [INFO ] Implicit Places using invariants in 2179 ms returned []
Implicit Place search using SMT only with invariants took 2223 ms to find 0 implicit places.
[2023-03-18 09:20:49] [INFO ] Invariant cache hit.
[2023-03-18 09:20:50] [INFO ] Dead Transitions using invariants and state equation in 1321 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6742 ms. Remains : 8841/8841 places, 16400/16400 transitions.
Support contains 82 out of 8841 places after structural reductions.
[2023-03-18 09:20:51] [INFO ] Flatten gal took : 1091 ms
[2023-03-18 09:20:52] [INFO ] Flatten gal took : 639 ms
[2023-03-18 09:20:54] [INFO ] Input system was already deterministic with 16400 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1139 ms. (steps per millisecond=8 ) properties (out of 50) seen :36
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 14) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 71 ms. (steps per millisecond=140 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 75 ms. (steps per millisecond=133 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 13) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 64 ms. (steps per millisecond=156 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 12) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 11) seen :0
Running SMT prover for 11 properties.
[2023-03-18 09:20:56] [INFO ] Invariant cache hit.
[2023-03-18 09:21:00] [INFO ] [Real]Absence check using 241 positive place invariants in 537 ms returned sat
[2023-03-18 09:21:00] [INFO ] [Real]Absence check using 241 positive and 200 generalized place invariants in 240 ms returned sat
[2023-03-18 09:21:21] [INFO ] After 19313ms SMT Verify possible using state equation in real domain returned unsat :3 sat :7
[2023-03-18 09:21:21] [INFO ] After 19348ms SMT Verify possible using trap constraints in real domain returned unsat :3 sat :7
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-18 09:21:21] [INFO ] After 25090ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :7
Fused 11 Parikh solutions to 3 different solutions.
Parikh walk visited 2 properties in 36 ms.
Support contains 6 out of 8841 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Drop transitions removed 7994 transitions
Trivial Post-agglo rules discarded 7994 transitions
Performed 7994 trivial Post agglomeration. Transition count delta: 7994
Iterating post reduction 0 with 7994 rules applied. Total rules applied 7994 place count 8841 transition count 8406
Reduce places removed 8028 places and 0 transitions.
Ensure Unique test removed 6600 transitions
Reduce isomorphic transitions removed 6600 transitions.
Iterating post reduction 1 with 14628 rules applied. Total rules applied 22622 place count 813 transition count 1806
Drop transitions removed 1194 transitions
Redundant transition composition rules discarded 1194 transitions
Iterating global reduction 2 with 1194 rules applied. Total rules applied 23816 place count 813 transition count 612
Discarding 194 places :
Implicit places reduction removed 194 places
Drop transitions removed 388 transitions
Trivial Post-agglo rules discarded 388 transitions
Performed 388 trivial Post agglomeration. Transition count delta: 388
Iterating post reduction 2 with 582 rules applied. Total rules applied 24398 place count 619 transition count 224
Reduce places removed 582 places and 0 transitions.
Drop transitions removed 194 transitions
Reduce isomorphic transitions removed 194 transitions.
Iterating post reduction 3 with 776 rules applied. Total rules applied 25174 place count 37 transition count 30
Partial Free-agglomeration rule applied 6 times.
Drop transitions removed 6 transitions
Iterating global reduction 4 with 6 rules applied. Total rules applied 25180 place count 37 transition count 30
Applied a total of 25180 rules in 356 ms. Remains 37 /8841 variables (removed 8804) and now considering 30/16400 (removed 16370) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 356 ms. Remains : 37/8841 places, 30/16400 transitions.
Finished random walk after 58 steps, including 0 resets, run visited all 6 properties in 4 ms. (steps per millisecond=14 )
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
[2023-03-18 09:21:22] [INFO ] Flatten gal took : 520 ms
[2023-03-18 09:21:23] [INFO ] Flatten gal took : 552 ms
[2023-03-18 09:21:24] [INFO ] Input system was already deterministic with 16400 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Drop transitions removed 7998 transitions
Trivial Post-agglo rules discarded 7998 transitions
Performed 7998 trivial Post agglomeration. Transition count delta: 7998
Iterating post reduction 0 with 7998 rules applied. Total rules applied 7998 place count 8841 transition count 8402
Reduce places removed 8036 places and 0 transitions.
Ensure Unique test removed 7400 transitions
Reduce isomorphic transitions removed 7400 transitions.
Iterating post reduction 1 with 15436 rules applied. Total rules applied 23434 place count 805 transition count 1002
Drop transitions removed 398 transitions
Redundant transition composition rules discarded 398 transitions
Iterating global reduction 2 with 398 rules applied. Total rules applied 23832 place count 805 transition count 604
Discarding 198 places :
Implicit places reduction removed 198 places
Drop transitions removed 396 transitions
Trivial Post-agglo rules discarded 396 transitions
Performed 396 trivial Post agglomeration. Transition count delta: 396
Iterating post reduction 2 with 594 rules applied. Total rules applied 24426 place count 607 transition count 208
Reduce places removed 594 places and 0 transitions.
Ensure Unique test removed 197 transitions
Reduce isomorphic transitions removed 197 transitions.
Iterating post reduction 3 with 791 rules applied. Total rules applied 25217 place count 13 transition count 11
Applied a total of 25217 rules in 249 ms. Remains 13 /8841 variables (removed 8828) and now considering 11/16400 (removed 16389) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 249 ms. Remains : 13/8841 places, 11/16400 transitions.
[2023-03-18 09:21:24] [INFO ] Flatten gal took : 1 ms
[2023-03-18 09:21:24] [INFO ] Flatten gal took : 0 ms
[2023-03-18 09:21:24] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Applied a total of 0 rules in 2778 ms. Remains 8841 /8841 variables (removed 0) and now considering 16400/16400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2787 ms. Remains : 8841/8841 places, 16400/16400 transitions.
[2023-03-18 09:21:27] [INFO ] Flatten gal took : 471 ms
[2023-03-18 09:21:28] [INFO ] Flatten gal took : 454 ms
[2023-03-18 09:21:29] [INFO ] Input system was already deterministic with 16400 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Drop transitions removed 7524 transitions
Trivial Post-agglo rules discarded 7524 transitions
Performed 7524 trivial Post agglomeration. Transition count delta: 7524
Iterating post reduction 0 with 7524 rules applied. Total rules applied 7524 place count 8841 transition count 8876
Reduce places removed 7524 places and 0 transitions.
Performed 76 Post agglomeration using F-continuation condition.Transition count delta: 76
Iterating post reduction 1 with 7600 rules applied. Total rules applied 15124 place count 1317 transition count 8800
Reduce places removed 114 places and 0 transitions.
Ensure Unique test removed 7400 transitions
Reduce isomorphic transitions removed 7400 transitions.
Iterating post reduction 2 with 7514 rules applied. Total rules applied 22638 place count 1203 transition count 1400
Applied a total of 22638 rules in 325 ms. Remains 1203 /8841 variables (removed 7638) and now considering 1400/16400 (removed 15000) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 326 ms. Remains : 1203/8841 places, 1400/16400 transitions.
[2023-03-18 09:21:29] [INFO ] Flatten gal took : 34 ms
[2023-03-18 09:21:29] [INFO ] Flatten gal took : 37 ms
[2023-03-18 09:21:29] [INFO ] Input system was already deterministic with 1400 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Drop transitions removed 7999 transitions
Trivial Post-agglo rules discarded 7999 transitions
Performed 7999 trivial Post agglomeration. Transition count delta: 7999
Iterating post reduction 0 with 7999 rules applied. Total rules applied 7999 place count 8841 transition count 8401
Reduce places removed 8038 places and 0 transitions.
Ensure Unique test removed 7600 transitions
Reduce isomorphic transitions removed 7600 transitions.
Iterating post reduction 1 with 15638 rules applied. Total rules applied 23637 place count 803 transition count 801
Drop transitions removed 199 transitions
Redundant transition composition rules discarded 199 transitions
Iterating global reduction 2 with 199 rules applied. Total rules applied 23836 place count 803 transition count 602
Discarding 199 places :
Implicit places reduction removed 199 places
Drop transitions removed 398 transitions
Trivial Post-agglo rules discarded 398 transitions
Performed 398 trivial Post agglomeration. Transition count delta: 398
Iterating post reduction 2 with 597 rules applied. Total rules applied 24433 place count 604 transition count 204
Reduce places removed 597 places and 0 transitions.
Ensure Unique test removed 198 transitions
Reduce isomorphic transitions removed 198 transitions.
Iterating post reduction 3 with 795 rules applied. Total rules applied 25228 place count 7 transition count 6
Applied a total of 25228 rules in 156 ms. Remains 7 /8841 variables (removed 8834) and now considering 6/16400 (removed 16394) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 157 ms. Remains : 7/8841 places, 6/16400 transitions.
[2023-03-18 09:21:29] [INFO ] Flatten gal took : 0 ms
[2023-03-18 09:21:29] [INFO ] Flatten gal took : 0 ms
[2023-03-18 09:21:29] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 8 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=8 )
FORMULA ServersAndClients-PT-200040-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Applied a total of 0 rules in 2391 ms. Remains 8841 /8841 variables (removed 0) and now considering 16400/16400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2398 ms. Remains : 8841/8841 places, 16400/16400 transitions.
[2023-03-18 09:21:32] [INFO ] Flatten gal took : 420 ms
[2023-03-18 09:21:33] [INFO ] Flatten gal took : 451 ms
[2023-03-18 09:21:33] [INFO ] Input system was already deterministic with 16400 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Drop transitions removed 7761 transitions
Trivial Post-agglo rules discarded 7761 transitions
Performed 7761 trivial Post agglomeration. Transition count delta: 7761
Iterating post reduction 0 with 7761 rules applied. Total rules applied 7761 place count 8841 transition count 8639
Reduce places removed 7761 places and 0 transitions.
Performed 39 Post agglomeration using F-continuation condition.Transition count delta: 39
Iterating post reduction 1 with 7800 rules applied. Total rules applied 15561 place count 1080 transition count 8600
Reduce places removed 78 places and 0 transitions.
Ensure Unique test removed 7600 transitions
Reduce isomorphic transitions removed 7600 transitions.
Iterating post reduction 2 with 7678 rules applied. Total rules applied 23239 place count 1002 transition count 1000
Applied a total of 23239 rules in 178 ms. Remains 1002 /8841 variables (removed 7839) and now considering 1000/16400 (removed 15400) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 178 ms. Remains : 1002/8841 places, 1000/16400 transitions.
[2023-03-18 09:21:34] [INFO ] Flatten gal took : 24 ms
[2023-03-18 09:21:34] [INFO ] Flatten gal took : 26 ms
[2023-03-18 09:21:34] [INFO ] Input system was already deterministic with 1000 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Applied a total of 0 rules in 2271 ms. Remains 8841 /8841 variables (removed 0) and now considering 16400/16400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2276 ms. Remains : 8841/8841 places, 16400/16400 transitions.
[2023-03-18 09:21:37] [INFO ] Flatten gal took : 404 ms
[2023-03-18 09:21:37] [INFO ] Flatten gal took : 681 ms
[2023-03-18 09:21:38] [INFO ] Input system was already deterministic with 16400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Applied a total of 0 rules in 2554 ms. Remains 8841 /8841 variables (removed 0) and now considering 16400/16400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2558 ms. Remains : 8841/8841 places, 16400/16400 transitions.
[2023-03-18 09:21:41] [INFO ] Flatten gal took : 397 ms
[2023-03-18 09:21:42] [INFO ] Flatten gal took : 448 ms
[2023-03-18 09:21:42] [INFO ] Input system was already deterministic with 16400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Applied a total of 0 rules in 2468 ms. Remains 8841 /8841 variables (removed 0) and now considering 16400/16400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2470 ms. Remains : 8841/8841 places, 16400/16400 transitions.
[2023-03-18 09:21:45] [INFO ] Flatten gal took : 399 ms
[2023-03-18 09:21:46] [INFO ] Flatten gal took : 448 ms
[2023-03-18 09:21:46] [INFO ] Input system was already deterministic with 16400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Applied a total of 0 rules in 2434 ms. Remains 8841 /8841 variables (removed 0) and now considering 16400/16400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2434 ms. Remains : 8841/8841 places, 16400/16400 transitions.
[2023-03-18 09:21:49] [INFO ] Flatten gal took : 399 ms
[2023-03-18 09:21:50] [INFO ] Flatten gal took : 446 ms
[2023-03-18 09:21:51] [INFO ] Input system was already deterministic with 16400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Applied a total of 0 rules in 2464 ms. Remains 8841 /8841 variables (removed 0) and now considering 16400/16400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2464 ms. Remains : 8841/8841 places, 16400/16400 transitions.
[2023-03-18 09:21:53] [INFO ] Flatten gal took : 402 ms
[2023-03-18 09:21:54] [INFO ] Flatten gal took : 446 ms
[2023-03-18 09:21:55] [INFO ] Input system was already deterministic with 16400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Applied a total of 0 rules in 2372 ms. Remains 8841 /8841 variables (removed 0) and now considering 16400/16400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2373 ms. Remains : 8841/8841 places, 16400/16400 transitions.
[2023-03-18 09:21:57] [INFO ] Flatten gal took : 393 ms
[2023-03-18 09:21:58] [INFO ] Flatten gal took : 446 ms
[2023-03-18 09:21:59] [INFO ] Input system was already deterministic with 16400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Applied a total of 0 rules in 2483 ms. Remains 8841 /8841 variables (removed 0) and now considering 16400/16400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2484 ms. Remains : 8841/8841 places, 16400/16400 transitions.
[2023-03-18 09:22:02] [INFO ] Flatten gal took : 419 ms
[2023-03-18 09:22:02] [INFO ] Flatten gal took : 468 ms
[2023-03-18 09:22:03] [INFO ] Input system was already deterministic with 16400 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Drop transitions removed 7999 transitions
Trivial Post-agglo rules discarded 7999 transitions
Performed 7999 trivial Post agglomeration. Transition count delta: 7999
Iterating post reduction 0 with 7999 rules applied. Total rules applied 7999 place count 8841 transition count 8401
Reduce places removed 8038 places and 0 transitions.
Ensure Unique test removed 7600 transitions
Reduce isomorphic transitions removed 7600 transitions.
Iterating post reduction 1 with 15638 rules applied. Total rules applied 23637 place count 803 transition count 801
Drop transitions removed 199 transitions
Redundant transition composition rules discarded 199 transitions
Iterating global reduction 2 with 199 rules applied. Total rules applied 23836 place count 803 transition count 602
Discarding 199 places :
Implicit places reduction removed 199 places
Drop transitions removed 398 transitions
Trivial Post-agglo rules discarded 398 transitions
Performed 398 trivial Post agglomeration. Transition count delta: 398
Iterating post reduction 2 with 597 rules applied. Total rules applied 24433 place count 604 transition count 204
Reduce places removed 597 places and 0 transitions.
Ensure Unique test removed 198 transitions
Reduce isomorphic transitions removed 198 transitions.
Iterating post reduction 3 with 795 rules applied. Total rules applied 25228 place count 7 transition count 6
Applied a total of 25228 rules in 135 ms. Remains 7 /8841 variables (removed 8834) and now considering 6/16400 (removed 16394) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 135 ms. Remains : 7/8841 places, 6/16400 transitions.
[2023-03-18 09:22:03] [INFO ] Flatten gal took : 1 ms
[2023-03-18 09:22:03] [INFO ] Flatten gal took : 0 ms
[2023-03-18 09:22:03] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Drop transitions removed 7761 transitions
Trivial Post-agglo rules discarded 7761 transitions
Performed 7761 trivial Post agglomeration. Transition count delta: 7761
Iterating post reduction 0 with 7761 rules applied. Total rules applied 7761 place count 8841 transition count 8639
Reduce places removed 7761 places and 0 transitions.
Performed 39 Post agglomeration using F-continuation condition.Transition count delta: 39
Iterating post reduction 1 with 7800 rules applied. Total rules applied 15561 place count 1080 transition count 8600
Reduce places removed 78 places and 0 transitions.
Ensure Unique test removed 7600 transitions
Reduce isomorphic transitions removed 7600 transitions.
Iterating post reduction 2 with 7678 rules applied. Total rules applied 23239 place count 1002 transition count 1000
Applied a total of 23239 rules in 169 ms. Remains 1002 /8841 variables (removed 7839) and now considering 1000/16400 (removed 15400) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 170 ms. Remains : 1002/8841 places, 1000/16400 transitions.
[2023-03-18 09:22:03] [INFO ] Flatten gal took : 25 ms
[2023-03-18 09:22:03] [INFO ] Flatten gal took : 28 ms
[2023-03-18 09:22:03] [INFO ] Input system was already deterministic with 1000 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8841/8841 places, 16400/16400 transitions.
Drop transitions removed 7999 transitions
Trivial Post-agglo rules discarded 7999 transitions
Performed 7999 trivial Post agglomeration. Transition count delta: 7999
Iterating post reduction 0 with 7999 rules applied. Total rules applied 7999 place count 8841 transition count 8401
Reduce places removed 8038 places and 0 transitions.
Ensure Unique test removed 7600 transitions
Reduce isomorphic transitions removed 7600 transitions.
Iterating post reduction 1 with 15638 rules applied. Total rules applied 23637 place count 803 transition count 801
Drop transitions removed 199 transitions
Redundant transition composition rules discarded 199 transitions
Iterating global reduction 2 with 199 rules applied. Total rules applied 23836 place count 803 transition count 602
Discarding 199 places :
Implicit places reduction removed 199 places
Drop transitions removed 398 transitions
Trivial Post-agglo rules discarded 398 transitions
Performed 398 trivial Post agglomeration. Transition count delta: 398
Iterating post reduction 2 with 597 rules applied. Total rules applied 24433 place count 604 transition count 204
Reduce places removed 597 places and 0 transitions.
Ensure Unique test removed 198 transitions
Reduce isomorphic transitions removed 198 transitions.
Iterating post reduction 3 with 795 rules applied. Total rules applied 25228 place count 7 transition count 6
Applied a total of 25228 rules in 126 ms. Remains 7 /8841 variables (removed 8834) and now considering 6/16400 (removed 16394) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 126 ms. Remains : 7/8841 places, 6/16400 transitions.
[2023-03-18 09:22:04] [INFO ] Flatten gal took : 0 ms
[2023-03-18 09:22:04] [INFO ] Flatten gal took : 0 ms
[2023-03-18 09:22:04] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-18 09:22:04] [INFO ] Flatten gal took : 453 ms
[2023-03-18 09:22:04] [INFO ] Flatten gal took : 467 ms
[2023-03-18 09:22:04] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-18 09:22:05] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8841 places, 16400 transitions and 49600 arcs took 101 ms.
Total runtime 82718 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ServersAndClients-PT-200040
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA ServersAndClients-PT-200040-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ServersAndClients-PT-200040-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679131553361

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 59 (type SKEL/FNDP) for 3 ServersAndClients-PT-200040-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SKEL/EQUN) for 3 ServersAndClients-PT-200040-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SKEL/SRCH) for 3 ServersAndClients-PT-200040-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type SKEL/SRCH) for 3 ServersAndClients-PT-200040-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: FINISHED task # 61 (type SKEL/SRCH) for ServersAndClients-PT-200040-CTLFireability-01
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 59 (type FNDP) for ServersAndClients-PT-200040-CTLFireability-01 (obsolete)
lola: CANCELED task # 60 (type EQUN) for ServersAndClients-PT-200040-CTLFireability-01 (obsolete)
lola: CANCELED task # 62 (type SRCH) for ServersAndClients-PT-200040-CTLFireability-01 (obsolete)
lola: FINISHED task # 59 (type SKEL/FNDP) for ServersAndClients-PT-200040-CTLFireability-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/375/CTLFireability-60.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 60 (type SKEL/EQUN) for ServersAndClients-PT-200040-CTLFireability-01
lola: result : true
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 63 (type SKEL/SRCH) for 35 ServersAndClients-PT-200040-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 63 (type SKEL/SRCH) for ServersAndClients-PT-200040-CTLFireability-10
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 64 (type SKEL/SRCH) for 3 ServersAndClients-PT-200040-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type SKEL/SRCH) for ServersAndClients-PT-200040-CTLFireability-01
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ServersAndClients-PT-200040-CTLFireability-00: ER 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-01: DISJ 0 0 0 0 5 0 0 1
ServersAndClients-PT-200040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
ServersAndClients-PT-200040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
ServersAndClients-PT-200040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
ServersAndClients-PT-200040-CTLFireability-13: EG 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-14: EG 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-15: AGAF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 155 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 15
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 65 (type EXCL) for 54 ServersAndClients-PT-200040-CTLFireability-15
lola: time limit : 202 sec
lola: memory limit: 32 pages
lola: FINISHED task # 65 (type EXCL) for ServersAndClients-PT-200040-CTLFireability-15
lola: result : false
lola: markings : 402
lola: fired transitions : 801
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 ServersAndClients-PT-200040-CTLFireability-13
lola: time limit : 215 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for ServersAndClients-PT-200040-CTLFireability-13
lola: result : true
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:736
lola: rewrite Frontend/Parser/formula_rewrite.k:696
lola: LAUNCH task # 1 (type EXCL) for 0 ServersAndClients-PT-200040-CTLFireability-00
lola: time limit : 229 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for ServersAndClients-PT-200040-CTLFireability-00
lola: result : true
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 21 (type EXCL) for 20 ServersAndClients-PT-200040-CTLFireability-05
lola: time limit : 245 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-200040-CTLFireability-00: ER true state space /ER
ServersAndClients-PT-200040-CTLFireability-13: EG true state space / EG
ServersAndClients-PT-200040-CTLFireability-15: AGAF true state space /EFEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ServersAndClients-PT-200040-CTLFireability-01: DISJ 0 0 0 0 5 0 0 1
ServersAndClients-PT-200040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-10: DISJ 0 0 0 0 3 0 0 0
ServersAndClients-PT-200040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-14: EG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 0/245 0/32 ServersAndClients-PT-200040-CTLFireability-05 --

Time elapsed: 160 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 15
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 67 (type FNDP) for 3 ServersAndClients-PT-200040-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type EQUN) for 3 ServersAndClients-PT-200040-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type SRCH) for 3 ServersAndClients-PT-200040-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 70 (type SRCH) for ServersAndClients-PT-200040-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 67 (type FNDP) for ServersAndClients-PT-200040-CTLFireability-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 68 (type EQUN) for ServersAndClients-PT-200040-CTLFireability-01 (obsolete)
lola: FINISHED task # 21 (type EXCL) for ServersAndClients-PT-200040-CTLFireability-05
lola: result : false
lola: markings : 601
lola: fired transitions : 2804
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 51 ServersAndClients-PT-200040-CTLFireability-14
lola: time limit : 312 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/375/CTLFireability-68.sara.
lola: FINISHED task # 52 (type EXCL) for ServersAndClients-PT-200040-CTLFireability-14
lola: result : true
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 15 (type EXCL) for 14 ServersAndClients-PT-200040-CTLFireability-02
lola: time limit : 343 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for ServersAndClients-PT-200040-CTLFireability-02
lola: result : false
lola: markings : 234
lola: fired transitions : 415
lola: time used : 0.000000
lola: memory pages used : 1

lola: FINISHED task # 68 (type EQUN) for ServersAndClients-PT-200040-CTLFireability-01
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 6 (type EXCL) for 3 ServersAndClients-PT-200040-CTLFireability-01
lola: time limit : 382 sec
lola: memory limit: 32 pages
lola: FINISHED task # 6 (type EXCL) for ServersAndClients-PT-200040-CTLFireability-01
lola: result : false
lola: markings : 801
lola: fired transitions : 3047
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-200040-CTLFireability-00: ER true state space /ER
ServersAndClients-PT-200040-CTLFireability-01: DISJ false DISJ
ServersAndClients-PT-200040-CTLFireability-02: CTL false CTL model checker
ServersAndClients-PT-200040-CTLFireability-05: CTL false CTL model checker
ServersAndClients-PT-200040-CTLFireability-13: EG true state space / EG
ServersAndClients-PT-200040-CTLFireability-14: EG true state space / EG
ServersAndClients-PT-200040-CTLFireability-15: AGAF true state space /EFEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ServersAndClients-PT-200040-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-10: DISJ 0 0 0 0 3 0 0 0
ServersAndClients-PT-200040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-200040-CTLFireability-12: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-200040-CTLFireability-00: ER true state space /ER
ServersAndClients-PT-200040-CTLFireability-01: DISJ false DISJ
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-200040-CTLFireability-00: ER true state space /ER
ServersAndClients-PT-200040-CTLFireability-01: DISJ false DISJ
ServersAndClients-PT-200040-CTLFireability-02: CTL false CTL model checker
ServersAndClients-PT-200040-CTLFireability-04: CTL false CTL model checker
ServersAndClients-PT-200040-CTLFireability-05: CTL false CTL model checker
ServersAndClients-PT-200040-CTLFireability-06: CTL false CTL model checker
ServersAndClients-PT-200040-CTLFireability-07: CTL true CTL model checker
ServersAndClients-PT-200040-CTLFireability-08: CTL true CTL model checker
ServersAndClients-PT-200040-CTLFireability-09: CTL true CTL model checker
ServersAndClients-PT-200040-CTLFireability-10: DISJ false DISJ
ServersAndClients-PT-200040-CTLFireability-11: CTL false CTL model checker
ServersAndClients-PT-200040-CTLFireability-12: CTL false CTL model checker
ServersAndClients-PT-200040-CTLFireability-13: EG true state space / EG
ServersAndClients-PT-200040-CTLFireability-14: EG true state space / EG
ServersAndClients-PT-200040-CTLFireability-15: AGAF true state space /EFEG


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ServersAndClients-PT-200040"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ServersAndClients-PT-200040, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891809100498"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ServersAndClients-PT-200040.tgz
mv ServersAndClients-PT-200040 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;