About the Execution of LoLa+red for ServersAndClients-PT-100080
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 14381.836 | 438753.00 | 724454.00 | 1503.70 | FTTFTFFFFTTFFFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r359-smll-167891809000474.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ServersAndClients-PT-100080, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891809000474
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.4M
-rw-r--r-- 1 mcc users 7.6K Feb 26 03:44 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 26 03:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 26 03:42 CTLFireability.txt
-rw-r--r-- 1 mcc users 61K Feb 26 03:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.5K Feb 25 16:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Feb 25 16:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Feb 25 16:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 03:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 116K Feb 26 03:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 26 03:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 115K Feb 26 03:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.9M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-00
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-01
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-02
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-03
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-04
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-05
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-06
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-07
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-08
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-09
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-10
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-11
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-12
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-13
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-14
FORMULA_NAME ServersAndClients-PT-100080-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679119285065
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ServersAndClients-PT-100080
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-18 06:01:28] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-18 06:01:28] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-18 06:01:29] [INFO ] Load time of PNML (sax parser for PT used): 822 ms
[2023-03-18 06:01:29] [INFO ] Transformed 8481 places.
[2023-03-18 06:01:29] [INFO ] Transformed 16200 transitions.
[2023-03-18 06:01:29] [INFO ] Parsed PT model containing 8481 places and 16200 transitions and 48800 arcs in 1071 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 43 ms.
Support contains 175 out of 8481 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2777 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
// Phase 1: matrix 16200 rows 8481 cols
[2023-03-18 06:01:33] [INFO ] Computed 281 place invariants in 417 ms
[2023-03-18 06:01:35] [INFO ] Implicit Places using invariants in 2483 ms returned []
Implicit Place search using SMT only with invariants took 2526 ms to find 0 implicit places.
[2023-03-18 06:01:35] [INFO ] Invariant cache hit.
[2023-03-18 06:01:36] [INFO ] Dead Transitions using invariants and state equation in 1651 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6966 ms. Remains : 8481/8481 places, 16200/16200 transitions.
Support contains 175 out of 8481 places after structural reductions.
[2023-03-18 06:01:38] [INFO ] Flatten gal took : 1141 ms
[2023-03-18 06:01:39] [INFO ] Flatten gal took : 615 ms
[2023-03-18 06:01:40] [INFO ] Input system was already deterministic with 16200 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1078 ms. (steps per millisecond=9 ) properties (out of 102) seen :65
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 37) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :0
Running SMT prover for 35 properties.
[2023-03-18 06:01:42] [INFO ] Invariant cache hit.
[2023-03-18 06:01:51] [INFO ] [Real]Absence check using 181 positive place invariants in 741 ms returned sat
[2023-03-18 06:01:52] [INFO ] [Real]Absence check using 181 positive and 100 generalized place invariants in 176 ms returned sat
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:631)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-18 06:02:07] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-18 06:02:07] [INFO ] After 25031ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 35 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 1 ms.
Support contains 30 out of 8481 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Drop transitions removed 7794 transitions
Trivial Post-agglo rules discarded 7794 transitions
Performed 7794 trivial Post agglomeration. Transition count delta: 7794
Iterating post reduction 0 with 7794 rules applied. Total rules applied 7794 place count 8481 transition count 8406
Reduce places removed 7794 places and 0 transitions.
Performed 79 Post agglomeration using F-continuation condition.Transition count delta: 79
Iterating post reduction 1 with 7873 rules applied. Total rules applied 15667 place count 687 transition count 8327
Reduce places removed 134 places and 0 transitions.
Ensure Unique test removed 5400 transitions
Reduce isomorphic transitions removed 5400 transitions.
Iterating post reduction 2 with 5534 rules applied. Total rules applied 21201 place count 553 transition count 2927
Drop transitions removed 2373 transitions
Redundant transition composition rules discarded 2373 transitions
Iterating global reduction 3 with 2373 rules applied. Total rules applied 23574 place count 553 transition count 554
Partial Free-agglomeration rule applied 99 times.
Drop transitions removed 99 transitions
Iterating global reduction 3 with 99 rules applied. Total rules applied 23673 place count 553 transition count 554
Applied a total of 23673 rules in 1114 ms. Remains 553 /8481 variables (removed 7928) and now considering 554/16200 (removed 15646) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1116 ms. Remains : 553/8481 places, 554/16200 transitions.
Finished random walk after 2354 steps, including 0 resets, run visited all 27 properties in 157 ms. (steps per millisecond=14 )
Successfully simplified 8 atomic propositions for a total of 16 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA ServersAndClients-PT-100080-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-18 06:02:09] [INFO ] Flatten gal took : 651 ms
[2023-03-18 06:02:09] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA ServersAndClients-PT-100080-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-18 06:02:09] [INFO ] Flatten gal took : 514 ms
[2023-03-18 06:02:10] [INFO ] Input system was already deterministic with 16200 transitions.
Support contains 132 out of 8481 places (down from 135) after GAL structural reductions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2187 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2192 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:13] [INFO ] Flatten gal took : 455 ms
[2023-03-18 06:02:14] [INFO ] Flatten gal took : 517 ms
[2023-03-18 06:02:15] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2417 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2419 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:18] [INFO ] Flatten gal took : 450 ms
[2023-03-18 06:02:18] [INFO ] Flatten gal took : 498 ms
[2023-03-18 06:02:19] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2353 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2354 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:22] [INFO ] Flatten gal took : 429 ms
[2023-03-18 06:02:22] [INFO ] Flatten gal took : 459 ms
[2023-03-18 06:02:23] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2431 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2433 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:26] [INFO ] Flatten gal took : 414 ms
[2023-03-18 06:02:27] [INFO ] Flatten gal took : 440 ms
[2023-03-18 06:02:27] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2139 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2145 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:30] [INFO ] Flatten gal took : 411 ms
[2023-03-18 06:02:30] [INFO ] Flatten gal took : 450 ms
[2023-03-18 06:02:31] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Drop transitions removed 7819 transitions
Trivial Post-agglo rules discarded 7819 transitions
Performed 7819 trivial Post agglomeration. Transition count delta: 7819
Iterating post reduction 0 with 7819 rules applied. Total rules applied 7819 place count 8481 transition count 8381
Reduce places removed 7819 places and 0 transitions.
Performed 79 Post agglomeration using F-continuation condition.Transition count delta: 79
Iterating post reduction 1 with 7898 rules applied. Total rules applied 15717 place count 662 transition count 8302
Reduce places removed 156 places and 0 transitions.
Ensure Unique test removed 7600 transitions
Reduce isomorphic transitions removed 7600 transitions.
Iterating post reduction 2 with 7756 rules applied. Total rules applied 23473 place count 506 transition count 702
Drop transitions removed 198 transitions
Redundant transition composition rules discarded 198 transitions
Iterating global reduction 3 with 198 rules applied. Total rules applied 23671 place count 506 transition count 504
Applied a total of 23671 rules in 231 ms. Remains 506 /8481 variables (removed 7975) and now considering 504/16200 (removed 15696) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 232 ms. Remains : 506/8481 places, 504/16200 transitions.
[2023-03-18 06:02:31] [INFO ] Flatten gal took : 12 ms
[2023-03-18 06:02:31] [INFO ] Flatten gal took : 13 ms
[2023-03-18 06:02:31] [INFO ] Input system was already deterministic with 504 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Drop transitions removed 7467 transitions
Trivial Post-agglo rules discarded 7467 transitions
Performed 7467 trivial Post agglomeration. Transition count delta: 7467
Iterating post reduction 0 with 7467 rules applied. Total rules applied 7467 place count 8481 transition count 8733
Reduce places removed 7467 places and 0 transitions.
Performed 231 Post agglomeration using F-continuation condition.Transition count delta: 231
Iterating post reduction 1 with 7698 rules applied. Total rules applied 15165 place count 1014 transition count 8502
Reduce places removed 306 places and 0 transitions.
Ensure Unique test removed 7400 transitions
Reduce isomorphic transitions removed 7400 transitions.
Iterating post reduction 2 with 7706 rules applied. Total rules applied 22871 place count 708 transition count 1102
Drop transitions removed 198 transitions
Redundant transition composition rules discarded 198 transitions
Iterating global reduction 3 with 198 rules applied. Total rules applied 23069 place count 708 transition count 904
Applied a total of 23069 rules in 332 ms. Remains 708 /8481 variables (removed 7773) and now considering 904/16200 (removed 15296) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 332 ms. Remains : 708/8481 places, 904/16200 transitions.
[2023-03-18 06:02:32] [INFO ] Flatten gal took : 32 ms
[2023-03-18 06:02:32] [INFO ] Flatten gal took : 35 ms
[2023-03-18 06:02:32] [INFO ] Input system was already deterministic with 904 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2273 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2278 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:35] [INFO ] Flatten gal took : 411 ms
[2023-03-18 06:02:35] [INFO ] Flatten gal took : 459 ms
[2023-03-18 06:02:36] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2206 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2207 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:39] [INFO ] Flatten gal took : 417 ms
[2023-03-18 06:02:39] [INFO ] Flatten gal took : 449 ms
[2023-03-18 06:02:40] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2196 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2198 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:42] [INFO ] Flatten gal took : 397 ms
[2023-03-18 06:02:43] [INFO ] Flatten gal took : 449 ms
[2023-03-18 06:02:44] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2178 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2182 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:46] [INFO ] Flatten gal took : 398 ms
[2023-03-18 06:02:47] [INFO ] Flatten gal took : 449 ms
[2023-03-18 06:02:48] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2168 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2172 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:50] [INFO ] Flatten gal took : 403 ms
[2023-03-18 06:02:51] [INFO ] Flatten gal took : 446 ms
[2023-03-18 06:02:51] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Applied a total of 0 rules in 2153 ms. Remains 8481 /8481 variables (removed 0) and now considering 16200/16200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2153 ms. Remains : 8481/8481 places, 16200/16200 transitions.
[2023-03-18 06:02:54] [INFO ] Flatten gal took : 402 ms
[2023-03-18 06:02:54] [INFO ] Flatten gal took : 428 ms
[2023-03-18 06:02:55] [INFO ] Input system was already deterministic with 16200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8481/8481 places, 16200/16200 transitions.
Drop transitions removed 7637 transitions
Trivial Post-agglo rules discarded 7637 transitions
Performed 7637 trivial Post agglomeration. Transition count delta: 7637
Iterating post reduction 0 with 7637 rules applied. Total rules applied 7637 place count 8481 transition count 8563
Reduce places removed 7637 places and 0 transitions.
Performed 155 Post agglomeration using F-continuation condition.Transition count delta: 155
Iterating post reduction 1 with 7792 rules applied. Total rules applied 15429 place count 844 transition count 8408
Reduce places removed 225 places and 0 transitions.
Ensure Unique test removed 6900 transitions
Reduce isomorphic transitions removed 6900 transitions.
Iterating post reduction 2 with 7125 rules applied. Total rules applied 22554 place count 619 transition count 1508
Drop transitions removed 792 transitions
Redundant transition composition rules discarded 792 transitions
Iterating global reduction 3 with 792 rules applied. Total rules applied 23346 place count 619 transition count 716
Applied a total of 23346 rules in 178 ms. Remains 619 /8481 variables (removed 7862) and now considering 716/16200 (removed 15484) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 178 ms. Remains : 619/8481 places, 716/16200 transitions.
[2023-03-18 06:02:55] [INFO ] Flatten gal took : 16 ms
[2023-03-18 06:02:55] [INFO ] Flatten gal took : 18 ms
[2023-03-18 06:02:55] [INFO ] Input system was already deterministic with 716 transitions.
[2023-03-18 06:02:56] [INFO ] Flatten gal took : 430 ms
[2023-03-18 06:02:56] [INFO ] Flatten gal took : 451 ms
[2023-03-18 06:02:56] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-18 06:02:56] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8481 places, 16200 transitions and 48800 arcs took 84 ms.
Total runtime 88460 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ServersAndClients-PT-100080
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA ServersAndClients-PT-100080-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100080-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679119723818
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: LAUNCH task # 50 (type SKEL/SRCH) for 6 ServersAndClients-PT-100080-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Rule S: 0 transitions removed,0 places removed
lola: FINISHED task # 50 (type SKEL/SRCH) for ServersAndClients-PT-100080-CTLFireability-02
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 51 (type SKEL/SRCH) for 6 ServersAndClients-PT-100080-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 51 (type SKEL/SRCH) for ServersAndClients-PT-100080-CTLFireability-02
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ServersAndClients-PT-100080-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-100080-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-100080-CTLFireability-02: CONJ 0 0 0 0 3 0 0 0
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ServersAndClients-PT-100080-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
ServersAndClients-PT-100080-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 248 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 14
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 9 (type EXCL) for 6 ServersAndClients-PT-100080-CTLFireability-02
lola: time limit : 209 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-02
lola: result : true
lola: markings : 3
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 27 (type EXCL) for 26 ServersAndClients-PT-100080-CTLFireability-07
lola: time limit : 223 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-07
lola: result : false
lola: markings : 21
lola: fired transitions : 47
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 24 (type EXCL) for 23 ServersAndClients-PT-100080-CTLFireability-05
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-05
lola: result : false
lola: markings : 190
lola: fired transitions : 636
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-100080-CTLFireability-05: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-07: CTL false CTL model checker
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ServersAndClients-PT-100080-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-100080-CTLFireability-15: CTL 1 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 253 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 14
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 48 (type EXCL) for 47 ServersAndClients-PT-100080-CTLFireability-15
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-15
lola: result : true
lola: markings : 47
lola: fired transitions : 166
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-100080-CTLFireability-05: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-07: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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lola: time used : 2.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 20 ServersAndClients-PT-100080-CTLFireability-04
lola: time limit : 363 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 21 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-04
lola: result : true
lola: markings : 4322
lola: fired transitions : 12856
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 17 ServersAndClients-PT-100080-CTLFireability-03
lola: time limit : 408 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-03
lola: result : false
lola: markings : 301
lola: fired transitions : 1304
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 15 (type EXCL) for 6 ServersAndClients-PT-100080-CTLFireability-02
lola: time limit : 466 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-02
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 ServersAndClients-PT-100080-CTLFireability-01
lola: time limit : 653 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-100080-CTLFireability-02: CONJ true CONJ
ServersAndClients-PT-100080-CTLFireability-03: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-04: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-05: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-07: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-09: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-12: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-14: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ServersAndClients-PT-100080-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-100080-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ServersAndClients-PT-100080-CTLFireability-08: CTL 1 0 0 0 1 0 0 0
ServersAndClients-PT-100080-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
ServersAndClients-PT-100080-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 0/653 1/32 ServersAndClients-PT-100080-CTLFireability-01 1977 m, 395 m/sec, 3903 t fired, .
Time elapsed: 333 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 14
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 4 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-01
lola: result : true
lola: markings : 7014
lola: fired transitions : 14115
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 ServersAndClients-PT-100080-CTLFireability-08
lola: time limit : 816 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 30 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-08
lola: result : false
lola: markings : 8201
lola: fired transitions : 65404
lola: time used : 4.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 ServersAndClients-PT-100080-CTLFireability-13
lola: time limit : 1087 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-13
lola: result : false
lola: markings : 4
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 ServersAndClients-PT-100080-CTLFireability-11
lola: time limit : 1631 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-100080-CTLFireability-01: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-02: CONJ true CONJ
ServersAndClients-PT-100080-CTLFireability-03: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-04: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-05: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-07: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-08: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-09: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-12: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-13: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-14: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ServersAndClients-PT-100080-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ServersAndClients-PT-100080-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 0/1631 1/32 ServersAndClients-PT-100080-CTLFireability-11 557 m, 111 m/sec, 1652 t fired, .
Time elapsed: 338 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 36 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-11
lola: result : false
lola: markings : 8201
lola: fired transitions : 24501
lola: time used : 2.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 ServersAndClients-PT-100080-CTLFireability-00
lola: time limit : 3260 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-100080-CTLFireability-01: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-02: CONJ true CONJ
ServersAndClients-PT-100080-CTLFireability-03: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-04: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-05: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-07: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-08: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-09: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-11: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-12: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-13: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-14: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ServersAndClients-PT-100080-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 3/3260 1/32 ServersAndClients-PT-100080-CTLFireability-00 8201 m, 1640 m/sec, 55806 t fired, .
Time elapsed: 343 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 1 (type EXCL) for ServersAndClients-PT-100080-CTLFireability-00
lola: result : false
lola: markings : 8201
lola: fired transitions : 81486
lola: time used : 5.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-100080-CTLFireability-00: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-01: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-02: CONJ true CONJ
ServersAndClients-PT-100080-CTLFireability-03: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-04: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-05: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-07: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-08: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-09: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-11: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-12: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-13: CTL false CTL model checker
ServersAndClients-PT-100080-CTLFireability-14: CTL true CTL model checker
ServersAndClients-PT-100080-CTLFireability-15: CTL true CTL model checker
Time elapsed: 345 secs. Pages in use: 1
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ServersAndClients-PT-100080"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ServersAndClients-PT-100080, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891809000474"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ServersAndClients-PT-100080.tgz
mv ServersAndClients-PT-100080 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;