About the Execution of LoLa+red for ServersAndClients-PT-100040
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5503.327 | 170016.00 | 262656.00 | 913.90 | TTFTFTTFTTTFTTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r359-smll-167891809000466.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ServersAndClients-PT-100040, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891809000466
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.0M
-rw-r--r-- 1 mcc users 7.5K Feb 26 03:38 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 26 03:38 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Feb 26 03:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K Feb 26 03:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 16:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 03:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 104K Feb 26 03:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 03:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 86K Feb 26 03:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 2.5M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-00
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-01
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-02
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-03
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-04
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-05
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-06
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-07
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-08
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-09
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-10
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-11
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-12
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-13
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-14
FORMULA_NAME ServersAndClients-PT-100040-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679118134272
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ServersAndClients-PT-100040
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-18 05:42:17] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-18 05:42:17] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-18 05:42:18] [INFO ] Load time of PNML (sax parser for PT used): 694 ms
[2023-03-18 05:42:18] [INFO ] Transformed 4441 places.
[2023-03-18 05:42:18] [INFO ] Transformed 8200 transitions.
[2023-03-18 05:42:18] [INFO ] Parsed PT model containing 4441 places and 8200 transitions and 24800 arcs in 994 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 28 ms.
Support contains 138 out of 4441 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 1076 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
// Phase 1: matrix 8200 rows 4441 cols
[2023-03-18 05:42:19] [INFO ] Computed 241 place invariants in 204 ms
[2023-03-18 05:42:22] [INFO ] Implicit Places using invariants in 2296 ms returned []
[2023-03-18 05:42:22] [INFO ] Invariant cache hit.
[2023-03-18 05:42:23] [INFO ] Implicit Places using invariants and state equation in 1565 ms returned []
Implicit Place search using SMT with State Equation took 3910 ms to find 0 implicit places.
[2023-03-18 05:42:23] [INFO ] Invariant cache hit.
[2023-03-18 05:42:24] [INFO ] Dead Transitions using invariants and state equation in 941 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5938 ms. Remains : 4441/4441 places, 8200/8200 transitions.
Support contains 138 out of 4441 places after structural reductions.
[2023-03-18 05:42:25] [INFO ] Flatten gal took : 766 ms
[2023-03-18 05:42:26] [INFO ] Flatten gal took : 360 ms
[2023-03-18 05:42:26] [INFO ] Input system was already deterministic with 8200 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1021 ms. (steps per millisecond=9 ) properties (out of 95) seen :71
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 24) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 23) seen :0
Running SMT prover for 23 properties.
[2023-03-18 05:42:28] [INFO ] Invariant cache hit.
[2023-03-18 05:42:31] [INFO ] [Real]Absence check using 141 positive place invariants in 378 ms returned sat
[2023-03-18 05:42:32] [INFO ] [Real]Absence check using 141 positive and 100 generalized place invariants in 83 ms returned sat
[2023-03-18 05:42:44] [INFO ] After 10600ms SMT Verify possible using state equation in real domain returned unsat :8 sat :13 real:2
[2023-03-18 05:42:52] [INFO ] After 18443ms SMT Verify possible using trap constraints in real domain returned unsat :8 sat :13 real:2
Attempting to minimize the solution found.
Minimization took 1437 ms.
[2023-03-18 05:42:53] [INFO ] After 25081ms SMT Verify possible using all constraints in real domain returned unsat :8 sat :13 real:2
[2023-03-18 05:42:56] [INFO ] [Nat]Absence check using 141 positive place invariants in 422 ms returned sat
[2023-03-18 05:42:56] [INFO ] [Nat]Absence check using 141 positive and 100 generalized place invariants in 124 ms returned sat
[2023-03-18 05:43:09] [INFO ] After 12156ms SMT Verify possible using state equation in natural domain returned unsat :10 sat :13
[2023-03-18 05:43:18] [INFO ] After 20706ms SMT Verify possible using trap constraints in natural domain returned unsat :10 sat :13
Attempting to minimize the solution found.
Minimization took 405 ms.
[2023-03-18 05:43:18] [INFO ] After 25059ms SMT Verify possible using all constraints in natural domain returned unsat :10 sat :13
Fused 23 Parikh solutions to 13 different solutions.
Finished Parikh walk after 10 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=10 )
Parikh walk visited 13 properties in 79 ms.
Successfully simplified 10 atomic propositions for a total of 16 simplifications.
[2023-03-18 05:43:19] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-18 05:43:19] [INFO ] Flatten gal took : 265 ms
FORMULA ServersAndClients-PT-100040-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-18 05:43:19] [INFO ] Flatten gal took : 293 ms
[2023-03-18 05:43:19] [INFO ] Input system was already deterministic with 8200 transitions.
Support contains 111 out of 4441 places (down from 115) after GAL structural reductions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Drop transitions removed 3999 transitions
Trivial Post-agglo rules discarded 3999 transitions
Performed 3999 trivial Post agglomeration. Transition count delta: 3999
Iterating post reduction 0 with 3999 rules applied. Total rules applied 3999 place count 4441 transition count 4201
Reduce places removed 4038 places and 0 transitions.
Ensure Unique test removed 3800 transitions
Reduce isomorphic transitions removed 3800 transitions.
Iterating post reduction 1 with 7838 rules applied. Total rules applied 11837 place count 403 transition count 401
Drop transitions removed 99 transitions
Redundant transition composition rules discarded 99 transitions
Iterating global reduction 2 with 99 rules applied. Total rules applied 11936 place count 403 transition count 302
Discarding 99 places :
Implicit places reduction removed 99 places
Drop transitions removed 198 transitions
Trivial Post-agglo rules discarded 198 transitions
Performed 198 trivial Post agglomeration. Transition count delta: 198
Iterating post reduction 2 with 297 rules applied. Total rules applied 12233 place count 304 transition count 104
Reduce places removed 297 places and 0 transitions.
Ensure Unique test removed 98 transitions
Reduce isomorphic transitions removed 98 transitions.
Iterating post reduction 3 with 395 rules applied. Total rules applied 12628 place count 7 transition count 6
Applied a total of 12628 rules in 129 ms. Remains 7 /4441 variables (removed 4434) and now considering 6/8200 (removed 8194) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 130 ms. Remains : 7/4441 places, 6/8200 transitions.
[2023-03-18 05:43:20] [INFO ] Flatten gal took : 1 ms
[2023-03-18 05:43:20] [INFO ] Flatten gal took : 0 ms
[2023-03-18 05:43:20] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 5 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=5 )
FORMULA ServersAndClients-PT-100040-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 683 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 687 ms. Remains : 4441/4441 places, 8200/8200 transitions.
[2023-03-18 05:43:21] [INFO ] Flatten gal took : 228 ms
[2023-03-18 05:43:21] [INFO ] Flatten gal took : 239 ms
[2023-03-18 05:43:21] [INFO ] Input system was already deterministic with 8200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Drop transitions removed 3194 transitions
Trivial Post-agglo rules discarded 3194 transitions
Performed 3194 trivial Post agglomeration. Transition count delta: 3194
Iterating post reduction 0 with 3194 rules applied. Total rules applied 3194 place count 4441 transition count 5006
Reduce places removed 3194 places and 0 transitions.
Performed 204 Post agglomeration using F-continuation condition.Transition count delta: 204
Iterating post reduction 1 with 3398 rules applied. Total rules applied 6592 place count 1247 transition count 4802
Reduce places removed 236 places and 0 transitions.
Ensure Unique test removed 3100 transitions
Reduce isomorphic transitions removed 3100 transitions.
Iterating post reduction 2 with 3336 rules applied. Total rules applied 9928 place count 1011 transition count 1702
Drop transitions removed 198 transitions
Redundant transition composition rules discarded 198 transitions
Iterating global reduction 3 with 198 rules applied. Total rules applied 10126 place count 1011 transition count 1504
Applied a total of 10126 rules in 359 ms. Remains 1011 /4441 variables (removed 3430) and now considering 1504/8200 (removed 6696) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 360 ms. Remains : 1011/4441 places, 1504/8200 transitions.
[2023-03-18 05:43:22] [INFO ] Flatten gal took : 37 ms
[2023-03-18 05:43:22] [INFO ] Flatten gal took : 41 ms
[2023-03-18 05:43:22] [INFO ] Input system was already deterministic with 1504 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 692 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 696 ms. Remains : 4441/4441 places, 8200/8200 transitions.
[2023-03-18 05:43:23] [INFO ] Flatten gal took : 207 ms
[2023-03-18 05:43:23] [INFO ] Flatten gal took : 221 ms
[2023-03-18 05:43:23] [INFO ] Input system was already deterministic with 8200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 614 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 618 ms. Remains : 4441/4441 places, 8200/8200 transitions.
[2023-03-18 05:43:24] [INFO ] Flatten gal took : 222 ms
[2023-03-18 05:43:25] [INFO ] Flatten gal took : 233 ms
[2023-03-18 05:43:25] [INFO ] Input system was already deterministic with 8200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 604 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 605 ms. Remains : 4441/4441 places, 8200/8200 transitions.
[2023-03-18 05:43:26] [INFO ] Flatten gal took : 221 ms
[2023-03-18 05:43:26] [INFO ] Flatten gal took : 235 ms
[2023-03-18 05:43:26] [INFO ] Input system was already deterministic with 8200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 683 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 684 ms. Remains : 4441/4441 places, 8200/8200 transitions.
[2023-03-18 05:43:27] [INFO ] Flatten gal took : 208 ms
[2023-03-18 05:43:28] [INFO ] Flatten gal took : 225 ms
[2023-03-18 05:43:28] [INFO ] Input system was already deterministic with 8200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 593 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 598 ms. Remains : 4441/4441 places, 8200/8200 transitions.
[2023-03-18 05:43:29] [INFO ] Flatten gal took : 197 ms
[2023-03-18 05:43:29] [INFO ] Flatten gal took : 217 ms
[2023-03-18 05:43:29] [INFO ] Input system was already deterministic with 8200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 593 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 594 ms. Remains : 4441/4441 places, 8200/8200 transitions.
[2023-03-18 05:43:30] [INFO ] Flatten gal took : 197 ms
[2023-03-18 05:43:30] [INFO ] Flatten gal took : 222 ms
[2023-03-18 05:43:31] [INFO ] Input system was already deterministic with 8200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 596 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 596 ms. Remains : 4441/4441 places, 8200/8200 transitions.
[2023-03-18 05:43:32] [INFO ] Flatten gal took : 195 ms
[2023-03-18 05:43:32] [INFO ] Flatten gal took : 216 ms
[2023-03-18 05:43:32] [INFO ] Input system was already deterministic with 8200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Drop transitions removed 3856 transitions
Trivial Post-agglo rules discarded 3856 transitions
Performed 3856 trivial Post agglomeration. Transition count delta: 3856
Iterating post reduction 0 with 3856 rules applied. Total rules applied 3856 place count 4441 transition count 4344
Reduce places removed 3856 places and 0 transitions.
Performed 39 Post agglomeration using F-continuation condition.Transition count delta: 39
Iterating post reduction 1 with 3895 rules applied. Total rules applied 7751 place count 585 transition count 4305
Reduce places removed 73 places and 0 transitions.
Ensure Unique test removed 3300 transitions
Reduce isomorphic transitions removed 3300 transitions.
Iterating post reduction 2 with 3373 rules applied. Total rules applied 11124 place count 512 transition count 1005
Drop transitions removed 495 transitions
Redundant transition composition rules discarded 495 transitions
Iterating global reduction 3 with 495 rules applied. Total rules applied 11619 place count 512 transition count 510
Applied a total of 11619 rules in 114 ms. Remains 512 /4441 variables (removed 3929) and now considering 510/8200 (removed 7690) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 115 ms. Remains : 512/4441 places, 510/8200 transitions.
[2023-03-18 05:43:32] [INFO ] Flatten gal took : 12 ms
[2023-03-18 05:43:32] [INFO ] Flatten gal took : 13 ms
[2023-03-18 05:43:32] [INFO ] Input system was already deterministic with 510 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 596 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 596 ms. Remains : 4441/4441 places, 8200/8200 transitions.
[2023-03-18 05:43:33] [INFO ] Flatten gal took : 197 ms
[2023-03-18 05:43:33] [INFO ] Flatten gal took : 229 ms
[2023-03-18 05:43:34] [INFO ] Input system was already deterministic with 8200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Drop transitions removed 3454 transitions
Trivial Post-agglo rules discarded 3454 transitions
Performed 3454 trivial Post agglomeration. Transition count delta: 3454
Iterating post reduction 0 with 3454 rules applied. Total rules applied 3454 place count 4441 transition count 4746
Reduce places removed 3454 places and 0 transitions.
Performed 144 Post agglomeration using F-continuation condition.Transition count delta: 144
Iterating post reduction 1 with 3598 rules applied. Total rules applied 7052 place count 987 transition count 4602
Reduce places removed 178 places and 0 transitions.
Ensure Unique test removed 3300 transitions
Reduce isomorphic transitions removed 3300 transitions.
Iterating post reduction 2 with 3478 rules applied. Total rules applied 10530 place count 809 transition count 1302
Drop transitions removed 198 transitions
Redundant transition composition rules discarded 198 transitions
Iterating global reduction 3 with 198 rules applied. Total rules applied 10728 place count 809 transition count 1104
Applied a total of 10728 rules in 154 ms. Remains 809 /4441 variables (removed 3632) and now considering 1104/8200 (removed 7096) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 155 ms. Remains : 809/4441 places, 1104/8200 transitions.
[2023-03-18 05:43:34] [INFO ] Flatten gal took : 24 ms
[2023-03-18 05:43:34] [INFO ] Flatten gal took : 27 ms
[2023-03-18 05:43:34] [INFO ] Input system was already deterministic with 1104 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Drop transitions removed 3999 transitions
Trivial Post-agglo rules discarded 3999 transitions
Performed 3999 trivial Post agglomeration. Transition count delta: 3999
Iterating post reduction 0 with 3999 rules applied. Total rules applied 3999 place count 4441 transition count 4201
Reduce places removed 4038 places and 0 transitions.
Ensure Unique test removed 3800 transitions
Reduce isomorphic transitions removed 3800 transitions.
Iterating post reduction 1 with 7838 rules applied. Total rules applied 11837 place count 403 transition count 401
Drop transitions removed 99 transitions
Redundant transition composition rules discarded 99 transitions
Iterating global reduction 2 with 99 rules applied. Total rules applied 11936 place count 403 transition count 302
Discarding 99 places :
Implicit places reduction removed 99 places
Drop transitions removed 198 transitions
Trivial Post-agglo rules discarded 198 transitions
Performed 198 trivial Post agglomeration. Transition count delta: 198
Iterating post reduction 2 with 297 rules applied. Total rules applied 12233 place count 304 transition count 104
Reduce places removed 297 places and 0 transitions.
Ensure Unique test removed 98 transitions
Reduce isomorphic transitions removed 98 transitions.
Iterating post reduction 3 with 395 rules applied. Total rules applied 12628 place count 7 transition count 6
Applied a total of 12628 rules in 66 ms. Remains 7 /4441 variables (removed 4434) and now considering 6/8200 (removed 8194) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 68 ms. Remains : 7/4441 places, 6/8200 transitions.
[2023-03-18 05:43:34] [INFO ] Flatten gal took : 1 ms
[2023-03-18 05:43:34] [INFO ] Flatten gal took : 1 ms
[2023-03-18 05:43:34] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 5 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=2 )
FORMULA ServersAndClients-PT-100040-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 4441/4441 places, 8200/8200 transitions.
Applied a total of 0 rules in 569 ms. Remains 4441 /4441 variables (removed 0) and now considering 8200/8200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 574 ms. Remains : 4441/4441 places, 8200/8200 transitions.
[2023-03-18 05:43:35] [INFO ] Flatten gal took : 198 ms
[2023-03-18 05:43:35] [INFO ] Flatten gal took : 218 ms
[2023-03-18 05:43:36] [INFO ] Input system was already deterministic with 8200 transitions.
[2023-03-18 05:43:36] [INFO ] Flatten gal took : 223 ms
[2023-03-18 05:43:36] [INFO ] Flatten gal took : 216 ms
[2023-03-18 05:43:36] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-18 05:43:36] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 4441 places, 8200 transitions and 24800 arcs took 46 ms.
Total runtime 79267 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ServersAndClients-PT-100040
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA ServersAndClients-PT-100040-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ServersAndClients-PT-100040-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679118304288
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 18 (type EXCL) for 9 ServersAndClients-PT-100040-CTLFireability-04
lola: time limit : 221 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-04
lola: result : true
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 40 (type EXCL) for 39 ServersAndClients-PT-100040-CTLFireability-10
lola: time limit : 235 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-10
lola: result : true
lola: markings : 278
lola: fired transitions : 924
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 46 (type EXCL) for 45 ServersAndClients-PT-100040-CTLFireability-12
lola: time limit : 252 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-12
lola: result : true
lola: markings : 603
lola: fired transitions : 1307
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 4 (type EXCL) for 3 ServersAndClients-PT-100040-CTLFireability-02
lola: time limit : 271 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-02
lola: result : false
lola: markings : 466
lola: fired transitions : 1005
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-100040-CTLFireability-02: CTL false CTL model checker
ServersAndClients-PT-100040-CTLFireability-10: CTL true CTL model checker
ServersAndClients-PT-100040-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 37 (type EXCL) for 36 ServersAndClients-PT-100040-CTLFireability-09
lola: time limit : 293 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-100040-CTLFireability-02: CTL false CTL model checker
ServersAndClients-PT-100040-CTLFireability-10: CTL true CTL model checker
ServersAndClients-PT-100040-CTLFireability-12: CTL true CTL model checker
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ServersAndClients-PT-100040-CTLFireability-15: CTL 1 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 2/293 1/32 ServersAndClients-PT-100040-CTLFireability-09 179 m, 35 m/sec, 348 t fired, .
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 37 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-09
lola: result : true
lola: markings : 4201
lola: fired transitions : 8201
lola: time used : 3.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 ServersAndClients-PT-100040-CTLFireability-15
lola: time limit : 319 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-15
lola: result : false
lola: markings : 4201
lola: fired transitions : 12401
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 ServersAndClients-PT-100040-CTLFireability-11
lola: time limit : 351 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-11
lola: result : false
lola: markings : 4
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 ServersAndClients-PT-100040-CTLFireability-08
lola: time limit : 390 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-08
lola: result : true
lola: markings : 4201
lola: fired transitions : 12401
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 ServersAndClients-PT-100040-CTLFireability-07
lola: time limit : 439 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-07
lola: result : false
lola: markings : 4201
lola: fired transitions : 31325
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 ServersAndClients-PT-100040-CTLFireability-06
lola: time limit : 502 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-06
lola: result : true
lola: markings : 290
lola: fired transitions : 592
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 20 ServersAndClients-PT-100040-CTLFireability-05
lola: time limit : 585 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-05
lola: result : true
lola: markings : 3731
lola: fired transitions : 7350
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 9 ServersAndClients-PT-100040-CTLFireability-04
lola: time limit : 878 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-04
lola: result : true
lola: markings : 158
lola: fired transitions : 304
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 12 (type EXCL) for 9 ServersAndClients-PT-100040-CTLFireability-04
lola: time limit : 1171 sec
lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-04
lola: result : false
lola: markings : 2734
lola: fired transitions : 10797
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 ServersAndClients-PT-100040-CTLFireability-03
lola: time limit : 1757 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-03
lola: result : true
lola: markings : 4201
lola: fired transitions : 27566
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 ServersAndClients-PT-100040-CTLFireability-01
lola: time limit : 3514 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for ServersAndClients-PT-100040-CTLFireability-01
lola: result : true
lola: markings : 99
lola: fired transitions : 98
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ServersAndClients-PT-100040-CTLFireability-01: CTL true CTL model checker
ServersAndClients-PT-100040-CTLFireability-02: CTL false CTL model checker
ServersAndClients-PT-100040-CTLFireability-03: CTL true CTL model checker
ServersAndClients-PT-100040-CTLFireability-04: CONJ false CTL model checker
ServersAndClients-PT-100040-CTLFireability-05: DISJ true CTL model checker
ServersAndClients-PT-100040-CTLFireability-06: CTL true CTL model checker
ServersAndClients-PT-100040-CTLFireability-07: CTL false CTL model checker
ServersAndClients-PT-100040-CTLFireability-08: CTL true CTL model checker
ServersAndClients-PT-100040-CTLFireability-09: CTL true CTL model checker
ServersAndClients-PT-100040-CTLFireability-10: CTL true CTL model checker
ServersAndClients-PT-100040-CTLFireability-11: CTL false CTL model checker
ServersAndClients-PT-100040-CTLFireability-12: CTL true CTL model checker
ServersAndClients-PT-100040-CTLFireability-15: CTL false CTL model checker
Time elapsed: 86 secs. Pages in use: 1
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ServersAndClients-PT-100040"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ServersAndClients-PT-100040, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891809000466"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ServersAndClients-PT-100040.tgz
mv ServersAndClients-PT-100040 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;