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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r359-smll-167891808800326
Last Updated
May 14, 2023

About the Execution of LoLa+red for SatelliteMemory-PT-X03000Y0094

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1252.896 55846.00 173834.00 390.70 TTFFFTFFTFFTFFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808800326.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SatelliteMemory-PT-X03000Y0094, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808800326
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 6.5K Feb 26 12:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K Feb 26 12:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 26 12:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 12:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.2K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:50 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:50 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:50 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:50 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 13:02 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 153K Feb 26 13:02 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 26 13:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 70K Feb 26 13:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:50 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:50 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 12 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rwxr-xr-x 1 mcc users 5.5K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1679071134532

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SatelliteMemory-PT-X03000Y0094
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 16:38:57] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-17 16:38:57] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 16:38:57] [INFO ] Load time of PNML (sax parser for PT used): 157 ms
[2023-03-17 16:38:57] [INFO ] Transformed 13 places.
[2023-03-17 16:38:57] [INFO ] Transformed 10 transitions.
[2023-03-17 16:38:57] [INFO ] Parsed PT model containing 13 places and 10 transitions and 40 arcs in 294 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 45 ms.
Working with output stream class java.io.PrintStream
Reduce places removed 1 places and 0 transitions.
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 725 ms. (steps per millisecond=13 ) properties (out of 15) seen :3
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 111 ms. (steps per millisecond=90 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 106 ms. (steps per millisecond=94 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 119 ms. (steps per millisecond=84 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 160 ms. (steps per millisecond=62 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 189 ms. (steps per millisecond=52 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 111 ms. (steps per millisecond=90 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 144 ms. (steps per millisecond=69 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 172 ms. (steps per millisecond=58 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 100 ms. (steps per millisecond=100 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 75 ms. (steps per millisecond=133 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 96 ms. (steps per millisecond=104 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 74 ms. (steps per millisecond=135 ) properties (out of 12) seen :0
Running SMT prover for 12 properties.
// Phase 1: matrix 10 rows 12 cols
[2023-03-17 16:39:00] [INFO ] Computed 6 place invariants in 3 ms
[2023-03-17 16:39:00] [INFO ] [Real]Absence check using 6 positive place invariants in 4 ms returned sat
[2023-03-17 16:39:00] [INFO ] After 261ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:9
[2023-03-17 16:39:00] [INFO ] [Nat]Absence check using 6 positive place invariants in 3 ms returned sat
[2023-03-17 16:39:00] [INFO ] After 78ms SMT Verify possible using state equation in natural domain returned unsat :8 sat :4
[2023-03-17 16:39:00] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-17 16:39:00] [INFO ] After 74ms SMT Verify possible using 1 Read/Feed constraints in natural domain returned unsat :8 sat :4
[2023-03-17 16:39:00] [INFO ] After 124ms SMT Verify possible using trap constraints in natural domain returned unsat :8 sat :4
Attempting to minimize the solution found.
Minimization took 132 ms.
[2023-03-17 16:39:00] [INFO ] After 471ms SMT Verify possible using all constraints in natural domain returned unsat :8 sat :4
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 12 Parikh solutions to 4 different solutions.
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 3 properties in 924 ms.
Support contains 11 out of 12 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 13 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:39:01] [INFO ] Invariant cache hit.
[2023-03-17 16:39:01] [INFO ] Dead Transitions using invariants and state equation in 42 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 57 ms. Remains : 12/12 places, 10/10 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 3181709 steps, run timeout after 3001 ms. (steps per millisecond=1060 ) properties seen :{}
Probabilistic random walk after 3181709 steps, saw 1113425 distinct states, run finished after 3004 ms. (steps per millisecond=1059 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 16:39:04] [INFO ] Invariant cache hit.
[2023-03-17 16:39:05] [INFO ] After 34ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 16:39:05] [INFO ] [Nat]Absence check using 6 positive place invariants in 3 ms returned sat
[2023-03-17 16:39:05] [INFO ] After 350ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 16:39:05] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-17 16:39:05] [INFO ] After 22ms SMT Verify possible using 1 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 16:39:05] [INFO ] After 30ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 25 ms.
[2023-03-17 16:39:05] [INFO ] After 451ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished Parikh walk after 162217 steps, including 0 resets, run visited all 1 properties in 182 ms. (steps per millisecond=891 )
FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 1 properties in 181 ms.
All properties solved without resorting to model-checking.
Total runtime 8161 ms.
starting LoLA
BK_INPUT SatelliteMemory-PT-X03000Y0094
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679071190378

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH INITIAL
lola: LAUNCH task # 22 (type CNST) for 21 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 57 (type EXCL) for 3 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 53 (type FNDP) for 3 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 3 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 22 (type CNST) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type SRCH) for 3 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-54.sara.
sara: place or transition ordering is non-deterministic
lola: CANCELED task # 56 (type SRCH) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01 (memory limit exceeded)

lola: FINISHED task # 54 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01
lola: result : false
lola: CANCELED task # 53 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 57 (type EXCL) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 143 (type EXCL) for 39 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 9 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 9 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 61 (type SRCH) for 9 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01
lola: result : unknown
lola: fired transitions : 6245632
lola: tried executions : 8
lola: time used : 3.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-49.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03: EF 0 2 3 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2/189 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03 3405606 t fired, 4 attempts, .
49 EF STEQ 2/189 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03 sara is running.
61 EF SRCH 2/199 4/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03 1158059 m, 231611 m/sec, 2132410 t fired, .
143 EF EXCL 2/256 4/32 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 1044725 m, 208945 m/sec, 1047907 t fired, .

Time elapsed: 5 secs. Pages in use: 9
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 61 (type SRCH) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03: EF 0 2 2 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 7/187 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03 13391224 t fired, 14 attempts, .
49 EF STEQ 7/187 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03 sara is running.
143 EF EXCL 7/256 15/32 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 3875748 m, 566204 m/sec, 3879433 t fired, .

Time elapsed: 10 secs. Pages in use: 15
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 78 (type FNDP) for 12 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages

lola: FINISHED task # 49 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03
lola: result : false
lola: CANCELED task # 48 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 97 (type FNDP) for 45 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 107 (type EQUN) for 45 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 48 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 14066677
lola: tried executions : 16
lola: time used : 8.000000
lola: memory pages used : 0
lola: FINISHED task # 97 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15
lola: result : true
lola: fired transitions : 322
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 107 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 109 (type FNDP) for 30 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 129 (type EQUN) for 30 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 109 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10
lola: result : true
lola: fired transitions : 3127
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 129 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 90 (type FNDP) for 24 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 98 (type EQUN) for 24 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-107.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-98.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 90 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 6188
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 98 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 101 (type FNDP) for 27 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 110 (type EQUN) for 27 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 98 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08
sara: lola: try reading problem file /home/mcc/execution/ReachabilityCardinality-129.sara.
result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-110.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 110 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09
lola: result : false
lola: CANCELED task # 101 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 67 (type FNDP) for 42 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type EQUN) for 42 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 101 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09
lola: result : unknown
lola: fired transitions : 337085
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 67 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14
lola: result : true
lola: fired transitions : 2542
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 68 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 84 (type FNDP) for 18 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type EQUN) for 18 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-68.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-85.sara.

lola: FINISHED task # 85 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06
lola: result : true
lola: CANCELED task # 84 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 118 (type FNDP) for 36 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 119 (type EQUN) for 36 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 84 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06
lola: result : unknown
lola: fired transitions : 17036
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0

lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 107 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15
lola: result : true
lola: FINISHED task # 118 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 1719
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 119 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 50 (type FNDP) for 6 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type EQUN) for 6 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 119 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-51.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 51 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02
lola: result : false
lola: CANCELED task # 50 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 75 (type FNDP) for 0 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type EQUN) for 0 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 50 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02
lola: result : unknown
lola: fired transitions : 39754
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-76.sara.

lola: FINISHED task # 76 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00
lola: result : false
lola: CANCELED task # 75 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 92 (type FNDP) for 15 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 95 (type EQUN) for 15 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 75 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00
lola: result : unknown
lola: fired transitions : 180437
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 92 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 376
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 95 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 94 (type FNDP) for 33 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 105 (type EQUN) for 33 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 95 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05
lola: result : unknown

lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 68 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-105.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 105 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11
lola: result : false
lola: CANCELED task # 94 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 79 (type EQUN) for 12 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 103 (type SRCH) for 12 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 94 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11
lola: result : unknown
lola: fired transitions : 87817
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-79.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 129 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06: AG false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07: INITIAL false preprocessing
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04: EF 0 2 3 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 EF FNDP 5/1792 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 6032357 t fired, 7 attempts, .
79 EF STEQ 3/1195 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 sara is running.
103 EF SRCH 3/1195 5/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 1452150 m, 290430 m/sec, 3833580 t fired, .
143 EF EXCL 12/1798 26/32 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 6560386 m, 536927 m/sec, 6564548 t fired, .

Time elapsed: 15 secs. Pages in use: 31
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 103 (type SRCH) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 (memory limit exceeded)
lola: CANCELED task # 143 (type EXCL) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06: AG false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07: INITIAL false preprocessing
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04: EF 0 2 2 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 EF FNDP 10/1790 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 13967807 t fired, 14 attempts, .
79 EF STEQ 8/1193 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 sara is running.

Time elapsed: 20 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 104 (type EXCL) for 12 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04
lola: time limit : 3580 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 112 (type FNDP) for 39 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06: AG false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07: INITIAL false preprocessing
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04: EF 0 1 3 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 EF FNDP 15/1785 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 15635816 t fired, 16 attempts, .
79 EF STEQ 13/1786 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 sara is running.
104 EF EXCL 5/3580 11/32 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 2657251 m, 531450 m/sec, 4312877 t fired, .
112 EF FNDP 5/1193 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 2978544 t fired, 3 attempts, .

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06: AG false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07: INITIAL false preprocessing
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04: EF 0 1 3 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 EF FNDP 20/1780 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 17273877 t fired, 18 attempts, .
79 EF STEQ 18/1781 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 sara is running.
104 EF EXCL 10/3580 20/32 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 5187485 m, 506046 m/sec, 8426227 t fired, .
112 EF FNDP 10/1188 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 6108976 t fired, 7 attempts, .

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06: AG false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07: INITIAL false preprocessing
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04: EF 0 1 3 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 EF FNDP 25/1775 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 18843087 t fired, 19 attempts, .
79 EF STEQ 23/1776 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 sara is running.
104 EF EXCL 15/3580 30/32 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 7823014 m, 527105 m/sec, 12709510 t fired, .
112 EF FNDP 15/1183 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 9238196 t fired, 10 attempts, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 104 (type EXCL) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06: AG false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07: INITIAL false preprocessing
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04: EF 0 1 2 0 1 0 2 0
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 EF FNDP 30/1770 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 20466572 t fired, 21 attempts, .
79 EF STEQ 28/1771 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 sara is running.
112 EF FNDP 20/1178 0/5 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 12341641 t fired, 13 attempts, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 130 (type EQUN) for 39 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-130.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 130 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13
lola: result : false
lola: CANCELED task # 112 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13 (obsolete)
lola: LAUNCH task # 140 (type SRCH) for 12 SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 140 (type SRCH) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04
lola: result : unknown
lola: markings : 10
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 112 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13
lola: result : unknown
lola: fired transitions : 12409533
lola: tried executions : 14
lola: time used : 20.000000
lola: memory pages used : 0

lola: FINISHED task # 79 (type EQUN) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04
lola: result : false
lola: CANCELED task # 78 (type FNDP) for SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-00: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-01: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-02: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-03: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-04: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-05: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-06: AG false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-07: INITIAL false preprocessing
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-08: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-09: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-10: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-11: AG true state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-12: AG false findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-13: EF false state equation
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-14: EF true findpath
SatelliteMemory-PT-X03000Y0094-ReachabilityCardinality-15: AG false findpath


Time elapsed: 44 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SatelliteMemory-PT-X03000Y0094"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SatelliteMemory-PT-X03000Y0094, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808800326"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SatelliteMemory-PT-X03000Y0094.tgz
mv SatelliteMemory-PT-X03000Y0094 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;