About the Execution of LoLa+red for SatelliteMemory-PT-X01500Y0046
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5634.571 | 204721.00 | 199986.00 | 1824.90 | T?T???T?FF?FFT?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808800314.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SatelliteMemory-PT-X01500Y0046, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808800314
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 7.7K Feb 26 12:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 26 12:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 26 12:43 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 26 12:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.2K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:50 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:50 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:50 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:50 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 12:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 156K Feb 26 12:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 26 12:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 26 12:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:50 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:50 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 12 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rwxr-xr-x 1 mcc users 5.5K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-00
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-01
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-02
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-03
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-04
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-05
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-06
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-07
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-08
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-09
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-10
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-11
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-12
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-13
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-14
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679070683650
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SatelliteMemory-PT-X01500Y0046
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 16:31:28] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 16:31:28] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 16:31:28] [INFO ] Load time of PNML (sax parser for PT used): 29 ms
[2023-03-17 16:31:28] [INFO ] Transformed 13 places.
[2023-03-17 16:31:28] [INFO ] Transformed 10 transitions.
[2023-03-17 16:31:28] [INFO ] Parsed PT model containing 13 places and 10 transitions and 40 arcs in 144 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Reduce places removed 1 places and 0 transitions.
Support contains 12 out of 12 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 13 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
// Phase 1: matrix 10 rows 12 cols
[2023-03-17 16:31:28] [INFO ] Computed 6 place invariants in 9 ms
[2023-03-17 16:31:29] [INFO ] Dead Transitions using invariants and state equation in 211 ms found 0 transitions.
[2023-03-17 16:31:29] [INFO ] Invariant cache hit.
[2023-03-17 16:31:29] [INFO ] Implicit Places using invariants in 34 ms returned []
[2023-03-17 16:31:29] [INFO ] Invariant cache hit.
[2023-03-17 16:31:29] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-17 16:31:29] [INFO ] Implicit Places using invariants and state equation in 53 ms returned []
Implicit Place search using SMT with State Equation took 90 ms to find 0 implicit places.
[2023-03-17 16:31:29] [INFO ] Invariant cache hit.
[2023-03-17 16:31:29] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 399 ms. Remains : 12/12 places, 10/10 transitions.
Support contains 12 out of 12 places after structural reductions.
[2023-03-17 16:31:29] [INFO ] Flatten gal took : 29 ms
[2023-03-17 16:31:29] [INFO ] Flatten gal took : 10 ms
[2023-03-17 16:31:29] [INFO ] Input system was already deterministic with 10 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 757 ms. (steps per millisecond=13 ) properties (out of 25) seen :16
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 108 ms. (steps per millisecond=92 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 90 ms. (steps per millisecond=111 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 117 ms. (steps per millisecond=85 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 79 ms. (steps per millisecond=126 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 96 ms. (steps per millisecond=104 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 116 ms. (steps per millisecond=86 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 9) seen :0
Running SMT prover for 9 properties.
[2023-03-17 16:31:31] [INFO ] Invariant cache hit.
[2023-03-17 16:31:31] [INFO ] [Real]Absence check using 6 positive place invariants in 2 ms returned sat
[2023-03-17 16:31:31] [INFO ] After 134ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:8
[2023-03-17 16:31:31] [INFO ] [Nat]Absence check using 6 positive place invariants in 3 ms returned sat
[2023-03-17 16:31:31] [INFO ] After 74ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :8
[2023-03-17 16:31:31] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-17 16:31:31] [INFO ] After 166ms SMT Verify possible using 1 Read/Feed constraints in natural domain returned unsat :1 sat :8
[2023-03-17 16:31:31] [INFO ] After 290ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :8
Attempting to minimize the solution found.
Minimization took 599 ms.
[2023-03-17 16:31:32] [INFO ] After 1037ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :8
Fused 9 Parikh solutions to 6 different solutions.
Finished Parikh walk after 2819 steps, including 0 resets, run visited all 8 properties in 118 ms. (steps per millisecond=23 )
Parikh walk visited 8 properties in 119 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-17 16:31:32] [INFO ] Flatten gal took : 5 ms
[2023-03-17 16:31:32] [INFO ] Flatten gal took : 5 ms
[2023-03-17 16:31:32] [INFO ] Input system was already deterministic with 10 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Graph (trivial) has 2 edges and 12 vertex of which 2 / 12 are part of one of the 1 SCC in 3 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Reduce places removed 1 places and 0 transitions.
Applied a total of 1 rules in 10 ms. Remains 10 /12 variables (removed 2) and now considering 9/10 (removed 1) transitions.
// Phase 1: matrix 9 rows 10 cols
[2023-03-17 16:31:32] [INFO ] Computed 5 place invariants in 2 ms
[2023-03-17 16:31:32] [INFO ] Dead Transitions using invariants and state equation in 54 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 65 ms. Remains : 10/12 places, 9/10 transitions.
[2023-03-17 16:31:32] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:32] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:32] [INFO ] Input system was already deterministic with 9 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 3170743 steps, run timeout after 3001 ms. (steps per millisecond=1056 ) properties seen :{}
Probabilistic random walk after 3170743 steps, saw 994244 distinct states, run finished after 3002 ms. (steps per millisecond=1056 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 16:31:35] [INFO ] Invariant cache hit.
[2023-03-17 16:31:35] [INFO ] [Real]Absence check using 5 positive place invariants in 3 ms returned sat
[2023-03-17 16:31:35] [INFO ] After 46ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 16:31:35] [INFO ] [Nat]Absence check using 5 positive place invariants in 2 ms returned sat
[2023-03-17 16:31:35] [INFO ] After 22ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 16:31:35] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-17 16:31:35] [INFO ] After 4ms SMT Verify possible using 1 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 16:31:35] [INFO ] After 28ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 11 ms.
[2023-03-17 16:31:35] [INFO ] After 90ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished Parikh walk after 3587 steps, including 0 resets, run visited all 1 properties in 13 ms. (steps per millisecond=275 )
FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 1 properties in 13 ms.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 2 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
// Phase 1: matrix 10 rows 12 cols
[2023-03-17 16:31:35] [INFO ] Computed 6 place invariants in 2 ms
[2023-03-17 16:31:35] [INFO ] Dead Transitions using invariants and state equation in 37 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 40 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:35] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:35] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 3 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 36 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 38 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 33 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 34 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Graph (trivial) has 2 edges and 12 vertex of which 2 / 12 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Reduce places removed 1 places and 0 transitions.
Applied a total of 1 rules in 2 ms. Remains 10 /12 variables (removed 2) and now considering 9/10 (removed 1) transitions.
// Phase 1: matrix 9 rows 10 cols
[2023-03-17 16:31:36] [INFO ] Computed 5 place invariants in 1 ms
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 10/12 places, 9/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
// Phase 1: matrix 10 rows 12 cols
[2023-03-17 16:31:36] [INFO ] Computed 6 place invariants in 1 ms
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 37 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 39 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 33 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 35 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 43 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 46 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:31:36] [INFO ] Invariant cache hit.
[2023-03-17 16:31:36] [INFO ] Dead Transitions using invariants and state equation in 37 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 39 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Input system was already deterministic with 10 transitions.
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:31:36] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:31:36] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-17 16:31:36] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 12 places, 10 transitions and 38 arcs took 0 ms.
Total runtime 8071 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SatelliteMemory-PT-X01500Y0046
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679070888371
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 8 (type EXCL) for 3 SatelliteMemory-PT-X01500Y0046-CTLFireability-02
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 8 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-02
lola: result : true
lola: markings : 11998
lola: fired transitions : 17996
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 SatelliteMemory-PT-X01500Y0046-CTLFireability-12
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 42 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-12
lola: result : false
lola: markings : 11998
lola: fired transitions : 32994
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 54 SatelliteMemory-PT-X01500Y0046-CTLFireability-15
lola: time limit : 240 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 5/240 9/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-15 1963002 m, 392600 m/sec, 3188039 t fired, .
Time elapsed: 5 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 10/240 18/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-15 4253451 m, 458089 m/sec, 6910915 t fired, .
Time elapsed: 10 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 15/240 28/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-15 6476438 m, 444597 m/sec, 10523208 t fired, .
Time elapsed: 15 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 55 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 52 (type EXCL) for 47 SatelliteMemory-PT-X01500Y0046-CTLFireability-14
lola: time limit : 255 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 1 1 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 5/255 13/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-14 2880683 m, 576136 m/sec, 4680113 t fired, .
Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 1 1 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 10/255 23/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-14 5426319 m, 509127 m/sec, 8817255 t fired, .
Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 52 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 1 0 0 2 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 50 (type EXCL) for 47 SatelliteMemory-PT-X01500Y0046-CTLFireability-14
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-14
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 SatelliteMemory-PT-X01500Y0046-CTLFireability-13
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-13
lola: result : true
lola: markings : 5634
lola: fired transitions : 14086
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 SatelliteMemory-PT-X01500Y0046-CTLFireability-10
lola: time limit : 324 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 5/324 12/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-10 2628110 m, 525622 m/sec, 8209940 t fired, .
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 10/324 21/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-10 4887684 m, 451914 m/sec, 15271223 t fired, .
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 15/324 30/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-10 7078084 m, 438080 m/sec, 22116904 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 36 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 33 (type EXCL) for 32 SatelliteMemory-PT-X01500Y0046-CTLFireability-09
lola: time limit : 354 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-09
lola: result : false
lola: markings : 12003
lola: fired transitions : 12005
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 SatelliteMemory-PT-X01500Y0046-CTLFireability-05
lola: time limit : 393 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/393 6/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 1306472 m, 261294 m/sec, 4076888 t fired, .
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/393 12/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 2715890 m, 281883 m/sec, 8478020 t fired, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/393 18/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 4095609 m, 275943 m/sec, 12790533 t fired, .
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 20/393 23/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 5447735 m, 270425 m/sec, 17012096 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 25/393 29/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 6779004 m, 266253 m/sec, 21175563 t fired, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 17 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 14 (type EXCL) for 13 SatelliteMemory-PT-X01500Y0046-CTLFireability-04
lola: time limit : 439 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/439 3/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 701500 m, 140300 m/sec, 5124334 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 10/439 6/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 1410568 m, 141813 m/sec, 10350865 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 15/439 9/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 2103343 m, 138555 m/sec, 15460720 t fired, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 20/439 12/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 2780421 m, 135415 m/sec, 20453068 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 25/439 15/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 3448767 m, 133669 m/sec, 25382638 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 30/439 18/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 4099019 m, 130050 m/sec, 30177577 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 35/439 20/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 4730099 m, 126216 m/sec, 34832388 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 40/439 23/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 5372697 m, 128519 m/sec, 39570510 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 45/439 26/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 6015547 m, 128570 m/sec, 44312517 t fired, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 50/439 28/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 6658929 m, 128676 m/sec, 49058508 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 55/439 31/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 7295420 m, 127298 m/sec, 53749672 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 14 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 11 (type EXCL) for 10 SatelliteMemory-PT-X01500Y0046-CTLFireability-03
lola: time limit : 493 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/493 16/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-03 3728228 m, 745645 m/sec, 6056927 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/493 30/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-03 6980207 m, 650395 m/sec, 11341881 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 11 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 58 (type EXCL) for 19 SatelliteMemory-PT-X01500Y0046-CTLFireability-06
lola: time limit : 573 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-06
lola: result : false
lola: markings : 5637
lola: fired transitions : 5638
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 38 SatelliteMemory-PT-X01500Y0046-CTLFireability-11
lola: time limit : 860 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-11
lola: result : true
lola: markings : 2817
lola: fired transitions : 2817
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 SatelliteMemory-PT-X01500Y0046-CTLFireability-07
lola: time limit : 1146 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 5/1146 22/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-07 5189548 m, 1037909 m/sec, 6258022 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 10/1146 28/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-07 6667315 m, 295553 m/sec, 14102620 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 27 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 30 (type EXCL) for 29 SatelliteMemory-PT-X01500Y0046-CTLFireability-08
lola: time limit : 1712 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-08
lola: result : false
lola: markings : 6001
lola: fired transitions : 12002
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 SatelliteMemory-PT-X01500Y0046-CTLFireability-01
lola: time limit : 3425 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/3425 13/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-01 2880860 m, 576172 m/sec, 7919362 t fired, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/3425 24/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-01 5524685 m, 528765 m/sec, 15189881 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 1 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: Portfolio finished: no open tasks 15
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ unknown DISJ
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL unknown AGGR
Time elapsed: 190 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SatelliteMemory-PT-X01500Y0046"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SatelliteMemory-PT-X01500Y0046, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808800314"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SatelliteMemory-PT-X01500Y0046.tgz
mv SatelliteMemory-PT-X01500Y0046 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;