About the Execution of LoLa+red for SatelliteMemory-PT-X00100Y0003
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 222.392 | 9853.00 | 16592.00 | 436.20 | FTFTFTTFTFFTFTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808800298.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SatelliteMemory-PT-X00100Y0003, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808800298
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 496K
-rw-r--r-- 1 mcc users 7.8K Feb 26 12:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 88K Feb 26 12:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 26 12:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 26 12:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.2K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:50 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:50 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:50 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:50 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 12:35 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 162K Feb 26 12:35 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 26 12:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 12:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:50 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:50 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 12 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rwxr-xr-x 1 mcc users 5.5K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-00
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-01
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-02
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-03
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-04
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-05
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-06
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-07
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-08
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-09
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-10
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-11
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-12
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-13
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-14
FORMULA_NAME SatelliteMemory-PT-X00100Y0003-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679069598552
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SatelliteMemory-PT-X00100Y0003
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 16:13:21] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 16:13:21] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 16:13:21] [INFO ] Load time of PNML (sax parser for PT used): 29 ms
[2023-03-17 16:13:21] [INFO ] Transformed 13 places.
[2023-03-17 16:13:21] [INFO ] Transformed 10 transitions.
[2023-03-17 16:13:21] [INFO ] Parsed PT model containing 13 places and 10 transitions and 40 arcs in 138 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Reduce places removed 1 places and 0 transitions.
Support contains 12 out of 12 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 14 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
// Phase 1: matrix 10 rows 12 cols
[2023-03-17 16:13:21] [INFO ] Computed 6 place invariants in 6 ms
[2023-03-17 16:13:21] [INFO ] Dead Transitions using invariants and state equation in 358 ms found 0 transitions.
[2023-03-17 16:13:21] [INFO ] Invariant cache hit.
[2023-03-17 16:13:22] [INFO ] Implicit Places using invariants in 38 ms returned []
[2023-03-17 16:13:22] [INFO ] Invariant cache hit.
[2023-03-17 16:13:22] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-17 16:13:22] [INFO ] Implicit Places using invariants and state equation in 55 ms returned []
Implicit Place search using SMT with State Equation took 95 ms to find 0 implicit places.
[2023-03-17 16:13:22] [INFO ] Invariant cache hit.
[2023-03-17 16:13:22] [INFO ] Dead Transitions using invariants and state equation in 42 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 556 ms. Remains : 12/12 places, 10/10 transitions.
Support contains 12 out of 12 places after structural reductions.
[2023-03-17 16:13:22] [INFO ] Flatten gal took : 28 ms
[2023-03-17 16:13:22] [INFO ] Flatten gal took : 9 ms
[2023-03-17 16:13:22] [INFO ] Input system was already deterministic with 10 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 669 ms. (steps per millisecond=14 ) properties (out of 23) seen :19
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 4) seen :3
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:23] [INFO ] [Real]Absence check using 6 positive place invariants in 2 ms returned sat
[2023-03-17 16:13:23] [INFO ] After 41ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 4 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 3 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Graph (trivial) has 2 edges and 12 vertex of which 2 / 12 are part of one of the 1 SCC in 3 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Reduce places removed 1 places and 0 transitions.
Applied a total of 1 rules in 9 ms. Remains 10 /12 variables (removed 2) and now considering 9/10 (removed 1) transitions.
// Phase 1: matrix 9 rows 10 cols
[2023-03-17 16:13:23] [INFO ] Computed 5 place invariants in 2 ms
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 48 ms. Remains : 10/12 places, 9/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
// Phase 1: matrix 10 rows 12 cols
[2023-03-17 16:13:23] [INFO ] Computed 6 place invariants in 2 ms
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 49 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 28 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 28 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 39 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 41 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 40 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 43 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 40 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:23] [INFO ] Dead Transitions using invariants and state equation in 40 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 42 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:23] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:23] [INFO ] Invariant cache hit.
[2023-03-17 16:13:24] [INFO ] Dead Transitions using invariants and state equation in 41 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 42 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 3 ms
[2023-03-17 16:13:24] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:13:24] [INFO ] Invariant cache hit.
[2023-03-17 16:13:24] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 40 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:13:24] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Graph (trivial) has 2 edges and 12 vertex of which 2 / 12 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Reduce places removed 1 places and 0 transitions.
Applied a total of 1 rules in 2 ms. Remains 10 /12 variables (removed 2) and now considering 9/10 (removed 1) transitions.
// Phase 1: matrix 9 rows 10 cols
[2023-03-17 16:13:24] [INFO ] Computed 5 place invariants in 1 ms
[2023-03-17 16:13:24] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 10/12 places, 9/10 transitions.
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 4 ms
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:24] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
// Phase 1: matrix 10 rows 12 cols
[2023-03-17 16:13:24] [INFO ] Computed 6 place invariants in 1 ms
[2023-03-17 16:13:24] [INFO ] Dead Transitions using invariants and state equation in 56 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 60 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:13:24] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Graph (trivial) has 2 edges and 12 vertex of which 2 / 12 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Reduce places removed 1 places and 0 transitions.
Applied a total of 1 rules in 1 ms. Remains 10 /12 variables (removed 2) and now considering 9/10 (removed 1) transitions.
// Phase 1: matrix 9 rows 10 cols
[2023-03-17 16:13:24] [INFO ] Computed 5 place invariants in 1 ms
[2023-03-17 16:13:24] [INFO ] Dead Transitions using invariants and state equation in 55 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 64 ms. Remains : 10/12 places, 9/10 transitions.
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:13:24] [INFO ] Input system was already deterministic with 9 transitions.
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 4 ms
[2023-03-17 16:13:24] [INFO ] Flatten gal took : 3 ms
[2023-03-17 16:13:24] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 10 ms.
[2023-03-17 16:13:24] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 12 places, 10 transitions and 38 arcs took 0 ms.
Total runtime 3019 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SatelliteMemory-PT-X00100Y0003
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/371
CTLFireability
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SatelliteMemory-PT-X00100Y0003-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679069608405
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/371/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/371/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/371/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 4 (type EXCL) for 3 SatelliteMemory-PT-X00100Y0003-CTLFireability-01
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 70 (type FNDP) for 0 SatelliteMemory-PT-X00100Y0003-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type EQUN) for 0 SatelliteMemory-PT-X00100Y0003-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SRCH) for 0 SatelliteMemory-PT-X00100Y0003-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 73 (type SRCH) for SatelliteMemory-PT-X00100Y0003-CTLFireability-00
lola: result : unknown
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 70 (type FNDP) for SatelliteMemory-PT-X00100Y0003-CTLFireability-00
lola: result : true
lola: fired transitions : 188
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 71 (type EQUN) for SatelliteMemory-PT-X00100Y0003-CTLFireability-00 (obsolete)
lola: FINISHED task # 71 (type EQUN) for SatelliteMemory-PT-X00100Y0003-CTLFireability-00
lola: result : unknown
lola: FINISHED task # 4 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-01
lola: result : true
lola: markings : 76358
lola: fired transitions : 609494
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 63 (type EXCL) for 62 SatelliteMemory-PT-X00100Y0003-CTLFireability-14
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 63 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-14
lola: result : true
lola: markings : 8
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 56 SatelliteMemory-PT-X00100Y0003-CTLFireability-12
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-12
lola: result : false
lola: markings : 804
lola: fired transitions : 4794
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 45 SatelliteMemory-PT-X00100Y0003-CTLFireability-11
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-11
lola: result : false
lola: markings : 76358
lola: fired transitions : 381019
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 45 SatelliteMemory-PT-X00100Y0003-CTLFireability-11
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-11
lola: result : true
lola: markings : 189
lola: fired transitions : 188
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 SatelliteMemory-PT-X00100Y0003-CTLFireability-10
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-10
lola: result : false
lola: markings : 76354
lola: fired transitions : 323256
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 SatelliteMemory-PT-X00100Y0003-CTLFireability-09
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-09
lola: result : false
lola: markings : 76354
lola: fired transitions : 304459
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 SatelliteMemory-PT-X00100Y0003-CTLFireability-07
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-07
lola: result : false
lola: markings : 74683
lola: fired transitions : 121454
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 26 SatelliteMemory-PT-X00100Y0003-CTLFireability-06
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-06
lola: result : false
lola: markings : 74685
lola: fired transitions : 121457
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 26 SatelliteMemory-PT-X00100Y0003-CTLFireability-06
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-06
lola: result : true
lola: markings : 75526
lola: fired transitions : 132159
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 23 SatelliteMemory-PT-X00100Y0003-CTLFireability-05
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-05
lola: result : true
lola: markings : 74685
lola: fired transitions : 346056
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 20 SatelliteMemory-PT-X00100Y0003-CTLFireability-04
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-04
lola: result : false
lola: markings : 76358
lola: fired transitions : 209485
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 17 SatelliteMemory-PT-X00100Y0003-CTLFireability-03
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-03
lola: result : true
lola: markings : 798
lola: fired transitions : 1195
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 6 SatelliteMemory-PT-X00100Y0003-CTLFireability-02
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-02
lola: result : false
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 6 SatelliteMemory-PT-X00100Y0003-CTLFireability-02
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-02
lola: result : false
lola: markings : 76358
lola: fired transitions : 209484
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 SatelliteMemory-PT-X00100Y0003-CTLFireability-08
lola: time limit : 1199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-08
lola: result : true
lola: markings : 380
lola: fired transitions : 571
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 68 (type EXCL) for 65 SatelliteMemory-PT-X00100Y0003-CTLFireability-15
lola: time limit : 1798 sec
lola: memory limit: 32 pages
lola: FINISHED task # 68 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-15
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 60 (type EXCL) for 59 SatelliteMemory-PT-X00100Y0003-CTLFireability-13
lola: time limit : 3597 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for SatelliteMemory-PT-X00100Y0003-CTLFireability-13
lola: result : true
lola: markings : 38177
lola: fired transitions : 247480
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X00100Y0003-CTLFireability-00: AG false findpath
SatelliteMemory-PT-X00100Y0003-CTLFireability-01: CTL true CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-02: CONJ false CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-03: CTL true CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-04: CTL false CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-05: CTL true CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-06: DISJ true CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-07: CTL false CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-08: AGEF true tscc_search
SatelliteMemory-PT-X00100Y0003-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-10: CTL false CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-11: DISJ true state space /EXEF
SatelliteMemory-PT-X00100Y0003-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-13: CTL true CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-14: CTL true CTL model checker
SatelliteMemory-PT-X00100Y0003-CTLFireability-15: F false state space / EG
Time elapsed: 3 secs. Pages in use: 2
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SatelliteMemory-PT-X00100Y0003"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SatelliteMemory-PT-X00100Y0003, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808800298"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SatelliteMemory-PT-X00100Y0003.tgz
mv SatelliteMemory-PT-X00100Y0003 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;