About the Execution of LoLa+red for RwMutex-PT-r2000w0010
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16225.451 | 1495870.00 | 1666625.00 | 23695.30 | F??T?T?T??F??T?T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808600194.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RwMutex-PT-r2000w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808600194
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.9M
-rw-r--r-- 1 mcc users 8.0K Feb 25 22:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 90K Feb 25 22:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 25 22:47 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 22:47 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 21K Feb 25 16:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 23:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Feb 25 23:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 23:06 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 95K Feb 25 23:06 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.4M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-00
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-01
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-02
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-03
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-04
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-05
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-06
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-07
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-08
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-09
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-10
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-11
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-12
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-13
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-14
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679002417717
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r2000w0010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 21:33:41] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 21:33:41] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 21:33:42] [INFO ] Load time of PNML (sax parser for PT used): 864 ms
[2023-03-16 21:33:42] [INFO ] Transformed 6020 places.
[2023-03-16 21:33:42] [INFO ] Transformed 4020 transitions.
[2023-03-16 21:33:42] [INFO ] Found NUPN structural information;
[2023-03-16 21:33:42] [INFO ] Parsed PT model containing 6020 places and 4020 transitions and 52040 arcs in 1097 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Support contains 2110 out of 6020 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 985 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
// Phase 1: matrix 4020 rows 6020 cols
[2023-03-16 21:33:43] [INFO ] Computed 4010 place invariants in 109 ms
[2023-03-16 21:33:46] [INFO ] Implicit Places using invariants in 2291 ms returned []
[2023-03-16 21:33:46] [INFO ] Invariant cache hit.
[2023-03-16 21:33:47] [INFO ] Implicit Places using invariants and state equation in 1723 ms returned []
Implicit Place search using SMT with State Equation took 4056 ms to find 0 implicit places.
[2023-03-16 21:33:47] [INFO ] Invariant cache hit.
[2023-03-16 21:33:49] [INFO ] Dead Transitions using invariants and state equation in 1628 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6678 ms. Remains : 6020/6020 places, 4020/4020 transitions.
Support contains 2110 out of 6020 places after structural reductions.
[2023-03-16 21:34:03] [INFO ] Flatten gal took : 13198 ms
[2023-03-16 21:34:15] [INFO ] Flatten gal took : 12259 ms
[2023-03-16 21:34:16] [INFO ] Input system was already deterministic with 4020 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 4485 ms. (steps per millisecond=2 ) properties (out of 87) seen :86
Finished Best-First random walk after 2011 steps, including 0 resets, run visited all 1 properties in 147 ms. (steps per millisecond=13 )
[2023-03-16 21:34:33] [INFO ] Flatten gal took : 11772 ms
[2023-03-16 21:34:44] [INFO ] Flatten gal took : 11456 ms
[2023-03-16 21:34:45] [INFO ] Input system was already deterministic with 4020 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Drop transitions removed 1997 transitions
Trivial Post-agglo rules discarded 1997 transitions
Performed 1997 trivial Post agglomeration. Transition count delta: 1997
Iterating post reduction 0 with 1997 rules applied. Total rules applied 1997 place count 6020 transition count 2023
Reduce places removed 3994 places and 0 transitions.
Iterating post reduction 1 with 3994 rules applied. Total rules applied 5991 place count 2026 transition count 2023
Applied a total of 5991 rules in 1760 ms. Remains 2026 /6020 variables (removed 3994) and now considering 2023/4020 (removed 1997) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1761 ms. Remains : 2026/6020 places, 2023/4020 transitions.
[2023-03-16 21:34:58] [INFO ] Flatten gal took : 10608 ms
[2023-03-16 21:35:08] [INFO ] Flatten gal took : 10561 ms
[2023-03-16 21:35:09] [INFO ] Input system was already deterministic with 2023 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 1118 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1121 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:35:21] [INFO ] Flatten gal took : 10677 ms
[2023-03-16 21:35:31] [INFO ] Flatten gal took : 10586 ms
[2023-03-16 21:35:32] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 851 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 851 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:35:43] [INFO ] Flatten gal took : 10226 ms
[2023-03-16 21:35:54] [INFO ] Flatten gal took : 10683 ms
[2023-03-16 21:35:54] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 615 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 616 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:36:06] [INFO ] Flatten gal took : 10723 ms
[2023-03-16 21:36:16] [INFO ] Flatten gal took : 10408 ms
[2023-03-16 21:36:17] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 845 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 846 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:36:28] [INFO ] Flatten gal took : 10617 ms
[2023-03-16 21:36:38] [INFO ] Flatten gal took : 10122 ms
[2023-03-16 21:36:39] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 711 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 712 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:36:50] [INFO ] Flatten gal took : 10201 ms
[2023-03-16 21:37:01] [INFO ] Flatten gal took : 10627 ms
[2023-03-16 21:37:01] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 726 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 727 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:37:13] [INFO ] Flatten gal took : 10410 ms
[2023-03-16 21:37:23] [INFO ] Flatten gal took : 10854 ms
[2023-03-16 21:37:24] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Drop transitions removed 1988 transitions
Trivial Post-agglo rules discarded 1988 transitions
Performed 1988 trivial Post agglomeration. Transition count delta: 1988
Iterating post reduction 0 with 1988 rules applied. Total rules applied 1988 place count 6020 transition count 2032
Reduce places removed 3976 places and 0 transitions.
Iterating post reduction 1 with 3976 rules applied. Total rules applied 5964 place count 2044 transition count 2032
Applied a total of 5964 rules in 1301 ms. Remains 2044 /6020 variables (removed 3976) and now considering 2032/4020 (removed 1988) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1301 ms. Remains : 2044/6020 places, 2032/4020 transitions.
[2023-03-16 21:37:36] [INFO ] Flatten gal took : 10650 ms
[2023-03-16 21:37:47] [INFO ] Flatten gal took : 10994 ms
[2023-03-16 21:37:48] [INFO ] Input system was already deterministic with 2032 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 921 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 921 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:37:59] [INFO ] Flatten gal took : 10323 ms
[2023-03-16 21:38:09] [INFO ] Flatten gal took : 10282 ms
[2023-03-16 21:38:10] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 798 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 799 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:38:21] [INFO ] Flatten gal took : 10206 ms
[2023-03-16 21:38:31] [INFO ] Flatten gal took : 10635 ms
[2023-03-16 21:38:32] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 722 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 722 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:38:43] [INFO ] Flatten gal took : 10281 ms
[2023-03-16 21:38:54] [INFO ] Flatten gal took : 10626 ms
[2023-03-16 21:38:54] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 720 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 721 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:39:06] [INFO ] Flatten gal took : 10961 ms
[2023-03-16 21:39:17] [INFO ] Flatten gal took : 10602 ms
[2023-03-16 21:39:17] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 720 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 720 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:39:29] [INFO ] Flatten gal took : 10739 ms
[2023-03-16 21:39:39] [INFO ] Flatten gal took : 10346 ms
[2023-03-16 21:39:40] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Drop transitions removed 2006 transitions
Trivial Post-agglo rules discarded 2006 transitions
Performed 2006 trivial Post agglomeration. Transition count delta: 2006
Iterating post reduction 0 with 2006 rules applied. Total rules applied 2006 place count 6020 transition count 2014
Reduce places removed 6008 places and 0 transitions.
Ensure Unique test removed 2004 transitions
Reduce isomorphic transitions removed 2004 transitions.
Iterating post reduction 1 with 8012 rules applied. Total rules applied 10018 place count 12 transition count 10
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 10019 place count 12 transition count 9
Ensure Unique test removed 4 places
Iterating post reduction 2 with 4 rules applied. Total rules applied 10023 place count 8 transition count 9
Applied a total of 10023 rules in 67 ms. Remains 8 /6020 variables (removed 6012) and now considering 9/4020 (removed 4011) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 68 ms. Remains : 8/6020 places, 9/4020 transitions.
[2023-03-16 21:39:40] [INFO ] Flatten gal took : 2 ms
[2023-03-16 21:39:40] [INFO ] Flatten gal took : 1 ms
[2023-03-16 21:39:40] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Applied a total of 0 rules in 894 ms. Remains 6020 /6020 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 894 ms. Remains : 6020/6020 places, 4020/4020 transitions.
[2023-03-16 21:39:52] [INFO ] Flatten gal took : 10748 ms
[2023-03-16 21:40:02] [INFO ] Flatten gal took : 10697 ms
[2023-03-16 21:40:03] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 6020/6020 places, 4020/4020 transitions.
Drop transitions removed 1999 transitions
Trivial Post-agglo rules discarded 1999 transitions
Performed 1999 trivial Post agglomeration. Transition count delta: 1999
Iterating post reduction 0 with 1999 rules applied. Total rules applied 1999 place count 6020 transition count 2021
Reduce places removed 3998 places and 0 transitions.
Iterating post reduction 1 with 3998 rules applied. Total rules applied 5997 place count 2022 transition count 2021
Applied a total of 5997 rules in 1380 ms. Remains 2022 /6020 variables (removed 3998) and now considering 2021/4020 (removed 1999) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1381 ms. Remains : 2022/6020 places, 2021/4020 transitions.
[2023-03-16 21:40:15] [INFO ] Flatten gal took : 10473 ms
[2023-03-16 21:40:26] [INFO ] Flatten gal took : 10659 ms
[2023-03-16 21:40:26] [INFO ] Input system was already deterministic with 2021 transitions.
[2023-03-16 21:40:37] [INFO ] Flatten gal took : 10636 ms
[2023-03-16 21:40:48] [INFO ] Flatten gal took : 10730 ms
[2023-03-16 21:40:48] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 16 ms.
[2023-03-16 21:40:48] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 6020 places, 4020 transitions and 52040 arcs took 62 ms.
Total runtime 426862 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RwMutex-PT-r2000w0010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/369
CTLFireability
FORMULA RwMutex-PT-r2000w0010-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r2000w0010-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r2000w0010-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r2000w0010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r2000w0010-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r2000w0010-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r2000w0010-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679003913587
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/369/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/369/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/369/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 82 (type SKEL/FNDP) for 0 RwMutex-PT-r2000w0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SKEL/EQUN) for 0 RwMutex-PT-r2000w0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SKEL/SRCH) for 0 RwMutex-PT-r2000w0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SKEL/SRCH) for 0 RwMutex-PT-r2000w0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 85 (type SKEL/SRCH) for RwMutex-PT-r2000w0010-CTLFireability-00
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 82 (type FNDP) for RwMutex-PT-r2000w0010-CTLFireability-00 (obsolete)
lola: CANCELED task # 83 (type EQUN) for RwMutex-PT-r2000w0010-CTLFireability-00 (obsolete)
lola: CANCELED task # 84 (type SRCH) for RwMutex-PT-r2000w0010-CTLFireability-00 (obsolete)
lola: FINISHED task # 84 (type SKEL/SRCH) for RwMutex-PT-r2000w0010-CTLFireability-00
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 82 (type SKEL/FNDP) for RwMutex-PT-r2000w0010-CTLFireability-00
lola: result : true
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/369/CTLFireability-83.sara.
lola: FINISHED task # 83 (type SKEL/EQUN) for RwMutex-PT-r2000w0010-CTLFireability-00
lola: result : true
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r2000w0010-CTLFireability-00: CONJ 0 0 0 0 6 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-15: EG 0 0 0 0 0 0 0 0
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lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 78 (type EXCL) for RwMutex-PT-r2000w0010-CTLFireability-15
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RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
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lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 105 (type EXCL) for RwMutex-PT-r2000w0010-CTLFireability-00
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG
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RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 0 0 0 8 0 0 1
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 1 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 483 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r2000w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RwMutex-PT-r2000w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808600194"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r2000w0010.tgz
mv RwMutex-PT-r2000w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;