About the Execution of LoLa+red for RwMutex-PT-r1000w0010
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16215.771 | 835326.00 | 896199.00 | 14815.00 | F?????F?FFT?FTF? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808600186.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RwMutex-PT-r1000w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808600186
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.7M
-rw-r--r-- 1 mcc users 6.2K Feb 25 22:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 25 22:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 22:53 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 25 22:53 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 16:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 23:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 147K Feb 25 23:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 23:03 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 101K Feb 25 23:03 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 2.2M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-00
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-01
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-02
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-03
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-04
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-05
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-06
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-07
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-08
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-09
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-10
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-11
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-12
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-13
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-14
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679000080475
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r1000w0010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 20:54:42] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 20:54:42] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 20:54:43] [INFO ] Load time of PNML (sax parser for PT used): 497 ms
[2023-03-16 20:54:43] [INFO ] Transformed 3020 places.
[2023-03-16 20:54:43] [INFO ] Transformed 2020 transitions.
[2023-03-16 20:54:43] [INFO ] Found NUPN structural information;
[2023-03-16 20:54:43] [INFO ] Parsed PT model containing 3020 places and 2020 transitions and 26040 arcs in 670 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 13 ms.
Support contains 113 out of 3020 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 404 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
// Phase 1: matrix 2020 rows 3020 cols
[2023-03-16 20:54:44] [INFO ] Computed 2010 place invariants in 81 ms
[2023-03-16 20:54:45] [INFO ] Implicit Places using invariants in 1546 ms returned []
[2023-03-16 20:54:45] [INFO ] Invariant cache hit.
[2023-03-16 20:54:46] [INFO ] Implicit Places using invariants and state equation in 939 ms returned []
Implicit Place search using SMT with State Equation took 2522 ms to find 0 implicit places.
[2023-03-16 20:54:46] [INFO ] Invariant cache hit.
[2023-03-16 20:54:49] [INFO ] Dead Transitions using invariants and state equation in 2570 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5506 ms. Remains : 3020/3020 places, 2020/2020 transitions.
Support contains 113 out of 3020 places after structural reductions.
[2023-03-16 20:54:53] [INFO ] Flatten gal took : 3461 ms
[2023-03-16 20:54:56] [INFO ] Flatten gal took : 2733 ms
[2023-03-16 20:54:56] [INFO ] Input system was already deterministic with 2020 transitions.
Support contains 107 out of 3020 places (down from 113) after GAL structural reductions.
Finished random walk after 3988 steps, including 1 resets, run visited all 62 properties in 1116 ms. (steps per millisecond=3 )
[2023-03-16 20:55:00] [INFO ] Flatten gal took : 2590 ms
[2023-03-16 20:55:03] [INFO ] Flatten gal took : 2611 ms
[2023-03-16 20:55:03] [INFO ] Input system was already deterministic with 2020 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Drop transitions removed 999 transitions
Trivial Post-agglo rules discarded 999 transitions
Performed 999 trivial Post agglomeration. Transition count delta: 999
Iterating post reduction 0 with 999 rules applied. Total rules applied 999 place count 3020 transition count 1021
Reduce places removed 1998 places and 0 transitions.
Iterating post reduction 1 with 1998 rules applied. Total rules applied 2997 place count 1022 transition count 1021
Applied a total of 2997 rules in 569 ms. Remains 1022 /3020 variables (removed 1998) and now considering 1021/2020 (removed 999) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 571 ms. Remains : 1022/3020 places, 1021/2020 transitions.
[2023-03-16 20:55:06] [INFO ] Flatten gal took : 2525 ms
[2023-03-16 20:55:09] [INFO ] Flatten gal took : 2470 ms
[2023-03-16 20:55:09] [INFO ] Input system was already deterministic with 1021 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 177 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 180 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:55:12] [INFO ] Flatten gal took : 2563 ms
[2023-03-16 20:55:14] [INFO ] Flatten gal took : 2479 ms
[2023-03-16 20:55:15] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 159 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 161 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:55:17] [INFO ] Flatten gal took : 2516 ms
[2023-03-16 20:55:20] [INFO ] Flatten gal took : 2553 ms
[2023-03-16 20:55:20] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 232 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 234 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:55:23] [INFO ] Flatten gal took : 2652 ms
[2023-03-16 20:55:26] [INFO ] Flatten gal took : 2599 ms
[2023-03-16 20:55:26] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 149 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 150 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:55:29] [INFO ] Flatten gal took : 2628 ms
[2023-03-16 20:55:31] [INFO ] Flatten gal took : 2421 ms
[2023-03-16 20:55:32] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 155 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 155 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:55:34] [INFO ] Flatten gal took : 2590 ms
[2023-03-16 20:55:37] [INFO ] Flatten gal took : 2368 ms
[2023-03-16 20:55:37] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 149 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 150 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:55:40] [INFO ] Flatten gal took : 2358 ms
[2023-03-16 20:55:42] [INFO ] Flatten gal took : 2367 ms
[2023-03-16 20:55:42] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 150 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 151 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:55:45] [INFO ] Flatten gal took : 2475 ms
[2023-03-16 20:55:48] [INFO ] Flatten gal took : 2569 ms
[2023-03-16 20:55:48] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 147 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 147 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:55:50] [INFO ] Flatten gal took : 2382 ms
[2023-03-16 20:55:53] [INFO ] Flatten gal took : 2610 ms
[2023-03-16 20:55:53] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 145 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 145 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:55:56] [INFO ] Flatten gal took : 2411 ms
[2023-03-16 20:55:58] [INFO ] Flatten gal took : 2449 ms
[2023-03-16 20:55:59] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 166 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 166 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:56:01] [INFO ] Flatten gal took : 2581 ms
[2023-03-16 20:56:04] [INFO ] Flatten gal took : 2499 ms
[2023-03-16 20:56:04] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 155 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 155 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:56:07] [INFO ] Flatten gal took : 2479 ms
[2023-03-16 20:56:09] [INFO ] Flatten gal took : 2505 ms
[2023-03-16 20:56:10] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Drop transitions removed 996 transitions
Trivial Post-agglo rules discarded 996 transitions
Performed 996 trivial Post agglomeration. Transition count delta: 996
Iterating post reduction 0 with 996 rules applied. Total rules applied 996 place count 3020 transition count 1024
Reduce places removed 1992 places and 0 transitions.
Iterating post reduction 1 with 1992 rules applied. Total rules applied 2988 place count 1028 transition count 1024
Applied a total of 2988 rules in 380 ms. Remains 1028 /3020 variables (removed 1992) and now considering 1024/2020 (removed 996) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 380 ms. Remains : 1028/3020 places, 1024/2020 transitions.
[2023-03-16 20:56:13] [INFO ] Flatten gal took : 2458 ms
[2023-03-16 20:56:15] [INFO ] Flatten gal took : 2528 ms
[2023-03-16 20:56:15] [INFO ] Input system was already deterministic with 1024 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 155 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 156 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:56:18] [INFO ] Flatten gal took : 2564 ms
[2023-03-16 20:56:21] [INFO ] Flatten gal took : 2565 ms
[2023-03-16 20:56:21] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 158 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 158 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:56:24] [INFO ] Flatten gal took : 2586 ms
[2023-03-16 20:56:26] [INFO ] Flatten gal took : 2567 ms
[2023-03-16 20:56:27] [INFO ] Input system was already deterministic with 2020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3020/3020 places, 2020/2020 transitions.
Applied a total of 0 rules in 154 ms. Remains 3020 /3020 variables (removed 0) and now considering 2020/2020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 154 ms. Remains : 3020/3020 places, 2020/2020 transitions.
[2023-03-16 20:56:29] [INFO ] Flatten gal took : 2582 ms
[2023-03-16 20:56:32] [INFO ] Flatten gal took : 2553 ms
[2023-03-16 20:56:32] [INFO ] Input system was already deterministic with 2020 transitions.
[2023-03-16 20:56:35] [INFO ] Flatten gal took : 2568 ms
[2023-03-16 20:56:37] [INFO ] Flatten gal took : 2563 ms
[2023-03-16 20:56:38] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-16 20:56:38] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 3020 places, 2020 transitions and 26040 arcs took 32 ms.
Total runtime 115175 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RwMutex-PT-r1000w0010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA RwMutex-PT-r1000w0010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679000915801
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 61 (type SKEL/FNDP) for 10 RwMutex-PT-r1000w0010-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type SKEL/EQUN) for 10 RwMutex-PT-r1000w0010-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 63 (type SKEL/SRCH) for 10 RwMutex-PT-r1000w0010-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SKEL/SRCH) for 10 RwMutex-PT-r1000w0010-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 63 (type SKEL/SRCH) for RwMutex-PT-r1000w0010-CTLFireability-02
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 61 (type FNDP) for RwMutex-PT-r1000w0010-CTLFireability-02 (obsolete)
lola: CANCELED task # 62 (type EQUN) for RwMutex-PT-r1000w0010-CTLFireability-02 (obsolete)
lola: CANCELED task # 64 (type SRCH) for RwMutex-PT-r1000w0010-CTLFireability-02 (obsolete)
lola: FINISHED task # 61 (type SKEL/FNDP) for RwMutex-PT-r1000w0010-CTLFireability-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 64 (type SKEL/SRCH) for RwMutex-PT-r1000w0010-CTLFireability-02
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/374/CTLFireability-62.sara.
lola: FINISHED task # 62 (type SKEL/EQUN) for RwMutex-PT-r1000w0010-CTLFireability-02
lola: result : true
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 67 (type EXCL) for 10 RwMutex-PT-r1000w0010-CTLFireability-02
lola: time limit : 188 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 65 (type FNDP) for 10 RwMutex-PT-r1000w0010-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type EQUN) for 10 RwMutex-PT-r1000w0010-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type SRCH) for 10 RwMutex-PT-r1000w0010-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 67 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-02
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 65 (type FNDP) for RwMutex-PT-r1000w0010-CTLFireability-02 (obsolete)
lola: CANCELED task # 66 (type EQUN) for RwMutex-PT-r1000w0010-CTLFireability-02 (obsolete)
lola: CANCELED task # 68 (type SRCH) for RwMutex-PT-r1000w0010-CTLFireability-02 (obsolete)
lola: FINISHED task # 65 (type FNDP) for RwMutex-PT-r1000w0010-CTLFireability-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/374/CTLFireability-66.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 66 (type EQUN) for RwMutex-PT-r1000w0010-CTLFireability-02
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CONJ 0 0 0 0 8 0 0 1
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 25 secs. Pages in use: 2
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lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 69 (type EXCL) for 0 RwMutex-PT-r1000w0010-CTLFireability-00
lola: time limit : 198 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 69 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-00
lola: result : true
lola: markings : 12
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 RwMutex-PT-r1000w0010-CTLFireability-12
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-12
lola: result : false
lola: markings : 13
lola: fired transitions : 5102
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CONJ 0 0 0 0 8 0 0 1
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 30 secs. Pages in use: 2
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 40 (type EXCL) for 39 RwMutex-PT-r1000w0010-CTLFireability-09
lola: time limit : 222 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 40 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-09
lola: result : false
lola: markings : 1043
lola: fired transitions : 1288
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 RwMutex-PT-r1000w0010-CTLFireability-06
lola: time limit : 237 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CONJ 0 1 0 0 8 0 0 1
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 2/237 2/32 RwMutex-PT-r1000w0010-CTLFireability-06 108535 m, 21707 m/sec, 137322 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CONJ 0 1 0 0 8 0 0 1
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 7/237 5/32 RwMutex-PT-r1000w0010-CTLFireability-06 392680 m, 56829 m/sec, 470386 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CONJ 0 1 0 0 8 0 0 1
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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27 CTL EXCL 12/237 9/32 RwMutex-PT-r1000w0010-CTLFireability-06 675703 m, 56604 m/sec, 763611 t fired, .
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lola: FINISHED task # 27 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-06
lola: result : false
lola: markings : 695706
lola: fired transitions : 783899
lola: time used : 13.000000
lola: memory pages used : 9
lola: LAUNCH task # 58 (type EXCL) for 57 RwMutex-PT-r1000w0010-CTLFireability-15
lola: time limit : 253 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CONJ 0 1 0 0 8 0 0 1
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 4/253 6/32 RwMutex-PT-r1000w0010-CTLFireability-15 356201 m, 71240 m/sec, 426055 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CONJ 0 1 0 0 8 0 0 1
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 9/253 12/32 RwMutex-PT-r1000w0010-CTLFireability-15 722764 m, 73312 m/sec, 881665 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
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RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 14/253 18/32 RwMutex-PT-r1000w0010-CTLFireability-15 1084096 m, 72266 m/sec, 1338878 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CONJ 0 1 0 0 8 0 0 1
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 19/253 24/32 RwMutex-PT-r1000w0010-CTLFireability-15 1440692 m, 71319 m/sec, 1794523 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 24/253 30/32 RwMutex-PT-r1000w0010-CTLFireability-15 1783347 m, 68531 m/sec, 2234806 t fired, .
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lola: CANCELED task # 58 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-15 (memory limit exceeded)
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RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 55 (type EXCL) for 54 RwMutex-PT-r1000w0010-CTLFireability-14
lola: time limit : 271 sec
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lola: FINISHED task # 55 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-14
lola: result : false
lola: markings : 1011
lola: fired transitions : 2110
lola: time used : 0.000000
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lola: LAUNCH task # 52 (type EXCL) for 51 RwMutex-PT-r1000w0010-CTLFireability-13
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lola: FINISHED task # 52 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-13
lola: result : true
lola: markings : 4007
lola: fired transitions : 14299
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lola: LAUNCH task # 46 (type EXCL) for 45 RwMutex-PT-r1000w0010-CTLFireability-11
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RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
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RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
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RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 4/320 2/32 RwMutex-PT-r1000w0010-CTLFireability-11 73855 m, 14771 m/sec, 545195 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 9/320 3/32 RwMutex-PT-r1000w0010-CTLFireability-11 147318 m, 14692 m/sec, 1166257 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
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RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
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RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 14/320 4/32 RwMutex-PT-r1000w0010-CTLFireability-11 220410 m, 14618 m/sec, 1788311 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
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RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 19/320 5/32 RwMutex-PT-r1000w0010-CTLFireability-11 293099 m, 14537 m/sec, 2412092 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
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RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 24/320 7/32 RwMutex-PT-r1000w0010-CTLFireability-11 364043 m, 14188 m/sec, 3004831 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 29/320 8/32 RwMutex-PT-r1000w0010-CTLFireability-11 432399 m, 13671 m/sec, 3626010 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 34/320 9/32 RwMutex-PT-r1000w0010-CTLFireability-11 497813 m, 13082 m/sec, 4251929 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
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46 CTL EXCL 39/320 10/32 RwMutex-PT-r1000w0010-CTLFireability-11 566165 m, 13670 m/sec, 4872328 t fired, .
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46 CTL EXCL 44/320 11/32 RwMutex-PT-r1000w0010-CTLFireability-11 630857 m, 12938 m/sec, 5482192 t fired, .
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46 CTL EXCL 49/320 12/32 RwMutex-PT-r1000w0010-CTLFireability-11 702441 m, 14316 m/sec, 6097649 t fired, .
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46 CTL EXCL 54/320 14/32 RwMutex-PT-r1000w0010-CTLFireability-11 771930 m, 13897 m/sec, 6718123 t fired, .
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46 CTL EXCL 59/320 15/32 RwMutex-PT-r1000w0010-CTLFireability-11 843442 m, 14302 m/sec, 7335510 t fired, .
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46 CTL EXCL 64/320 16/32 RwMutex-PT-r1000w0010-CTLFireability-11 911548 m, 13621 m/sec, 7958367 t fired, .
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46 CTL EXCL 69/320 17/32 RwMutex-PT-r1000w0010-CTLFireability-11 979302 m, 13550 m/sec, 8583382 t fired, .
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46 CTL EXCL 74/320 18/32 RwMutex-PT-r1000w0010-CTLFireability-11 1055887 m, 15317 m/sec, 9202820 t fired, .
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46 CTL EXCL 79/320 20/32 RwMutex-PT-r1000w0010-CTLFireability-11 1128668 m, 14556 m/sec, 9825662 t fired, .
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46 CTL EXCL 84/320 21/32 RwMutex-PT-r1000w0010-CTLFireability-11 1203875 m, 15041 m/sec, 10442561 t fired, .
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46 CTL EXCL 89/320 22/32 RwMutex-PT-r1000w0010-CTLFireability-11 1272017 m, 13628 m/sec, 11068538 t fired, .
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46 CTL EXCL 94/320 23/32 RwMutex-PT-r1000w0010-CTLFireability-11 1340949 m, 13786 m/sec, 11692753 t fired, .
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46 CTL EXCL 99/320 24/32 RwMutex-PT-r1000w0010-CTLFireability-11 1415821 m, 14974 m/sec, 12305915 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 104/320 26/32 RwMutex-PT-r1000w0010-CTLFireability-11 1480916 m, 13019 m/sec, 12932315 t fired, .
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46 CTL EXCL 109/320 27/32 RwMutex-PT-r1000w0010-CTLFireability-11 1550728 m, 13962 m/sec, 13551372 t fired, .
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46 CTL EXCL 114/320 28/32 RwMutex-PT-r1000w0010-CTLFireability-11 1617296 m, 13313 m/sec, 14177108 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 124/320 30/32 RwMutex-PT-r1000w0010-CTLFireability-11 1759790 m, 14285 m/sec, 15412437 t fired, .
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46 CTL EXCL 129/320 31/32 RwMutex-PT-r1000w0010-CTLFireability-11 1822910 m, 12624 m/sec, 16039886 t fired, .
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46 CTL EXCL 134/320 32/32 RwMutex-PT-r1000w0010-CTLFireability-11 1887566 m, 12931 m/sec, 16666622 t fired, .
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lola: CANCELED task # 46 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-11 (memory limit exceeded)
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lola: result : true
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RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
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24 CTL EXCL 5/537 1/32 RwMutex-PT-r1000w0010-CTLFireability-05 4187 m, 837 m/sec, 17165 t fired, .
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24 CTL EXCL 15/537 1/32 RwMutex-PT-r1000w0010-CTLFireability-05 9887 m, 568 m/sec, 55964 t fired, .
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24 CTL EXCL 30/537 1/32 RwMutex-PT-r1000w0010-CTLFireability-05 18274 m, 558 m/sec, 122183 t fired, .
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24 CTL EXCL 200/537 2/32 RwMutex-PT-r1000w0010-CTLFireability-05 114036 m, 566 m/sec, 990198 t fired, .
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24 CTL EXCL 270/537 3/32 RwMutex-PT-r1000w0010-CTLFireability-05 153502 m, 563 m/sec, 1362057 t fired, .
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RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CONJ 0 1 0 0 8 0 0 1
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 335/537 4/32 RwMutex-PT-r1000w0010-CTLFireability-05 190098 m, 571 m/sec, 1725435 t fired, .
Time elapsed: 710 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 472 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r1000w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RwMutex-PT-r1000w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808600186"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r1000w0010.tgz
mv RwMutex-PT-r1000w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;