Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808600178.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RwMutex-PT-r0500w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808600178
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.6M
-rw-r--r-- 1 mcc users 8.1K Feb 25 22:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 93K Feb 25 22:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 25 22:40 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 25 22:40 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 21K Feb 25 16:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 16:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 22:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 118K Feb 25 22:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 25 22:45 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 124K Feb 25 22:45 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 1.1M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-00
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-01
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-02
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-03
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-04
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-05
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-06
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-07
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-08
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-09
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-10
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-11
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-12
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-13
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-14
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678999417867

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r0500w0010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 20:43:41] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 20:43:41] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 20:43:42] [INFO ] Load time of PNML (sax parser for PT used): 428 ms
[2023-03-16 20:43:42] [INFO ] Transformed 1520 places.
[2023-03-16 20:43:42] [INFO ] Transformed 1020 transitions.
[2023-03-16 20:43:42] [INFO ] Found NUPN structural information;
[2023-03-16 20:43:42] [INFO ] Parsed PT model containing 1520 places and 1020 transitions and 13040 arcs in 630 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 19 ms.
Initial state reduction rules removed 1 formulas.
FORMULA RwMutex-PT-r0500w0010-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 592 out of 1520 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 174 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
// Phase 1: matrix 1020 rows 1520 cols
[2023-03-16 20:43:42] [INFO ] Computed 1010 place invariants in 61 ms
[2023-03-16 20:43:44] [INFO ] Implicit Places using invariants in 1815 ms returned []
[2023-03-16 20:43:44] [INFO ] Invariant cache hit.
[2023-03-16 20:43:45] [INFO ] Implicit Places using invariants and state equation in 1316 ms returned []
Implicit Place search using SMT with State Equation took 3174 ms to find 0 implicit places.
[2023-03-16 20:43:45] [INFO ] Invariant cache hit.
[2023-03-16 20:43:47] [INFO ] Dead Transitions using invariants and state equation in 1938 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5291 ms. Remains : 1520/1520 places, 1020/1020 transitions.
Support contains 592 out of 1520 places after structural reductions.
[2023-03-16 20:43:49] [INFO ] Flatten gal took : 1501 ms
[2023-03-16 20:43:50] [INFO ] Flatten gal took : 832 ms
[2023-03-16 20:43:50] [INFO ] Input system was already deterministic with 1020 transitions.
Finished random walk after 3487 steps, including 1 resets, run visited all 72 properties in 685 ms. (steps per millisecond=5 )
[2023-03-16 20:43:52] [INFO ] Flatten gal took : 711 ms
[2023-03-16 20:43:53] [INFO ] Flatten gal took : 651 ms
[2023-03-16 20:43:53] [INFO ] Input system was already deterministic with 1020 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 295 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 297 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:43:54] [INFO ] Flatten gal took : 630 ms
[2023-03-16 20:43:55] [INFO ] Flatten gal took : 712 ms
[2023-03-16 20:43:55] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 105 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 108 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:43:56] [INFO ] Flatten gal took : 743 ms
[2023-03-16 20:43:56] [INFO ] Flatten gal took : 612 ms
[2023-03-16 20:43:57] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Drop transitions removed 509 transitions
Trivial Post-agglo rules discarded 509 transitions
Performed 509 trivial Post agglomeration. Transition count delta: 509
Iterating post reduction 0 with 509 rules applied. Total rules applied 509 place count 1520 transition count 511
Reduce places removed 1517 places and 0 transitions.
Ensure Unique test removed 507 transitions
Reduce isomorphic transitions removed 507 transitions.
Iterating post reduction 1 with 2024 rules applied. Total rules applied 2533 place count 3 transition count 4
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 2534 place count 3 transition count 3
Ensure Unique test removed 1 places
Iterating post reduction 2 with 1 rules applied. Total rules applied 2535 place count 2 transition count 3
Applied a total of 2535 rules in 53 ms. Remains 2 /1520 variables (removed 1518) and now considering 3/1020 (removed 1017) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 53 ms. Remains : 2/1520 places, 3/1020 transitions.
[2023-03-16 20:43:57] [INFO ] Flatten gal took : 1 ms
[2023-03-16 20:43:57] [INFO ] Flatten gal took : 0 ms
[2023-03-16 20:43:57] [INFO ] Input system was already deterministic with 3 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 44 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 45 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:43:57] [INFO ] Flatten gal took : 595 ms
[2023-03-16 20:43:58] [INFO ] Flatten gal took : 624 ms
[2023-03-16 20:43:58] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 62 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 63 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:43:59] [INFO ] Flatten gal took : 573 ms
[2023-03-16 20:43:59] [INFO ] Flatten gal took : 566 ms
[2023-03-16 20:43:59] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 77 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 77 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:44:00] [INFO ] Flatten gal took : 568 ms
[2023-03-16 20:44:01] [INFO ] Flatten gal took : 567 ms
[2023-03-16 20:44:01] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 73 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 73 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:44:02] [INFO ] Flatten gal took : 572 ms
[2023-03-16 20:44:02] [INFO ] Flatten gal took : 565 ms
[2023-03-16 20:44:02] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 52 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 53 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:44:03] [INFO ] Flatten gal took : 575 ms
[2023-03-16 20:44:03] [INFO ] Flatten gal took : 619 ms
[2023-03-16 20:44:04] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 52 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 52 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:44:04] [INFO ] Flatten gal took : 560 ms
[2023-03-16 20:44:05] [INFO ] Flatten gal took : 569 ms
[2023-03-16 20:44:05] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Drop transitions removed 498 transitions
Trivial Post-agglo rules discarded 498 transitions
Performed 498 trivial Post agglomeration. Transition count delta: 498
Iterating post reduction 0 with 498 rules applied. Total rules applied 498 place count 1520 transition count 522
Reduce places removed 996 places and 0 transitions.
Iterating post reduction 1 with 996 rules applied. Total rules applied 1494 place count 524 transition count 522
Applied a total of 1494 rules in 218 ms. Remains 524 /1520 variables (removed 996) and now considering 522/1020 (removed 498) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 219 ms. Remains : 524/1520 places, 522/1020 transitions.
[2023-03-16 20:44:06] [INFO ] Flatten gal took : 545 ms
[2023-03-16 20:44:06] [INFO ] Flatten gal took : 529 ms
[2023-03-16 20:44:06] [INFO ] Input system was already deterministic with 522 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 76 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 77 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:44:07] [INFO ] Flatten gal took : 578 ms
[2023-03-16 20:44:08] [INFO ] Flatten gal took : 562 ms
[2023-03-16 20:44:08] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 63 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 64 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:44:08] [INFO ] Flatten gal took : 576 ms
[2023-03-16 20:44:09] [INFO ] Flatten gal took : 568 ms
[2023-03-16 20:44:09] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Drop transitions removed 497 transitions
Trivial Post-agglo rules discarded 497 transitions
Performed 497 trivial Post agglomeration. Transition count delta: 497
Iterating post reduction 0 with 497 rules applied. Total rules applied 497 place count 1520 transition count 523
Reduce places removed 994 places and 0 transitions.
Iterating post reduction 1 with 994 rules applied. Total rules applied 1491 place count 526 transition count 523
Applied a total of 1491 rules in 134 ms. Remains 526 /1520 variables (removed 994) and now considering 523/1020 (removed 497) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 135 ms. Remains : 526/1520 places, 523/1020 transitions.
[2023-03-16 20:44:10] [INFO ] Flatten gal took : 543 ms
[2023-03-16 20:44:10] [INFO ] Flatten gal took : 528 ms
[2023-03-16 20:44:11] [INFO ] Input system was already deterministic with 523 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 64 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 65 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:44:11] [INFO ] Flatten gal took : 565 ms
[2023-03-16 20:44:12] [INFO ] Flatten gal took : 579 ms
[2023-03-16 20:44:12] [INFO ] Input system was already deterministic with 1020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 62 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 62 ms. Remains : 1520/1520 places, 1020/1020 transitions.
[2023-03-16 20:44:13] [INFO ] Flatten gal took : 569 ms
[2023-03-16 20:44:13] [INFO ] Flatten gal took : 642 ms
[2023-03-16 20:44:13] [INFO ] Input system was already deterministic with 1020 transitions.
[2023-03-16 20:44:14] [INFO ] Flatten gal took : 673 ms
[2023-03-16 20:44:15] [INFO ] Flatten gal took : 664 ms
[2023-03-16 20:44:15] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 9 ms.
[2023-03-16 20:44:15] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1520 places, 1020 transitions and 13040 arcs took 17 ms.
Total runtime 33741 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RwMutex-PT-r0500w0010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA RwMutex-PT-r0500w0010-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0500w0010-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0500w0010-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0500w0010-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678999747646

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
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lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
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lola: RELEASE
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lola: Created skeleton in 0.000000 secs.
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lola: Created skeleton in 0.000000 secs.
lola: RELEASE
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lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 53 (type EXCL) for 10 RwMutex-PT-r0500w0010-CTLFireability-02
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type EXCL) for RwMutex-PT-r0500w0010-CTLFireability-02
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: LAUNCH task # 32 (type EXCL) for 31 RwMutex-PT-r0500w0010-CTLFireability-09
lola: time limit : 223 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for RwMutex-PT-r0500w0010-CTLFireability-09
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 14 (type EXCL) for 13 RwMutex-PT-r0500w0010-CTLFireability-03
lola: time limit : 238 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0500w0010-CTLFireability-02: AGAF false state space /EFEG
RwMutex-PT-r0500w0010-CTLFireability-09: AGEF true tscc_search

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0500w0010-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 2/238 1/32 RwMutex-PT-r0500w0010-CTLFireability-03 62904 m, 12580 m/sec, 433700 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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14 CTL EXCL 7/238 2/32 RwMutex-PT-r0500w0010-CTLFireability-03 215691 m, 30557 m/sec, 1554447 t fired, .

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RwMutex-PT-r0500w0010-CTLFireability-09: AGEF true tscc_search

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RwMutex-PT-r0500w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
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RwMutex-PT-r0500w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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14 CTL EXCL 12/238 3/32 RwMutex-PT-r0500w0010-CTLFireability-03 371410 m, 31143 m/sec, 2676169 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0500w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
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RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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14 CTL EXCL 17/238 4/32 RwMutex-PT-r0500w0010-CTLFireability-03 520207 m, 29759 m/sec, 3767606 t fired, .

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RwMutex-PT-r0500w0010-CTLFireability-09: AGEF true tscc_search

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0500w0010-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 22/238 5/32 RwMutex-PT-r0500w0010-CTLFireability-03 667570 m, 29472 m/sec, 4881385 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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14 CTL EXCL 27/238 6/32 RwMutex-PT-r0500w0010-CTLFireability-03 816909 m, 29867 m/sec, 5993846 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0500w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
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RwMutex-PT-r0500w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r0500w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 32/238 8/32 RwMutex-PT-r0500w0010-CTLFireability-03 969587 m, 30535 m/sec, 7112545 t fired, .

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RwMutex-PT-r0500w0010-CTLFireability-09: AGEF true tscc_search

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0500w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
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RwMutex-PT-r0500w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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14 CTL EXCL 37/238 9/32 RwMutex-PT-r0500w0010-CTLFireability-03 1116790 m, 29440 m/sec, 8228723 t fired, .

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48 CTL EXCL 15/311 4/32 RwMutex-PT-r0500w0010-CTLFireability-13 492305 m, 32482 m/sec, 2680940 t fired, .

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48 CTL EXCL 20/311 5/32 RwMutex-PT-r0500w0010-CTLFireability-13 647896 m, 31118 m/sec, 3576816 t fired, .

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48 CTL EXCL 25/311 6/32 RwMutex-PT-r0500w0010-CTLFireability-13 807215 m, 31863 m/sec, 4466605 t fired, .

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48 CTL EXCL 30/311 8/32 RwMutex-PT-r0500w0010-CTLFireability-13 967872 m, 32131 m/sec, 5368499 t fired, .

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48 CTL EXCL 35/311 9/32 RwMutex-PT-r0500w0010-CTLFireability-13 1122860 m, 30997 m/sec, 6268968 t fired, .

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48 CTL EXCL 40/311 10/32 RwMutex-PT-r0500w0010-CTLFireability-13 1271180 m, 29664 m/sec, 7143535 t fired, .

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48 CTL EXCL 45/311 10/32 RwMutex-PT-r0500w0010-CTLFireability-13 1350047 m, 15773 m/sec, 7583010 t fired, .

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48 CTL EXCL 50/311 11/32 RwMutex-PT-r0500w0010-CTLFireability-13 1471145 m, 24219 m/sec, 8266815 t fired, .

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48 CTL EXCL 55/311 11/32 RwMutex-PT-r0500w0010-CTLFireability-13 1515363 m, 8843 m/sec, 8528383 t fired, .

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48 CTL EXCL 60/311 12/32 RwMutex-PT-r0500w0010-CTLFireability-13 1616912 m, 20309 m/sec, 9105607 t fired, .

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48 CTL EXCL 65/311 13/32 RwMutex-PT-r0500w0010-CTLFireability-13 1684298 m, 13477 m/sec, 9480798 t fired, .

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48 CTL EXCL 84/311 14/32 RwMutex-PT-r0500w0010-CTLFireability-13 1906883 m, 11723 m/sec, 10750370 t fired, .

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RwMutex-PT-r0500w0010-CTLFireability-01: CONJ false state space /EXEG
RwMutex-PT-r0500w0010-CTLFireability-02: AGAF false state space /EFEG
RwMutex-PT-r0500w0010-CTLFireability-09: AGEF true tscc_search
RwMutex-PT-r0500w0010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0500w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0500w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 93/311 15/32 RwMutex-PT-r0500w0010-CTLFireability-13 2028817 m, 24386 m/sec, 11421267 t fired, .

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RwMutex-PT-r0500w0010-CTLFireability-01: CONJ false state space /EXEG
RwMutex-PT-r0500w0010-CTLFireability-02: AGAF false state space /EFEG
RwMutex-PT-r0500w0010-CTLFireability-09: AGEF true tscc_search
RwMutex-PT-r0500w0010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0500w0010-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0500w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 98/311 16/32 RwMutex-PT-r0500w0010-CTLFireability-13 2111458 m, 16528 m/sec, 11889913 t fired, .

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RwMutex-PT-r0500w0010-CTLFireability-01: CONJ false state space /EXEG
RwMutex-PT-r0500w0010-CTLFireability-02: AGAF false state space /EFEG
RwMutex-PT-r0500w0010-CTLFireability-09: AGEF true tscc_search
RwMutex-PT-r0500w0010-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0500w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0500w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

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48 CTL EXCL 103/311 16/32 RwMutex-PT-r0500w0010-CTLFireability-13 2184802 m, 14668 m/sec, 12321264 t fired, .

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RwMutex-PT-r0500w0010-CTLFireability-02: AGAF false state space /EFEG
RwMutex-PT-r0500w0010-CTLFireability-09: AGEF true tscc_search
RwMutex-PT-r0500w0010-CTLFireability-15: CTL false CTL model checker

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RwMutex-PT-r0500w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

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48 CTL EXCL 108/311 17/32 RwMutex-PT-r0500w0010-CTLFireability-13 2242297 m, 11499 m/sec, 12666180 t fired, .

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RwMutex-PT-r0500w0010-CTLFireability-01: CONJ false state space /EXEG
RwMutex-PT-r0500w0010-CTLFireability-02: AGAF false state space /EFEG
RwMutex-PT-r0500w0010-CTLFireability-09: AGEF true tscc_search
RwMutex-PT-r0500w0010-CTLFireability-15: CTL false CTL model checker

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RwMutex-PT-r0500w0010-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0500w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0500w0010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

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48 CTL EXCL 113/311 17/32 RwMutex-PT-r0500w0010-CTLFireability-13 2309479 m, 13436 m/sec, 13033182 t fired, .

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/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 476 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0500w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RwMutex-PT-r0500w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808600178"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0500w0010.tgz
mv RwMutex-PT-r0500w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;