Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808500170.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RwMutex-PT-r0100w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808500170
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 696K
-rw-r--r-- 1 mcc users 5.6K Feb 25 22:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Feb 25 22:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 25 22:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 22:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 16:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 22:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Feb 25 22:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 22:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 100K Feb 25 22:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 215K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-00
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-01
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-02
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-03
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-04
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-05
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-06
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-07
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-08
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-09
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-10
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-11
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-12
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-13
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-14
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678999180095

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r0100w0010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 20:39:43] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 20:39:43] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 20:39:43] [INFO ] Load time of PNML (sax parser for PT used): 208 ms
[2023-03-16 20:39:43] [INFO ] Transformed 320 places.
[2023-03-16 20:39:44] [INFO ] Transformed 220 transitions.
[2023-03-16 20:39:44] [INFO ] Found NUPN structural information;
[2023-03-16 20:39:44] [INFO ] Parsed PT model containing 320 places and 220 transitions and 2640 arcs in 428 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 22 ms.
Initial state reduction rules removed 1 formulas.
FORMULA RwMutex-PT-r0100w0010-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 180 out of 320 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 320/320 places, 220/220 transitions.
Applied a total of 0 rules in 56 ms. Remains 320 /320 variables (removed 0) and now considering 220/220 (removed 0) transitions.
// Phase 1: matrix 220 rows 320 cols
[2023-03-16 20:39:44] [INFO ] Computed 210 place invariants in 36 ms
[2023-03-16 20:39:44] [INFO ] Implicit Places using invariants in 731 ms returned [265]
Discarding 1 places :
Implicit Place search using SMT only with invariants took 802 ms to find 1 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 319/320 places, 220/220 transitions.
Applied a total of 0 rules in 35 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 895 ms. Remains : 319/320 places, 220/220 transitions.
Support contains 180 out of 319 places after structural reductions.
[2023-03-16 20:39:45] [INFO ] Flatten gal took : 328 ms
[2023-03-16 20:39:45] [INFO ] Flatten gal took : 141 ms
[2023-03-16 20:39:46] [INFO ] Input system was already deterministic with 220 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 667 ms. (steps per millisecond=14 ) properties (out of 65) seen :63
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 220 rows 319 cols
[2023-03-16 20:39:47] [INFO ] Computed 209 place invariants in 10 ms
[2023-03-16 20:39:47] [INFO ] After 172ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 20:39:47] [INFO ] [Nat]Absence check using 209 positive place invariants in 64 ms returned sat
[2023-03-16 20:39:47] [INFO ] After 213ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 15 simplifications.
[2023-03-16 20:39:47] [INFO ] Flatten gal took : 65 ms
[2023-03-16 20:39:47] [INFO ] Flatten gal took : 63 ms
[2023-03-16 20:39:47] [INFO ] Input system was already deterministic with 220 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 20 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 20 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:47] [INFO ] Flatten gal took : 43 ms
[2023-03-16 20:39:47] [INFO ] Flatten gal took : 44 ms
[2023-03-16 20:39:47] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 8 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:47] [INFO ] Flatten gal took : 40 ms
[2023-03-16 20:39:47] [INFO ] Flatten gal took : 41 ms
[2023-03-16 20:39:48] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 8 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 37 ms
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 48 ms
[2023-03-16 20:39:48] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 8 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 36 ms
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 44 ms
[2023-03-16 20:39:48] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 8 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 35 ms
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 44 ms
[2023-03-16 20:39:48] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 6 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 36 ms
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 38 ms
[2023-03-16 20:39:48] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 6 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 35 ms
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 38 ms
[2023-03-16 20:39:48] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Graph (trivial) has 2 edges and 319 vertex of which 2 / 319 are part of one of the 1 SCC in 4 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 91 transitions
Trivial Post-agglo rules discarded 91 transitions
Performed 91 trivial Post agglomeration. Transition count delta: 91
Iterating post reduction 0 with 91 rules applied. Total rules applied 92 place count 318 transition count 128
Reduce places removed 182 places and 0 transitions.
Iterating post reduction 1 with 182 rules applied. Total rules applied 274 place count 136 transition count 128
Applied a total of 274 rules in 52 ms. Remains 136 /319 variables (removed 183) and now considering 128/220 (removed 92) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 52 ms. Remains : 136/319 places, 128/220 transitions.
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 35 ms
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 30 ms
[2023-03-16 20:39:48] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 8 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:48] [INFO ] Flatten gal took : 36 ms
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 35 ms
[2023-03-16 20:39:49] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 8 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 33 ms
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 35 ms
[2023-03-16 20:39:49] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Graph (trivial) has 2 edges and 319 vertex of which 2 / 319 are part of one of the 1 SCC in 1 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 98 transitions
Trivial Post-agglo rules discarded 98 transitions
Performed 98 trivial Post agglomeration. Transition count delta: 98
Iterating post reduction 0 with 98 rules applied. Total rules applied 99 place count 318 transition count 121
Reduce places removed 196 places and 0 transitions.
Iterating post reduction 1 with 196 rules applied. Total rules applied 295 place count 122 transition count 121
Applied a total of 295 rules in 33 ms. Remains 122 /319 variables (removed 197) and now considering 121/220 (removed 99) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 34 ms. Remains : 122/319 places, 121/220 transitions.
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 30 ms
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 30 ms
[2023-03-16 20:39:49] [INFO ] Input system was already deterministic with 121 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 4 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 34 ms
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 37 ms
[2023-03-16 20:39:49] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Graph (trivial) has 2 edges and 319 vertex of which 2 / 319 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 108 transitions
Trivial Post-agglo rules discarded 108 transitions
Performed 108 trivial Post agglomeration. Transition count delta: 108
Iterating post reduction 0 with 108 rules applied. Total rules applied 109 place count 318 transition count 111
Reduce places removed 315 places and 0 transitions.
Ensure Unique test removed 107 transitions
Reduce isomorphic transitions removed 107 transitions.
Iterating post reduction 1 with 422 rules applied. Total rules applied 531 place count 3 transition count 4
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 532 place count 3 transition count 3
Ensure Unique test removed 1 places
Iterating post reduction 2 with 1 rules applied. Total rules applied 533 place count 2 transition count 3
Applied a total of 533 rules in 11 ms. Remains 2 /319 variables (removed 317) and now considering 3/220 (removed 217) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 2/319 places, 3/220 transitions.
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 0 ms
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 0 ms
[2023-03-16 20:39:49] [INFO ] Input system was already deterministic with 3 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 4 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 35 ms
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 35 ms
[2023-03-16 20:39:49] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in LTL mode, iteration 0 : 319/319 places, 220/220 transitions.
Applied a total of 0 rules in 4 ms. Remains 319 /319 variables (removed 0) and now considering 220/220 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 319/319 places, 220/220 transitions.
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 40 ms
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 42 ms
[2023-03-16 20:39:49] [INFO ] Input system was already deterministic with 220 transitions.
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 35 ms
[2023-03-16 20:39:49] [INFO ] Flatten gal took : 36 ms
[2023-03-16 20:39:49] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 7 ms.
[2023-03-16 20:39:49] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 319 places, 220 transitions and 2638 arcs took 5 ms.
Total runtime 6282 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RwMutex-PT-r0100w0010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA RwMutex-PT-r0100w0010-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0100w0010-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0100w0010-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0100w0010-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0100w0010-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0100w0010-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0100w0010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0100w0010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0100w0010-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0100w0010-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678999372549

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/211 8/32 RwMutex-PT-r0100w0010-CTLFireability-08 1617296 m, 323459 m/sec, 1918095 t fired, .

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37 CTL EXCL 10/211 17/32 RwMutex-PT-r0100w0010-CTLFireability-08 3578662 m, 392273 m/sec, 4008694 t fired, .

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37 CTL EXCL 15/211 26/32 RwMutex-PT-r0100w0010-CTLFireability-08 5548183 m, 393904 m/sec, 6116110 t fired, .

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55 CTL EXCL 10/223 20/32 RwMutex-PT-r0100w0010-CTLFireability-15 4129053 m, 408091 m/sec, 6235113 t fired, .

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55 CTL EXCL 15/223 30/32 RwMutex-PT-r0100w0010-CTLFireability-15 6114095 m, 397008 m/sec, 9395078 t fired, .

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52 CTL EXCL 5/237 4/32 RwMutex-PT-r0100w0010-CTLFireability-14 642338 m, 128467 m/sec, 2383524 t fired, .

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52 CTL EXCL 10/237 7/32 RwMutex-PT-r0100w0010-CTLFireability-14 1252235 m, 121979 m/sec, 4721424 t fired, .

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52 CTL EXCL 15/237 10/32 RwMutex-PT-r0100w0010-CTLFireability-14 1844395 m, 118432 m/sec, 7056101 t fired, .

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52 CTL EXCL 20/237 13/32 RwMutex-PT-r0100w0010-CTLFireability-14 2425685 m, 116258 m/sec, 9394536 t fired, .

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52 CTL EXCL 25/237 16/32 RwMutex-PT-r0100w0010-CTLFireability-14 3017942 m, 118451 m/sec, 11777772 t fired, .

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52 CTL EXCL 30/237 19/32 RwMutex-PT-r0100w0010-CTLFireability-14 3591781 m, 114767 m/sec, 14122268 t fired, .

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52 CTL EXCL 35/237 22/32 RwMutex-PT-r0100w0010-CTLFireability-14 4151622 m, 111968 m/sec, 16442329 t fired, .

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52 CTL EXCL 40/237 24/32 RwMutex-PT-r0100w0010-CTLFireability-14 4705520 m, 110779 m/sec, 18730216 t fired, .

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52 CTL EXCL 45/237 27/32 RwMutex-PT-r0100w0010-CTLFireability-14 5226645 m, 104225 m/sec, 20972634 t fired, .

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52 CTL EXCL 50/237 29/32 RwMutex-PT-r0100w0010-CTLFireability-14 5760803 m, 106831 m/sec, 23187426 t fired, .

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52 CTL EXCL 55/237 32/32 RwMutex-PT-r0100w0010-CTLFireability-14 6273660 m, 102571 m/sec, 25335051 t fired, .

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RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 55/434 28/32 RwMutex-PT-r0100w0010-CTLFireability-03 5215370 m, 184997 m/sec, 20718642 t fired, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 14 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 11 (type EXCL) for 10 RwMutex-PT-r0100w0010-CTLFireability-02
lola: time limit : 488 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-02
lola: result : false
lola: markings : 5
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 8 (type EXCL) for 7 RwMutex-PT-r0100w0010-CTLFireability-01
lola: time limit : 569 sec
lola: memory limit: 32 pages
lola: FINISHED task # 8 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-01
lola: result : false
lola: markings : 162
lola: fired transitions : 737
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 RwMutex-PT-r0100w0010-CTLFireability-10
lola: time limit : 683 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-10
lola: result : true
lola: markings : 12
lola: fired transitions : 121
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 0 RwMutex-PT-r0100w0010-CTLFireability-00
lola: time limit : 854 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-00
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 RwMutex-PT-r0100w0010-CTLFireability-12
lola: time limit : 1139 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-12
lola: result : false
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 29 RwMutex-PT-r0100w0010-CTLFireability-07
lola: time limit : 1709 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-07
lola: result : false
lola: markings : 5
lola: fired transitions : 159
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 29 RwMutex-PT-r0100w0010-CTLFireability-07
lola: time limit : 3419 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-07
lola: result : true
lola: markings : 42
lola: fired transitions : 3357
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ false tscc_search
RwMutex-PT-r0100w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-03: CTL unknown AGGR
RwMutex-PT-r0100w0010-CTLFireability-04: CTL unknown AGGR
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-08: CTL unknown AGGR
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF true tscc_search
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: CTL unknown AGGR
RwMutex-PT-r0100w0010-CTLFireability-15: CTL unknown AGGR


Time elapsed: 181 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0100w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RwMutex-PT-r0100w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808500170"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0100w0010.tgz
mv RwMutex-PT-r0100w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;