About the Execution of LoLa+red for RwMutex-PT-r0020w0010
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1118.436 | 158754.00 | 166194.00 | 876.40 | TFFFFFFTTFFTFFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808500162.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RwMutex-PT-r0020w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808500162
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 476K
-rw-r--r-- 1 mcc users 6.3K Feb 25 22:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 22:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 25 22:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 25 22:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 22:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 25 22:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 25 22:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 25 22:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 47K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-00
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-01
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-02
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-03
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-04
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-05
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-06
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-07
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-08
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-09
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-10
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-11
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-12
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-13
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-14
FORMULA_NAME RwMutex-PT-r0020w0010-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678998919081
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r0020w0010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 20:35:21] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 20:35:21] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 20:35:21] [INFO ] Load time of PNML (sax parser for PT used): 265 ms
[2023-03-16 20:35:21] [INFO ] Transformed 80 places.
[2023-03-16 20:35:21] [INFO ] Transformed 60 transitions.
[2023-03-16 20:35:21] [INFO ] Found NUPN structural information;
[2023-03-16 20:35:21] [INFO ] Parsed PT model containing 80 places and 60 transitions and 560 arcs in 433 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
Initial state reduction rules removed 4 formulas.
FORMULA RwMutex-PT-r0020w0010-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0020w0010-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0020w0010-CTLFireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0020w0010-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 69 out of 80 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 60/60 transitions.
Applied a total of 0 rules in 17 ms. Remains 80 /80 variables (removed 0) and now considering 60/60 (removed 0) transitions.
// Phase 1: matrix 60 rows 80 cols
[2023-03-16 20:35:22] [INFO ] Computed 50 place invariants in 16 ms
[2023-03-16 20:35:22] [INFO ] Implicit Places using invariants in 303 ms returned [4, 6, 7, 16, 17, 22, 44]
Discarding 7 places :
Implicit Place search using SMT only with invariants took 345 ms to find 7 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 73/80 places, 60/60 transitions.
Applied a total of 0 rules in 2 ms. Remains 73 /73 variables (removed 0) and now considering 60/60 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 365 ms. Remains : 73/80 places, 60/60 transitions.
Support contains 69 out of 73 places after structural reductions.
[2023-03-16 20:35:22] [INFO ] Flatten gal took : 64 ms
[2023-03-16 20:35:22] [INFO ] Flatten gal took : 25 ms
[2023-03-16 20:35:22] [INFO ] Input system was already deterministic with 60 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 709 ms. (steps per millisecond=14 ) properties (out of 61) seen :52
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 9) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 8) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
// Phase 1: matrix 60 rows 73 cols
[2023-03-16 20:35:23] [INFO ] Computed 43 place invariants in 3 ms
[2023-03-16 20:35:23] [INFO ] [Real]Absence check using 43 positive place invariants in 14 ms returned sat
[2023-03-16 20:35:23] [INFO ] After 134ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:1
[2023-03-16 20:35:24] [INFO ] [Nat]Absence check using 43 positive place invariants in 17 ms returned sat
[2023-03-16 20:35:24] [INFO ] After 84ms SMT Verify possible using all constraints in natural domain returned unsat :4 sat :0
Fused 4 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 4 atomic propositions for a total of 12 simplifications.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 20 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 19 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 60 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Graph (trivial) has 6 edges and 73 vertex of which 6 / 73 are part of one of the 3 SCC in 3 ms
Free SCC test removed 3 places
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded 12 transitions
Performed 12 trivial Post agglomeration. Transition count delta: 12
Iterating post reduction 0 with 12 rules applied. Total rules applied 13 place count 70 transition count 45
Reduce places removed 24 places and 0 transitions.
Iterating post reduction 1 with 24 rules applied. Total rules applied 37 place count 46 transition count 45
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 38 place count 45 transition count 44
Iterating global reduction 2 with 1 rules applied. Total rules applied 39 place count 45 transition count 44
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 40 place count 45 transition count 43
Applied a total of 40 rules in 29 ms. Remains 45 /73 variables (removed 28) and now considering 43/60 (removed 17) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 45/73 places, 43/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 16 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 10 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 43 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 72 transition count 59
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 72 transition count 59
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 72 transition count 58
Applied a total of 3 rules in 12 ms. Remains 72 /73 variables (removed 1) and now considering 58/60 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 72/73 places, 58/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 11 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 12 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 58 transitions.
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 72 transition count 59
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 72 transition count 59
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 72 transition count 58
Applied a total of 3 rules in 6 ms. Remains 72 /73 variables (removed 1) and now considering 58/60 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 72/73 places, 58/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 10 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 11 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 58 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 72 transition count 59
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 72 transition count 59
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 72 transition count 58
Applied a total of 3 rules in 12 ms. Remains 72 /73 variables (removed 1) and now considering 58/60 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 72/73 places, 58/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 10 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 11 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 58 transitions.
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 72 transition count 59
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 72 transition count 59
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 72 transition count 58
Applied a total of 3 rules in 7 ms. Remains 72 /73 variables (removed 1) and now considering 58/60 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 72/73 places, 58/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 8 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 9 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 58 transitions.
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 72 transition count 59
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 72 transition count 59
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 72 transition count 58
Applied a total of 3 rules in 6 ms. Remains 72 /73 variables (removed 1) and now considering 58/60 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 72/73 places, 58/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 7 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 8 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 58 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Graph (trivial) has 10 edges and 73 vertex of which 10 / 73 are part of one of the 5 SCC in 0 ms
Free SCC test removed 5 places
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 14 transitions
Trivial Post-agglo rules discarded 14 transitions
Performed 14 trivial Post agglomeration. Transition count delta: 14
Iterating post reduction 0 with 14 rules applied. Total rules applied 15 place count 68 transition count 41
Reduce places removed 28 places and 0 transitions.
Iterating post reduction 1 with 28 rules applied. Total rules applied 43 place count 40 transition count 41
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 44 place count 39 transition count 40
Iterating global reduction 2 with 1 rules applied. Total rules applied 45 place count 39 transition count 40
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 46 place count 39 transition count 39
Applied a total of 46 rules in 13 ms. Remains 39 /73 variables (removed 34) and now considering 39/60 (removed 21) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 39/73 places, 39/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 6 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 6 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 39 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=0 )
FORMULA RwMutex-PT-r0020w0010-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 72 transition count 59
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 72 transition count 59
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 72 transition count 58
Applied a total of 3 rules in 6 ms. Remains 72 /73 variables (removed 1) and now considering 58/60 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 72/73 places, 58/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 8 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 6 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 58 transitions.
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Applied a total of 0 rules in 1 ms. Remains 73 /73 variables (removed 0) and now considering 60/60 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 73/73 places, 60/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 8 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 8 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 72 transition count 59
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 72 transition count 59
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 72 transition count 58
Applied a total of 3 rules in 4 ms. Remains 72 /73 variables (removed 1) and now considering 58/60 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 72/73 places, 58/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 7 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 7 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 58 transitions.
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Applied a total of 0 rules in 2 ms. Remains 73 /73 variables (removed 0) and now considering 60/60 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 73/73 places, 60/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 6 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 7 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 60/60 transitions.
Applied a total of 0 rules in 2 ms. Remains 73 /73 variables (removed 0) and now considering 60/60 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 73/73 places, 60/60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 6 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 7 ms
[2023-03-16 20:35:24] [INFO ] Input system was already deterministic with 60 transitions.
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 8 ms
[2023-03-16 20:35:24] [INFO ] Flatten gal took : 8 ms
[2023-03-16 20:35:24] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 8 ms.
[2023-03-16 20:35:24] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 73 places, 60 transitions and 546 arcs took 1 ms.
Total runtime 3448 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RwMutex-PT-r0020w0010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA RwMutex-PT-r0020w0010-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0020w0010-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0020w0010-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0020w0010-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0020w0010-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0020w0010-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0020w0010-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0020w0010-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0020w0010-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0020w0010-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0020w0010-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678999077835
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
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lola: Rule S: 0 transitions removed,0 places removed
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lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 4 (type EXCL) for 3 RwMutex-PT-r0020w0010-CTLFireability-01
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ 0 3 0 0 3 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/276 5/32 RwMutex-PT-r0020w0010-CTLFireability-01 1037894 m, 207578 m/sec, 6733237 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ 0 3 0 0 3 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/276 5/32 RwMutex-PT-r0020w0010-CTLFireability-01 1048510 m, 2123 m/sec, 13654130 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ 0 3 0 0 3 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/276 5/32 RwMutex-PT-r0020w0010-CTLFireability-01 1048586 m, 15 m/sec, 21226031 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ 0 3 0 0 3 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/276 5/32 RwMutex-PT-r0020w0010-CTLFireability-01 1048586 m, 0 m/sec, 28114597 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ 0 3 0 0 3 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/276 5/32 RwMutex-PT-r0020w0010-CTLFireability-01 1048586 m, 0 m/sec, 35056895 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ 0 3 0 0 3 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/276 5/32 RwMutex-PT-r0020w0010-CTLFireability-01 1048586 m, 0 m/sec, 42047078 t fired, .
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lola: FINISHED task # 4 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-01
lola: result : false
lola: markings : 1048586
lola: fired transitions : 49440133
lola: time used : 35.000000
lola: memory pages used : 5
lola: LAUNCH task # 41 (type EXCL) for 24 RwMutex-PT-r0020w0010-CTLFireability-10
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-10
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 RwMutex-PT-r0020w0010-CTLFireability-15
lola: time limit : 396 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 0/396 1/32 RwMutex-PT-r0020w0010-CTLFireability-15 31046 m, 6209 m/sec, 144663 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 5/396 5/32 RwMutex-PT-r0020w0010-CTLFireability-15 1033114 m, 200413 m/sec, 6443091 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 10/396 5/32 RwMutex-PT-r0020w0010-CTLFireability-15 1048499 m, 3077 m/sec, 13330410 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 15/396 5/32 RwMutex-PT-r0020w0010-CTLFireability-15 1048577 m, 15 m/sec, 20732098 t fired, .
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lola: FINISHED task # 39 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-15
lola: result : false
lola: markings : 1048586
lola: fired transitions : 21766183
lola: time used : 15.000000
lola: memory pages used : 5
lola: LAUNCH task # 36 (type EXCL) for 35 RwMutex-PT-r0020w0010-CTLFireability-12
lola: time limit : 443 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-12
lola: result : false
lola: markings : 31
lola: fired transitions : 61
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 RwMutex-PT-r0020w0010-CTLFireability-08
lola: time limit : 507 sec
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/507 2/32 RwMutex-PT-r0020w0010-CTLFireability-08 430247 m, 86049 m/sec, 3387163 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/507 4/32 RwMutex-PT-r0020w0010-CTLFireability-08 822081 m, 78366 m/sec, 7734137 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
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RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
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RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/507 5/32 RwMutex-PT-r0020w0010-CTLFireability-08 1003792 m, 36342 m/sec, 12980384 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
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RwMutex-PT-r0020w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/507 5/32 RwMutex-PT-r0020w0010-CTLFireability-08 1035313 m, 6304 m/sec, 19336158 t fired, .
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lola: FINISHED task # 22 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-08
lola: result : true
lola: markings : 1048586
lola: fired transitions : 22770378
lola: time used : 22.000000
lola: memory pages used : 5
lola: LAUNCH task # 16 (type EXCL) for 15 RwMutex-PT-r0020w0010-CTLFireability-05
lola: time limit : 587 sec
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lola: FINISHED task # 16 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-05
lola: result : false
lola: markings : 1
lola: fired transitions : 2
lola: time used : 0.000000
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 3/705 2/32 RwMutex-PT-r0020w0010-CTLFireability-04 364186 m, 72837 m/sec, 3050636 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
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RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 8/705 3/32 RwMutex-PT-r0020w0010-CTLFireability-04 705295 m, 68221 m/sec, 8434175 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 13/705 4/32 RwMutex-PT-r0020w0010-CTLFireability-04 874135 m, 33768 m/sec, 13465537 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
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RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 18/705 4/32 RwMutex-PT-r0020w0010-CTLFireability-04 994968 m, 24166 m/sec, 18485536 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
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RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
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RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 23/705 5/32 RwMutex-PT-r0020w0010-CTLFireability-04 1048444 m, 10695 m/sec, 23600866 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
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RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 28/705 5/32 RwMutex-PT-r0020w0010-CTLFireability-04 1048571 m, 25 m/sec, 29992738 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 33/705 5/32 RwMutex-PT-r0020w0010-CTLFireability-04 1048586 m, 3 m/sec, 36630579 t fired, .
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lola: FINISHED task # 13 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-04
lola: result : false
lola: markings : 1048586
lola: fired transitions : 38723890
lola: time used : 34.000000
lola: memory pages used : 5
lola: LAUNCH task # 7 (type EXCL) for 6 RwMutex-PT-r0020w0010-CTLFireability-02
lola: time limit : 873 sec
lola: memory limit: 32 pages
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
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RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 4/873 3/32 RwMutex-PT-r0020w0010-CTLFireability-02 597887 m, 119577 m/sec, 3647386 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 9/873 5/32 RwMutex-PT-r0020w0010-CTLFireability-02 1048435 m, 90109 m/sec, 9188290 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-04: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 14/873 5/32 RwMutex-PT-r0020w0010-CTLFireability-02 1048563 m, 25 m/sec, 16021815 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-04: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 19/873 5/32 RwMutex-PT-r0020w0010-CTLFireability-02 1048577 m, 2 m/sec, 23265283 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-04: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 24/873 5/32 RwMutex-PT-r0020w0010-CTLFireability-02 1048577 m, 0 m/sec, 30039188 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-04: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 29/873 5/32 RwMutex-PT-r0020w0010-CTLFireability-02 1048577 m, 0 m/sec, 36373462 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-04: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 34/873 5/32 RwMutex-PT-r0020w0010-CTLFireability-02 1048577 m, 0 m/sec, 43290933 t fired, .
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lola: FINISHED task # 7 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-02
lola: result : false
lola: markings : 1048586
lola: fired transitions : 45285417
lola: time used : 35.000000
lola: memory pages used : 5
lola: LAUNCH task # 19 (type EXCL) for 18 RwMutex-PT-r0020w0010-CTLFireability-07
lola: time limit : 1152 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-07
lola: result : true
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 RwMutex-PT-r0020w0010-CTLFireability-03
lola: time limit : 1729 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-04: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 4/1729 3/32 RwMutex-PT-r0020w0010-CTLFireability-03 609586 m, 121917 m/sec, 4140836 t fired, .
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RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-04: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0020w0010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0020w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 9/1729 4/32 RwMutex-PT-r0020w0010-CTLFireability-03 955883 m, 69259 m/sec, 10819798 t fired, .
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lola: FINISHED task # 10 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-03
lola: result : false
lola: markings : 1048586
lola: fired transitions : 13107253
lola: time used : 10.000000
lola: memory pages used : 5
lola: LAUNCH task # 1 (type EXCL) for 0 RwMutex-PT-r0020w0010-CTLFireability-00
lola: time limit : 3448 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for RwMutex-PT-r0020w0010-CTLFireability-00
lola: result : true
lola: markings : 9
lola: fired transitions : 58
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0020w0010-CTLFireability-00: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-03: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-04: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-07: EGEF true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-10: CONJ false state space /EXEF
RwMutex-PT-r0020w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0020w0010-CTLFireability-15: CTL false CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0020w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RwMutex-PT-r0020w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808500162"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0020w0010.tgz
mv RwMutex-PT-r0020w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;