Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808500122.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RwMutex-PT-r0010w0050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808500122
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 476K
-rw-r--r-- 1 mcc users 5.3K Feb 25 22:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 51K Feb 25 22:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Feb 25 22:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 25 22:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:48 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:48 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:48 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.9K Feb 25 22:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 25 22:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Feb 25 22:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Feb 25 22:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:48 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:48 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 95K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-00
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-01
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-02
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-03
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-04
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-05
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-06
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-07
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-08
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-09
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-10
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-11
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-12
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-13
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-14
FORMULA_NAME RwMutex-PT-r0010w0050-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678997519985

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r0010w0050
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 20:12:02] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 20:12:02] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 20:12:02] [INFO ] Load time of PNML (sax parser for PT used): 104 ms
[2023-03-16 20:12:02] [INFO ] Transformed 130 places.
[2023-03-16 20:12:02] [INFO ] Transformed 120 transitions.
[2023-03-16 20:12:02] [INFO ] Found NUPN structural information;
[2023-03-16 20:12:02] [INFO ] Parsed PT model containing 130 places and 120 transitions and 1260 arcs in 230 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 15 ms.
Initial state reduction rules removed 1 formulas.
FORMULA RwMutex-PT-r0010w0050-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 75 out of 130 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 130/130 places, 120/120 transitions.
Applied a total of 0 rules in 34 ms. Remains 130 /130 variables (removed 0) and now considering 120/120 (removed 0) transitions.
// Phase 1: matrix 120 rows 130 cols
[2023-03-16 20:12:02] [INFO ] Computed 70 place invariants in 20 ms
[2023-03-16 20:12:03] [INFO ] Implicit Places using invariants in 521 ms returned [1, 23, 34, 37, 38, 39, 42, 44, 45, 51, 52, 54, 55, 57, 62, 67, 69, 72, 76, 78, 81, 85, 86, 88, 108]
Discarding 25 places :
Implicit Place search using SMT only with invariants took 569 ms to find 25 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 105/130 places, 120/120 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 94 transition count 109
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 94 transition count 109
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 33 place count 94 transition count 98
Applied a total of 33 rules in 11 ms. Remains 94 /105 variables (removed 11) and now considering 98/120 (removed 22) transitions.
// Phase 1: matrix 98 rows 94 cols
[2023-03-16 20:12:03] [INFO ] Computed 45 place invariants in 6 ms
[2023-03-16 20:12:03] [INFO ] Implicit Places using invariants in 66 ms returned []
[2023-03-16 20:12:03] [INFO ] Invariant cache hit.
[2023-03-16 20:12:03] [INFO ] Implicit Places using invariants and state equation in 128 ms returned []
Implicit Place search using SMT with State Equation took 197 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 94/130 places, 98/120 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 812 ms. Remains : 94/130 places, 98/120 transitions.
Support contains 75 out of 94 places after structural reductions.
[2023-03-16 20:12:03] [INFO ] Flatten gal took : 73 ms
[2023-03-16 20:12:03] [INFO ] Flatten gal took : 33 ms
[2023-03-16 20:12:04] [INFO ] Input system was already deterministic with 98 transitions.
Support contains 74 out of 94 places (down from 75) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 939 ms. (steps per millisecond=10 ) properties (out of 61) seen :46
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 15) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 14) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 13) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 12) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 11) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 10) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 8) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 6) seen :1
Running SMT prover for 5 properties.
[2023-03-16 20:12:05] [INFO ] Invariant cache hit.
[2023-03-16 20:12:05] [INFO ] [Real]Absence check using 45 positive place invariants in 17 ms returned sat
[2023-03-16 20:12:05] [INFO ] After 136ms SMT Verify possible using all constraints in real domain returned unsat :5 sat :0
Fused 5 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 5 atomic propositions for a total of 15 simplifications.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 25 ms
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 25 ms
[2023-03-16 20:12:05] [INFO ] Input system was already deterministic with 98 transitions.
Support contains 59 out of 94 places (down from 61) after GAL structural reductions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 85 transition count 89
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 85 transition count 89
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 27 place count 85 transition count 80
Applied a total of 27 rules in 13 ms. Remains 85 /94 variables (removed 9) and now considering 80/98 (removed 18) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 85/94 places, 80/98 transitions.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 17 ms
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 17 ms
[2023-03-16 20:12:05] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 86 transition count 90
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 86 transition count 90
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 24 place count 86 transition count 82
Applied a total of 24 rules in 25 ms. Remains 86 /94 variables (removed 8) and now considering 82/98 (removed 16) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 86/94 places, 82/98 transitions.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 18 ms
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 16 ms
[2023-03-16 20:12:05] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 85 transition count 89
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 85 transition count 89
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 27 place count 85 transition count 80
Applied a total of 27 rules in 10 ms. Remains 85 /94 variables (removed 9) and now considering 80/98 (removed 18) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 85/94 places, 80/98 transitions.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 14 ms
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 15 ms
[2023-03-16 20:12:05] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 7 place count 87 transition count 91
Iterating global reduction 0 with 7 rules applied. Total rules applied 14 place count 87 transition count 91
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 0 with 7 rules applied. Total rules applied 21 place count 87 transition count 84
Applied a total of 21 rules in 8 ms. Remains 87 /94 variables (removed 7) and now considering 84/98 (removed 14) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 87/94 places, 84/98 transitions.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 13 ms
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 13 ms
[2023-03-16 20:12:05] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 85 transition count 89
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 85 transition count 89
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 27 place count 85 transition count 80
Applied a total of 27 rules in 5 ms. Remains 85 /94 variables (removed 9) and now considering 80/98 (removed 18) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 85/94 places, 80/98 transitions.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 10 ms
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 23 ms
[2023-03-16 20:12:05] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 85 transition count 89
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 85 transition count 89
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 27 place count 85 transition count 80
Applied a total of 27 rules in 5 ms. Remains 85 /94 variables (removed 9) and now considering 80/98 (removed 18) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 85/94 places, 80/98 transitions.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 9 ms
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 9 ms
[2023-03-16 20:12:05] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Graph (trivial) has 8 edges and 94 vertex of which 8 / 94 are part of one of the 4 SCC in 5 ms
Free SCC test removed 4 places
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 44 transitions
Trivial Post-agglo rules discarded 44 transitions
Performed 44 trivial Post agglomeration. Transition count delta: 44
Iterating post reduction 0 with 44 rules applied. Total rules applied 45 place count 90 transition count 50
Reduce places removed 78 places and 0 transitions.
Ensure Unique test removed 37 transitions
Reduce isomorphic transitions removed 37 transitions.
Iterating post reduction 1 with 115 rules applied. Total rules applied 160 place count 12 transition count 13
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 161 place count 12 transition count 12
Applied a total of 161 rules in 16 ms. Remains 12 /94 variables (removed 82) and now considering 12/98 (removed 86) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 12/94 places, 12/98 transitions.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 1 ms
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 1 ms
[2023-03-16 20:12:05] [INFO ] Input system was already deterministic with 12 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=1 )
FORMULA RwMutex-PT-r0010w0050-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 86 transition count 90
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 86 transition count 90
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 24 place count 86 transition count 82
Applied a total of 24 rules in 4 ms. Remains 86 /94 variables (removed 8) and now considering 82/98 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 86/94 places, 82/98 transitions.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 9 ms
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 9 ms
[2023-03-16 20:12:05] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Graph (trivial) has 8 edges and 94 vertex of which 8 / 94 are part of one of the 4 SCC in 0 ms
Free SCC test removed 4 places
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 43 transitions
Trivial Post-agglo rules discarded 43 transitions
Performed 43 trivial Post agglomeration. Transition count delta: 43
Iterating post reduction 0 with 43 rules applied. Total rules applied 44 place count 90 transition count 51
Reduce places removed 77 places and 0 transitions.
Ensure Unique test removed 36 transitions
Reduce isomorphic transitions removed 36 transitions.
Iterating post reduction 1 with 113 rules applied. Total rules applied 157 place count 13 transition count 15
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 158 place count 13 transition count 14
Applied a total of 158 rules in 6 ms. Remains 13 /94 variables (removed 81) and now considering 14/98 (removed 84) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 13/94 places, 14/98 transitions.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 1 ms
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 0 ms
[2023-03-16 20:12:05] [INFO ] Input system was already deterministic with 14 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 7 place count 87 transition count 91
Iterating global reduction 0 with 7 rules applied. Total rules applied 14 place count 87 transition count 91
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 0 with 7 rules applied. Total rules applied 21 place count 87 transition count 84
Applied a total of 21 rules in 4 ms. Remains 87 /94 variables (removed 7) and now considering 84/98 (removed 14) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 87/94 places, 84/98 transitions.
[2023-03-16 20:12:05] [INFO ] Flatten gal took : 16 ms
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 10 ms
[2023-03-16 20:12:06] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 86 transition count 90
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 86 transition count 90
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 24 place count 86 transition count 82
Applied a total of 24 rules in 14 ms. Remains 86 /94 variables (removed 8) and now considering 82/98 (removed 16) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 86/94 places, 82/98 transitions.
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 9 ms
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 9 ms
[2023-03-16 20:12:06] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 85 transition count 89
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 85 transition count 89
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 27 place count 85 transition count 80
Applied a total of 27 rules in 3 ms. Remains 85 /94 variables (removed 9) and now considering 80/98 (removed 18) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 85/94 places, 80/98 transitions.
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 9 ms
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 10 ms
[2023-03-16 20:12:06] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 85 transition count 89
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 85 transition count 89
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 27 place count 85 transition count 80
Applied a total of 27 rules in 3 ms. Remains 85 /94 variables (removed 9) and now considering 80/98 (removed 18) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 85/94 places, 80/98 transitions.
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 9 ms
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 9 ms
[2023-03-16 20:12:06] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 85 transition count 89
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 85 transition count 89
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 27 place count 85 transition count 80
Applied a total of 27 rules in 3 ms. Remains 85 /94 variables (removed 9) and now considering 80/98 (removed 18) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 85/94 places, 80/98 transitions.
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 8 ms
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 10 ms
[2023-03-16 20:12:06] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 98/98 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 86 transition count 90
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 86 transition count 90
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 24 place count 86 transition count 82
Applied a total of 24 rules in 3 ms. Remains 86 /94 variables (removed 8) and now considering 82/98 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 86/94 places, 82/98 transitions.
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 8 ms
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 8 ms
[2023-03-16 20:12:06] [INFO ] Input system was already deterministic with 82 transitions.
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 11 ms
[2023-03-16 20:12:06] [INFO ] Flatten gal took : 12 ms
[2023-03-16 20:12:06] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 9 ms.
[2023-03-16 20:12:06] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 94 places, 98 transitions and 968 arcs took 2 ms.
Total runtime 3987 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RwMutex-PT-r0010w0050
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/369
CTLFireability

FORMULA RwMutex-PT-r0010w0050-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w0050-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678997527863

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/369/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/369/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/369/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type SKEL/FNDP) for 18 RwMutex-PT-r0010w0050-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SKEL/EQUN) for 18 RwMutex-PT-r0010w0050-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 53 (type SKEL/SRCH) for 18 RwMutex-PT-r0010w0050-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/SRCH) for 18 RwMutex-PT-r0010w0050-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 53 (type SKEL/SRCH) for RwMutex-PT-r0010w0050-CTLFireability-07
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 51 (type FNDP) for RwMutex-PT-r0010w0050-CTLFireability-07 (obsolete)
lola: CANCELED task # 52 (type EQUN) for RwMutex-PT-r0010w0050-CTLFireability-07 (obsolete)
lola: CANCELED task # 54 (type SRCH) for RwMutex-PT-r0010w0050-CTLFireability-07 (obsolete)
lola: FINISHED task # 51 (type SKEL/FNDP) for RwMutex-PT-r0010w0050-CTLFireability-07
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 55 (type SKEL/SRCH) for 15 RwMutex-PT-r0010w0050-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: FINISHED task # 55 (type SKEL/SRCH) for RwMutex-PT-r0010w0050-CTLFireability-05
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 54 (type SKEL/SRCH) for RwMutex-PT-r0010w0050-CTLFireability-07
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 10 (type EXCL) for 9 RwMutex-PT-r0010w0050-CTLFireability-03
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-03
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 RwMutex-PT-r0010w0050-CTLFireability-02
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-02
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 RwMutex-PT-r0010w0050-CTLFireability-00
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 1 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-00
lola: result : false
lola: markings : 49
lola: fired transitions : 48
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 35 (type EXCL) for 34 RwMutex-PT-r0010w0050-CTLFireability-12
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-12
lola: result : false
lola: markings : 7
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 RwMutex-PT-r0010w0050-CTLFireability-11
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: try reading problem file /home/mcc/execution/369/CTLFireability-52.sara.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 56 (type FNDP) for 18 RwMutex-PT-r0010w0050-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 18 RwMutex-PT-r0010w0050-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type SRCH) for 18 RwMutex-PT-r0010w0050-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 59 (type SRCH) for RwMutex-PT-r0010w0050-CTLFireability-07
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 56 (type FNDP) for RwMutex-PT-r0010w0050-CTLFireability-07
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 32 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-11
lola: result : false
lola: markings : 1063
lola: fired transitions : 11382
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 57 (type EQUN) for RwMutex-PT-r0010w0050-CTLFireability-07 (obsolete)
lola: LAUNCH task # 13 (type EXCL) for 12 RwMutex-PT-r0010w0050-CTLFireability-04
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-04
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 40 RwMutex-PT-r0010w0050-CTLFireability-14
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EQUN) for RwMutex-PT-r0010w0050-CTLFireability-07
lola: result : unknown
lola: FINISHED task # 45 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-14
lola: result : false
lola: markings : 2
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807

lola: LAUNCH task # 38 (type EXCL) for 37 RwMutex-PT-r0010w0050-CTLFireability-13
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 38 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-13
lola: result : true
lola: markings : 2
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 RwMutex-PT-r0010w0050-CTLFireability-15
lola: time limit : 720 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type SKEL/EQUN) for RwMutex-PT-r0010w0050-CTLFireability-07
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 48 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-15
lola: result : true
lola: markings : 1063
lola: fired transitions : 11393
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 RwMutex-PT-r0010w0050-CTLFireability-10
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-10
lola: result : true
lola: markings : 3
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 RwMutex-PT-r0010w0050-CTLFireability-05
lola: time limit : 1200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-05
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 RwMutex-PT-r0010w0050-CTLFireability-01
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-01
lola: result : true
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 RwMutex-PT-r0010w0050-CTLFireability-09
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for RwMutex-PT-r0010w0050-CTLFireability-09
lola: result : true
lola: markings : 1
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w0050-CTLFireability-00: CTL false CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-01: CTL true CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-02: LTL/CTL true CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-03: CTL true CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-04: CTL true CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-05: CTL true CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-07: DISJ true findpath
RwMutex-PT-r0010w0050-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-11: CTL false CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-14: CONJ false CTL model checker
RwMutex-PT-r0010w0050-CTLFireability-15: CTL true CTL model checker


Time elapsed: 0 secs. Pages in use: 2

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0010w0050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RwMutex-PT-r0010w0050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808500122"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0010w0050.tgz
mv RwMutex-PT-r0010w0050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;